Path: blob/master/drivers/media/dvb/b2c2/flexcop-sram.c
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/*1* Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III2* flexcop-sram.c - functions for controlling the SRAM3* see flexcop.c for copyright information4*/5#include "flexcop.h"67static void flexcop_sram_set_chip(struct flexcop_device *fc,8flexcop_sram_type_t type)9{10flexcop_set_ibi_value(wan_ctrl_reg_71c, sram_chip, type);11}1213int flexcop_sram_init(struct flexcop_device *fc)14{15switch (fc->rev) {16case FLEXCOP_II:17case FLEXCOP_IIB:18flexcop_sram_set_chip(fc, FC_SRAM_1_32KB);19break;20case FLEXCOP_III:21flexcop_sram_set_chip(fc, FC_SRAM_1_48KB);22break;23default:24return -EINVAL;25}26return 0;27}2829int flexcop_sram_set_dest(struct flexcop_device *fc, flexcop_sram_dest_t dest,30flexcop_sram_dest_target_t target)31{32flexcop_ibi_value v;33v = fc->read_ibi_reg(fc, sram_dest_reg_714);3435if (fc->rev != FLEXCOP_III && target == FC_SRAM_DEST_TARGET_FC3_CA) {36err("SRAM destination target to available on FlexCopII(b)\n");37return -EINVAL;38}39deb_sram("sram dest: %x target: %x\n", dest, target);4041if (dest & FC_SRAM_DEST_NET)42v.sram_dest_reg_714.NET_Dest = target;43if (dest & FC_SRAM_DEST_CAI)44v.sram_dest_reg_714.CAI_Dest = target;45if (dest & FC_SRAM_DEST_CAO)46v.sram_dest_reg_714.CAO_Dest = target;47if (dest & FC_SRAM_DEST_MEDIA)48v.sram_dest_reg_714.MEDIA_Dest = target;4950fc->write_ibi_reg(fc,sram_dest_reg_714,v);51udelay(1000); /* TODO delay really necessary */5253return 0;54}55EXPORT_SYMBOL(flexcop_sram_set_dest);5657void flexcop_wan_set_speed(struct flexcop_device *fc, flexcop_wan_speed_t s)58{59flexcop_set_ibi_value(wan_ctrl_reg_71c,wan_speed_sig,s);60}61EXPORT_SYMBOL(flexcop_wan_set_speed);6263void flexcop_sram_ctrl(struct flexcop_device *fc, int usb_wan, int sramdma, int maximumfill)64{65flexcop_ibi_value v = fc->read_ibi_reg(fc,sram_dest_reg_714);66v.sram_dest_reg_714.ctrl_usb_wan = usb_wan;67v.sram_dest_reg_714.ctrl_sramdma = sramdma;68v.sram_dest_reg_714.ctrl_maximumfill = maximumfill;69fc->write_ibi_reg(fc,sram_dest_reg_714,v);70}71EXPORT_SYMBOL(flexcop_sram_ctrl);7273#if 074static void flexcop_sram_write(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)75{76int i, retries;77u32 command;7879for (i = 0; i < len; i++) {80command = bank | addr | 0x04000000 | (*buf << 0x10);8182retries = 2;8384while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {85mdelay(1);86retries--;87};8889if (retries == 0)90printk("%s: SRAM timeout\n", __func__);9192write_reg_dw(adapter, 0x700, command);9394buf++;95addr++;96}97}9899static void flex_sram_read(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)100{101int i, retries;102u32 command, value;103104for (i = 0; i < len; i++) {105command = bank | addr | 0x04008000;106107retries = 10000;108109while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {110mdelay(1);111retries--;112};113114if (retries == 0)115printk("%s: SRAM timeout\n", __func__);116117write_reg_dw(adapter, 0x700, command);118119retries = 10000;120121while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {122mdelay(1);123retries--;124};125126if (retries == 0)127printk("%s: SRAM timeout\n", __func__);128129value = read_reg_dw(adapter, 0x700) >> 0x10;130131*buf = (value & 0xff);132133addr++;134buf++;135}136}137138static void sram_write_chunk(struct adapter *adapter, u32 addr, u8 *buf, u16 len)139{140u32 bank;141142bank = 0;143144if (adapter->dw_sram_type == 0x20000) {145bank = (addr & 0x18000) << 0x0d;146}147148if (adapter->dw_sram_type == 0x00000) {149if ((addr >> 0x0f) == 0)150bank = 0x20000000;151else152bank = 0x10000000;153}154flex_sram_write(adapter, bank, addr & 0x7fff, buf, len);155}156157static void sram_read_chunk(struct adapter *adapter, u32 addr, u8 *buf, u16 len)158{159u32 bank;160bank = 0;161162if (adapter->dw_sram_type == 0x20000) {163bank = (addr & 0x18000) << 0x0d;164}165166if (adapter->dw_sram_type == 0x00000) {167if ((addr >> 0x0f) == 0)168bank = 0x20000000;169else170bank = 0x10000000;171}172flex_sram_read(adapter, bank, addr & 0x7fff, buf, len);173}174175static void sram_read(struct adapter *adapter, u32 addr, u8 *buf, u32 len)176{177u32 length;178while (len != 0) {179length = len;180/* check if the address range belongs to the same181* 32K memory chip. If not, the data is read182* from one chip at a time */183if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {184length = (((addr >> 0x0f) + 1) << 0x0f) - addr;185}186187sram_read_chunk(adapter, addr, buf, length);188addr = addr + length;189buf = buf + length;190len = len - length;191}192}193194static void sram_write(struct adapter *adapter, u32 addr, u8 *buf, u32 len)195{196u32 length;197while (len != 0) {198length = len;199200/* check if the address range belongs to the same201* 32K memory chip. If not, the data is202* written to one chip at a time */203if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {204length = (((addr >> 0x0f) + 1) << 0x0f) - addr;205}206207sram_write_chunk(adapter, addr, buf, length);208addr = addr + length;209buf = buf + length;210len = len - length;211}212}213214static void sram_set_size(struct adapter *adapter, u32 mask)215{216write_reg_dw(adapter, 0x71c,217(mask | (~0x30000 & read_reg_dw(adapter, 0x71c))));218}219220static void sram_init(struct adapter *adapter)221{222u32 tmp;223tmp = read_reg_dw(adapter, 0x71c);224write_reg_dw(adapter, 0x71c, 1);225226if (read_reg_dw(adapter, 0x71c) != 0) {227write_reg_dw(adapter, 0x71c, tmp);228adapter->dw_sram_type = tmp & 0x30000;229ddprintk("%s: dw_sram_type = %x\n", __func__, adapter->dw_sram_type);230} else {231adapter->dw_sram_type = 0x10000;232ddprintk("%s: dw_sram_type = %x\n", __func__, adapter->dw_sram_type);233}234}235236static int sram_test_location(struct adapter *adapter, u32 mask, u32 addr)237{238u8 tmp1, tmp2;239dprintk("%s: mask = %x, addr = %x\n", __func__, mask, addr);240241sram_set_size(adapter, mask);242sram_init(adapter);243244tmp2 = 0xa5;245tmp1 = 0x4f;246247sram_write(adapter, addr, &tmp2, 1);248sram_write(adapter, addr + 4, &tmp1, 1);249250tmp2 = 0;251mdelay(20);252253sram_read(adapter, addr, &tmp2, 1);254sram_read(adapter, addr, &tmp2, 1);255256dprintk("%s: wrote 0xa5, read 0x%2x\n", __func__, tmp2);257258if (tmp2 != 0xa5)259return 0;260261tmp2 = 0x5a;262tmp1 = 0xf4;263264sram_write(adapter, addr, &tmp2, 1);265sram_write(adapter, addr + 4, &tmp1, 1);266267tmp2 = 0;268mdelay(20);269270sram_read(adapter, addr, &tmp2, 1);271sram_read(adapter, addr, &tmp2, 1);272273dprintk("%s: wrote 0x5a, read 0x%2x\n", __func__, tmp2);274275if (tmp2 != 0x5a)276return 0;277return 1;278}279280static u32 sram_length(struct adapter *adapter)281{282if (adapter->dw_sram_type == 0x10000)283return 32768; /* 32K */284if (adapter->dw_sram_type == 0x00000)285return 65536; /* 64K */286if (adapter->dw_sram_type == 0x20000)287return 131072; /* 128K */288return 32768; /* 32K */289}290291/* FlexcopII can work with 32K, 64K or 128K of external SRAM memory.292- for 128K there are 4x32K chips at bank 0,1,2,3.293- for 64K there are 2x32K chips at bank 1,2.294- for 32K there is one 32K chip at bank 0.295296FlexCop works only with one bank at a time. The bank is selected297by bits 28-29 of the 0x700 register.298299bank 0 covers addresses 0x00000-0x07fff300bank 1 covers addresses 0x08000-0x0ffff301bank 2 covers addresses 0x10000-0x17fff302bank 3 covers addresses 0x18000-0x1ffff */303304static int flexcop_sram_detect(struct flexcop_device *fc)305{306flexcop_ibi_value r208, r71c_0, vr71c_1;307r208 = fc->read_ibi_reg(fc, ctrl_208);308fc->write_ibi_reg(fc, ctrl_208, ibi_zero);309310r71c_0 = fc->read_ibi_reg(fc, wan_ctrl_reg_71c);311write_reg_dw(adapter, 0x71c, 1);312tmp3 = read_reg_dw(adapter, 0x71c);313dprintk("%s: tmp3 = %x\n", __func__, tmp3);314write_reg_dw(adapter, 0x71c, tmp2);315316// check for internal SRAM ???317tmp3--;318if (tmp3 != 0) {319sram_set_size(adapter, 0x10000);320sram_init(adapter);321write_reg_dw(adapter, 0x208, tmp);322dprintk("%s: sram size = 32K\n", __func__);323return 32;324}325326if (sram_test_location(adapter, 0x20000, 0x18000) != 0) {327sram_set_size(adapter, 0x20000);328sram_init(adapter);329write_reg_dw(adapter, 0x208, tmp);330dprintk("%s: sram size = 128K\n", __func__);331return 128;332}333334if (sram_test_location(adapter, 0x00000, 0x10000) != 0) {335sram_set_size(adapter, 0x00000);336sram_init(adapter);337write_reg_dw(adapter, 0x208, tmp);338dprintk("%s: sram size = 64K\n", __func__);339return 64;340}341342if (sram_test_location(adapter, 0x10000, 0x00000) != 0) {343sram_set_size(adapter, 0x10000);344sram_init(adapter);345write_reg_dw(adapter, 0x208, tmp);346dprintk("%s: sram size = 32K\n", __func__);347return 32;348}349350sram_set_size(adapter, 0x10000);351sram_init(adapter);352write_reg_dw(adapter, 0x208, tmp);353dprintk("%s: SRAM detection failed. Set to 32K \n", __func__);354return 0;355}356357static void sll_detect_sram_size(struct adapter *adapter)358{359sram_detect_for_flex2(adapter);360}361362#endif363364365