Path: blob/master/drivers/media/dvb/frontends/cxd2820r_t.c
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/*1* Sony CXD2820R demodulator driver2*3* Copyright (C) 2010 Antti Palosaari <[email protected]>4*5* This program is free software; you can redistribute it and/or modify6* it under the terms of the GNU General Public License as published by7* the Free Software Foundation; either version 2 of the License, or8* (at your option) any later version.9*10* This program is distributed in the hope that it will be useful,11* but WITHOUT ANY WARRANTY; without even the implied warranty of12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the13* GNU General Public License for more details.14*15* You should have received a copy of the GNU General Public License along16* with this program; if not, write to the Free Software Foundation, Inc.,17* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.18*/192021#include "cxd2820r_priv.h"2223int cxd2820r_set_frontend_t(struct dvb_frontend *fe,24struct dvb_frontend_parameters *p)25{26struct cxd2820r_priv *priv = fe->demodulator_priv;27struct dtv_frontend_properties *c = &fe->dtv_property_cache;28int ret, i;29u32 if_khz, if_ctl;30u64 num;31u8 buf[3], bw_param;32u8 bw_params1[][5] = {33{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */34{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */35{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */36};37u8 bw_params2[][2] = {38{ 0x1f, 0xdc }, /* 6 MHz */39{ 0x12, 0xf8 }, /* 7 MHz */40{ 0x01, 0xe0 }, /* 8 MHz */41};42struct reg_val_mask tab[] = {43{ 0x00080, 0x00, 0xff },44{ 0x00081, 0x03, 0xff },45{ 0x00085, 0x07, 0xff },46{ 0x00088, 0x01, 0xff },4748{ 0x00070, priv->cfg.ts_mode, 0xff },49{ 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },50{ 0x000a5, 0x00, 0x01 },51{ 0x00082, 0x20, 0x60 },52{ 0x000c2, 0xc3, 0xff },53{ 0x0016a, 0x50, 0xff },54{ 0x00427, 0x41, 0xff },55};5657dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);5859/* update GPIOs */60ret = cxd2820r_gpio(fe);61if (ret)62goto error;6364/* program tuner */65if (fe->ops.tuner_ops.set_params)66fe->ops.tuner_ops.set_params(fe, p);6768if (priv->delivery_system != SYS_DVBT) {69for (i = 0; i < ARRAY_SIZE(tab); i++) {70ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,71tab[i].val, tab[i].mask);72if (ret)73goto error;74}75}7677priv->delivery_system = SYS_DVBT;78priv->ber_running = 0; /* tune stops BER counter */7980switch (c->bandwidth_hz) {81case 6000000:82if_khz = priv->cfg.if_dvbt_6;83i = 0;84bw_param = 2;85break;86case 7000000:87if_khz = priv->cfg.if_dvbt_7;88i = 1;89bw_param = 1;90break;91case 8000000:92if_khz = priv->cfg.if_dvbt_8;93i = 2;94bw_param = 0;95break;96default:97return -EINVAL;98}99100num = if_khz;101num *= 0x1000000;102if_ctl = cxd2820r_div_u64_round_closest(num, 41000);103buf[0] = ((if_ctl >> 16) & 0xff);104buf[1] = ((if_ctl >> 8) & 0xff);105buf[2] = ((if_ctl >> 0) & 0xff);106107ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);108if (ret)109goto error;110111ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[i], 5);112if (ret)113goto error;114115ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);116if (ret)117goto error;118119ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[i], 2);120if (ret)121goto error;122123ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);124if (ret)125goto error;126127ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);128if (ret)129goto error;130131return ret;132error:133dbg("%s: failed:%d", __func__, ret);134return ret;135}136137int cxd2820r_get_frontend_t(struct dvb_frontend *fe,138struct dvb_frontend_parameters *p)139{140struct cxd2820r_priv *priv = fe->demodulator_priv;141struct dtv_frontend_properties *c = &fe->dtv_property_cache;142int ret;143u8 buf[2];144145ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));146if (ret)147goto error;148149switch ((buf[0] >> 6) & 0x03) {150case 0:151c->modulation = QPSK;152break;153case 1:154c->modulation = QAM_16;155break;156case 2:157c->modulation = QAM_64;158break;159}160161switch ((buf[1] >> 1) & 0x03) {162case 0:163c->transmission_mode = TRANSMISSION_MODE_2K;164break;165case 1:166c->transmission_mode = TRANSMISSION_MODE_8K;167break;168}169170switch ((buf[1] >> 3) & 0x03) {171case 0:172c->guard_interval = GUARD_INTERVAL_1_32;173break;174case 1:175c->guard_interval = GUARD_INTERVAL_1_16;176break;177case 2:178c->guard_interval = GUARD_INTERVAL_1_8;179break;180case 3:181c->guard_interval = GUARD_INTERVAL_1_4;182break;183}184185switch ((buf[0] >> 3) & 0x07) {186case 0:187c->hierarchy = HIERARCHY_NONE;188break;189case 1:190c->hierarchy = HIERARCHY_1;191break;192case 2:193c->hierarchy = HIERARCHY_2;194break;195case 3:196c->hierarchy = HIERARCHY_4;197break;198}199200switch ((buf[0] >> 0) & 0x07) {201case 0:202c->code_rate_HP = FEC_1_2;203break;204case 1:205c->code_rate_HP = FEC_2_3;206break;207case 2:208c->code_rate_HP = FEC_3_4;209break;210case 3:211c->code_rate_HP = FEC_5_6;212break;213case 4:214c->code_rate_HP = FEC_7_8;215break;216}217218switch ((buf[1] >> 5) & 0x07) {219case 0:220c->code_rate_LP = FEC_1_2;221break;222case 1:223c->code_rate_LP = FEC_2_3;224break;225case 2:226c->code_rate_LP = FEC_3_4;227break;228case 3:229c->code_rate_LP = FEC_5_6;230break;231case 4:232c->code_rate_LP = FEC_7_8;233break;234}235236ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);237if (ret)238goto error;239240switch ((buf[0] >> 0) & 0x01) {241case 0:242c->inversion = INVERSION_OFF;243break;244case 1:245c->inversion = INVERSION_ON;246break;247}248249return ret;250error:251dbg("%s: failed:%d", __func__, ret);252return ret;253}254255int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)256{257struct cxd2820r_priv *priv = fe->demodulator_priv;258int ret;259u8 buf[3], start_ber = 0;260*ber = 0;261262if (priv->ber_running) {263ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));264if (ret)265goto error;266267if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {268*ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];269start_ber = 1;270}271} else {272priv->ber_running = 1;273start_ber = 1;274}275276if (start_ber) {277/* (re)start BER */278ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);279if (ret)280goto error;281}282283return ret;284error:285dbg("%s: failed:%d", __func__, ret);286return ret;287}288289int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,290u16 *strength)291{292struct cxd2820r_priv *priv = fe->demodulator_priv;293int ret;294u8 buf[2];295u16 tmp;296297ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));298if (ret)299goto error;300301tmp = (buf[0] & 0x0f) << 8 | buf[1];302tmp = ~tmp & 0x0fff;303304/* scale value to 0x0000-0xffff from 0x0000-0x0fff */305*strength = tmp * 0xffff / 0x0fff;306307return ret;308error:309dbg("%s: failed:%d", __func__, ret);310return ret;311}312313int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)314{315struct cxd2820r_priv *priv = fe->demodulator_priv;316int ret;317u8 buf[2];318u16 tmp;319/* report SNR in dB * 10 */320321ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));322if (ret)323goto error;324325tmp = (buf[0] & 0x1f) << 8 | buf[1];326#define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */327if (tmp)328*snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)329/ 100);330else331*snr = 0;332333dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);334335return ret;336error:337dbg("%s: failed:%d", __func__, ret);338return ret;339}340341int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)342{343*ucblocks = 0;344/* no way to read ? */345return 0;346}347348int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status)349{350struct cxd2820r_priv *priv = fe->demodulator_priv;351int ret;352u8 buf[4];353*status = 0;354355ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);356if (ret)357goto error;358359if ((buf[0] & 0x07) == 6) {360ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);361if (ret)362goto error;363364if (((buf[1] >> 3) & 0x01) == 1) {365*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |366FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;367} else {368*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |369FE_HAS_VITERBI | FE_HAS_SYNC;370}371} else {372ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);373if (ret)374goto error;375376if ((buf[2] & 0x0f) >= 4) {377ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);378if (ret)379goto error;380381if (((buf[3] >> 4) & 0x01) == 1)382*status |= FE_HAS_SIGNAL;383}384}385386dbg("%s: lock=%02x %02x %02x %02x", __func__,387buf[0], buf[1], buf[2], buf[3]);388389return ret;390error:391dbg("%s: failed:%d", __func__, ret);392return ret;393}394395int cxd2820r_init_t(struct dvb_frontend *fe)396{397struct cxd2820r_priv *priv = fe->demodulator_priv;398int ret;399400ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);401if (ret)402goto error;403404return ret;405error:406dbg("%s: failed:%d", __func__, ret);407return ret;408}409410int cxd2820r_sleep_t(struct dvb_frontend *fe)411{412struct cxd2820r_priv *priv = fe->demodulator_priv;413int ret, i;414struct reg_val_mask tab[] = {415{ 0x000ff, 0x1f, 0xff },416{ 0x00085, 0x00, 0xff },417{ 0x00088, 0x01, 0xff },418{ 0x00081, 0x00, 0xff },419{ 0x00080, 0x00, 0xff },420};421422dbg("%s", __func__);423424priv->delivery_system = SYS_UNDEFINED;425426for (i = 0; i < ARRAY_SIZE(tab); i++) {427ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,428tab[i].mask);429if (ret)430goto error;431}432433return ret;434error:435dbg("%s: failed:%d", __func__, ret);436return ret;437}438439int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,440struct dvb_frontend_tune_settings *s)441{442s->min_delay_ms = 500;443s->step_size = fe->ops.info.frequency_stepsize * 2;444s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;445446return 0;447}448449450451