CoCalc -- cx18-av-core.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/drivers/media/video/cx18/cx18-av-core.h
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/*
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 *  cx18 ADEC header
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 *
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 *  Derived from cx25840-core.h
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 *
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 *  Copyright (C) 2007  Hans Verkuil <[email protected]>
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 *  Copyright (C) 2008  Andy Walls <[email protected]>
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 *
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 *  This program is free software; you can redistribute it and/or
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 *  modify it under the terms of the GNU General Public License
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 *  as published by the Free Software Foundation; either version 2
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 *  of the License, or (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *  GNU General Public License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program; if not, write to the Free Software
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 *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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 *  02110-1301, USA.
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 */
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#ifndef _CX18_AV_CORE_H_
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#define _CX18_AV_CORE_H_
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#include <media/v4l2-device.h>
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#include <media/v4l2-ctrls.h>
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struct cx18;
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enum cx18_av_video_input {
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	/* Composite video inputs In1-In8 */
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	CX18_AV_COMPOSITE1 = 1,
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	CX18_AV_COMPOSITE2,
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	CX18_AV_COMPOSITE3,
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	CX18_AV_COMPOSITE4,
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	CX18_AV_COMPOSITE5,
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	CX18_AV_COMPOSITE6,
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	CX18_AV_COMPOSITE7,
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	CX18_AV_COMPOSITE8,
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	/* S-Video inputs consist of one luma input (In1-In8) ORed with one
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	   chroma input (In5-In8) */
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	CX18_AV_SVIDEO_LUMA1 = 0x10,
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	CX18_AV_SVIDEO_LUMA2 = 0x20,
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	CX18_AV_SVIDEO_LUMA3 = 0x30,
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	CX18_AV_SVIDEO_LUMA4 = 0x40,
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	CX18_AV_SVIDEO_LUMA5 = 0x50,
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	CX18_AV_SVIDEO_LUMA6 = 0x60,
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	CX18_AV_SVIDEO_LUMA7 = 0x70,
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	CX18_AV_SVIDEO_LUMA8 = 0x80,
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	CX18_AV_SVIDEO_CHROMA4 = 0x400,
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	CX18_AV_SVIDEO_CHROMA5 = 0x500,
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	CX18_AV_SVIDEO_CHROMA6 = 0x600,
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	CX18_AV_SVIDEO_CHROMA7 = 0x700,
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	CX18_AV_SVIDEO_CHROMA8 = 0x800,
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	/* S-Video aliases for common luma/chroma combinations */
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	CX18_AV_SVIDEO1 = 0x510,
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	CX18_AV_SVIDEO2 = 0x620,
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	CX18_AV_SVIDEO3 = 0x730,
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	CX18_AV_SVIDEO4 = 0x840,
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	/* Component Video inputs consist of one luma input (In1-In8) ORed
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	   with a red chroma (In4-In6) and blue chroma input (In7-In8) */
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	CX18_AV_COMPONENT_LUMA1 = 0x1000,
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	CX18_AV_COMPONENT_LUMA2 = 0x2000,
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	CX18_AV_COMPONENT_LUMA3 = 0x3000,
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	CX18_AV_COMPONENT_LUMA4 = 0x4000,
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	CX18_AV_COMPONENT_LUMA5 = 0x5000,
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	CX18_AV_COMPONENT_LUMA6 = 0x6000,
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	CX18_AV_COMPONENT_LUMA7 = 0x7000,
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	CX18_AV_COMPONENT_LUMA8 = 0x8000,
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	CX18_AV_COMPONENT_R_CHROMA4 = 0x40000,
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	CX18_AV_COMPONENT_R_CHROMA5 = 0x50000,
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	CX18_AV_COMPONENT_R_CHROMA6 = 0x60000,
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	CX18_AV_COMPONENT_B_CHROMA7 = 0x700000,
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	CX18_AV_COMPONENT_B_CHROMA8 = 0x800000,
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	/* Component Video aliases for common combinations */
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	CX18_AV_COMPONENT1 = 0x861000,
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};
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enum cx18_av_audio_input {
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	/* Audio inputs: serial or In4-In8 */
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	CX18_AV_AUDIO_SERIAL1,
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	CX18_AV_AUDIO_SERIAL2,
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	CX18_AV_AUDIO4 = 4,
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	CX18_AV_AUDIO5,
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	CX18_AV_AUDIO6,
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	CX18_AV_AUDIO7,
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	CX18_AV_AUDIO8,
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};
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struct cx18_av_state {
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	struct v4l2_subdev sd;
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	struct v4l2_ctrl_handler hdl;
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	struct v4l2_ctrl *volume;
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	int radio;
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	v4l2_std_id std;
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	enum cx18_av_video_input vid_input;
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	enum cx18_av_audio_input aud_input;
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	u32 audclk_freq;
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	int audmode;
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	u32 id;
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	u32 rev;
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	int is_initialized;
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	/*
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	 * The VBI slicer starts operating and counting lines, beginning at
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	 * slicer line count of 1, at D lines after the deassertion of VRESET.
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	 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
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	 * line systems respectively.  Sliced ancillary data captured on VBI
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	 * slicer line M is inserted after the VBI slicer is done with line M,
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	 * when VBI slicer line count is N = M+1.  Thus when the VBI slicer
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	 * reports a VBI slicer line number with ancillary data, the IDID0 byte
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	 * indicates VBI slicer line N.  The actual field line that the captured
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	 * data comes from is
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	 *
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	 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
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	 *
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	 * L is the line in the field, not frame, from which the VBI data came.
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	 * N is the line reported by the slicer in the ancillary data.
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	 * D is the slicer_line_delay value programmed into register 0x47f.
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	 * S is 6 for 625 line systems or 10 for 525 line systems
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	 * (S+D-2) is the slicer_line_offset used to convert slicer reported
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	 * line counts to actual field lines.
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	 */
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	int slicer_line_delay;
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	int slicer_line_offset;
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};
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/* Registers */
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#define CXADEC_CHIP_TYPE_TIGER     0x837
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#define CXADEC_CHIP_TYPE_MAKO      0x843
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#define CXADEC_HOST_REG1           0x000
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#define CXADEC_HOST_REG2           0x001
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#define CXADEC_CHIP_CTRL           0x100
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#define CXADEC_AFE_CTRL            0x104
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#define CXADEC_PLL_CTRL1           0x108
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#define CXADEC_VID_PLL_FRAC        0x10C
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#define CXADEC_AUX_PLL_FRAC        0x110
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#define CXADEC_PIN_CTRL1           0x114
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#define CXADEC_PIN_CTRL2           0x118
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#define CXADEC_PIN_CFG1            0x11C
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#define CXADEC_PIN_CFG2            0x120
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#define CXADEC_PIN_CFG3            0x124
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#define CXADEC_I2S_MCLK            0x127
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#define CXADEC_AUD_LOCK1           0x128
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#define CXADEC_AUD_LOCK2           0x12C
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#define CXADEC_POWER_CTRL          0x130
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#define CXADEC_AFE_DIAG_CTRL1      0x134
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#define CXADEC_AFE_DIAG_CTRL2      0x138
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#define CXADEC_AFE_DIAG_CTRL3      0x13C
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#define CXADEC_PLL_DIAG_CTRL       0x140
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#define CXADEC_TEST_CTRL1          0x144
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#define CXADEC_TEST_CTRL2          0x148
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#define CXADEC_BIST_STAT           0x14C
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#define CXADEC_DLL1_DIAG_CTRL      0x158
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#define CXADEC_DLL2_DIAG_CTRL      0x15C
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/* IR registers */
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#define CXADEC_IR_CTRL_REG         0x200
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#define CXADEC_IR_TXCLK_REG        0x204
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#define CXADEC_IR_RXCLK_REG        0x208
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#define CXADEC_IR_CDUTY_REG        0x20C
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#define CXADEC_IR_STAT_REG         0x210
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#define CXADEC_IR_IRQEN_REG        0x214
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#define CXADEC_IR_FILTER_REG       0x218
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#define CXADEC_IR_FIFO_REG         0x21C
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/* Video Registers */
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#define CXADEC_MODE_CTRL           0x400
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#define CXADEC_OUT_CTRL1           0x404
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#define CXADEC_OUT_CTRL2           0x408
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#define CXADEC_GEN_STAT            0x40C
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#define CXADEC_INT_STAT_MASK       0x410
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#define CXADEC_LUMA_CTRL           0x414
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#define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
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#define CXADEC_CONTRAST_CTRL_BYTE  0x415
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#define CXADEC_LUMA_CTRL_BYTE_3    0x416
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#define CXADEC_HSCALE_CTRL         0x418
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#define CXADEC_VSCALE_CTRL         0x41C
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#define CXADEC_CHROMA_CTRL         0x420
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#define CXADEC_USAT_CTRL_BYTE      0x420
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#define CXADEC_VSAT_CTRL_BYTE      0x421
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#define CXADEC_HUE_CTRL_BYTE       0x422
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#define CXADEC_VBI_LINE_CTRL1      0x424
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#define CXADEC_VBI_LINE_CTRL2      0x428
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#define CXADEC_VBI_LINE_CTRL3      0x42C
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#define CXADEC_VBI_LINE_CTRL4      0x430
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#define CXADEC_VBI_LINE_CTRL5      0x434
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#define CXADEC_VBI_FC_CFG          0x438
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#define CXADEC_VBI_MISC_CFG1       0x43C
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#define CXADEC_VBI_MISC_CFG2       0x440
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#define CXADEC_VBI_PAY1            0x444
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#define CXADEC_VBI_PAY2            0x448
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#define CXADEC_VBI_CUST1_CFG1      0x44C
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#define CXADEC_VBI_CUST1_CFG2      0x450
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#define CXADEC_VBI_CUST1_CFG3      0x454
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#define CXADEC_VBI_CUST2_CFG1      0x458
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#define CXADEC_VBI_CUST2_CFG2      0x45C
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#define CXADEC_VBI_CUST2_CFG3      0x460
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#define CXADEC_VBI_CUST3_CFG1      0x464
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#define CXADEC_VBI_CUST3_CFG2      0x468
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#define CXADEC_VBI_CUST3_CFG3      0x46C
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#define CXADEC_HORIZ_TIM_CTRL      0x470
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#define CXADEC_VERT_TIM_CTRL       0x474
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#define CXADEC_SRC_COMB_CFG        0x478
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#define CXADEC_CHROMA_VBIOFF_CFG   0x47C
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#define CXADEC_FIELD_COUNT         0x480
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#define CXADEC_MISC_TIM_CTRL       0x484
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#define CXADEC_DFE_CTRL1           0x488
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#define CXADEC_DFE_CTRL2           0x48C
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#define CXADEC_DFE_CTRL3           0x490
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#define CXADEC_PLL_CTRL2           0x494
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#define CXADEC_HTL_CTRL            0x498
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#define CXADEC_COMB_CTRL           0x49C
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#define CXADEC_CRUSH_CTRL          0x4A0
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#define CXADEC_SOFT_RST_CTRL       0x4A4
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#define CXADEC_MV_DT_CTRL2         0x4A8
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#define CXADEC_MV_DT_CTRL3         0x4AC
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#define CXADEC_MISC_DIAG_CTRL      0x4B8
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#define CXADEC_DL_CTL              0x800
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#define CXADEC_DL_CTL_ADDRESS_LOW  0x800   /* Byte 1 in DL_CTL */
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#define CXADEC_DL_CTL_ADDRESS_HIGH 0x801   /* Byte 2 in DL_CTL */
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#define CXADEC_DL_CTL_DATA         0x802   /* Byte 3 in DL_CTL */
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#define CXADEC_DL_CTL_CONTROL      0x803   /* Byte 4 in DL_CTL */
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#define CXADEC_STD_DET_STATUS      0x804
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#define CXADEC_STD_DET_CTL         0x808
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#define CXADEC_STD_DET_CTL_AUD_CTL   0x808 /* Byte 1 in STD_DET_CTL */
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#define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
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#define CXADEC_DW8051_INT          0x80C
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#define CXADEC_GENERAL_CTL         0x810
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#define CXADEC_AAGC_CTL            0x814
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#define CXADEC_IF_SRC_CTL          0x818
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#define CXADEC_ANLOG_DEMOD_CTL     0x81C
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#define CXADEC_ROT_FREQ_CTL        0x820
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#define CXADEC_FM1_CTL             0x824
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#define CXADEC_PDF_CTL             0x828
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#define CXADEC_DFT1_CTL1           0x82C
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#define CXADEC_DFT1_CTL2           0x830
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#define CXADEC_DFT_STATUS          0x834
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#define CXADEC_DFT2_CTL1           0x838
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#define CXADEC_DFT2_CTL2           0x83C
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#define CXADEC_DFT2_STATUS         0x840
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#define CXADEC_DFT3_CTL1           0x844
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#define CXADEC_DFT3_CTL2           0x848
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#define CXADEC_DFT3_STATUS         0x84C
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#define CXADEC_DFT4_CTL1           0x850
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#define CXADEC_DFT4_CTL2           0x854
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#define CXADEC_DFT4_STATUS         0x858
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#define CXADEC_AM_MTS_DET          0x85C
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#define CXADEC_ANALOG_MUX_CTL      0x860
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#define CXADEC_DIG_PLL_CTL1        0x864
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#define CXADEC_DIG_PLL_CTL2        0x868
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#define CXADEC_DIG_PLL_CTL3        0x86C
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#define CXADEC_DIG_PLL_CTL4        0x870
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#define CXADEC_DIG_PLL_CTL5        0x874
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#define CXADEC_DEEMPH_GAIN_CTL     0x878
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#define CXADEC_DEEMPH_COEF1        0x87C
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#define CXADEC_DEEMPH_COEF2        0x880
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#define CXADEC_DBX1_CTL1           0x884
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#define CXADEC_DBX1_CTL2           0x888
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#define CXADEC_DBX1_STATUS         0x88C
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#define CXADEC_DBX2_CTL1           0x890
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#define CXADEC_DBX2_CTL2           0x894
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#define CXADEC_DBX2_STATUS         0x898
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#define CXADEC_AM_FM_DIFF          0x89C
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/* NICAM registers go here */
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#define CXADEC_NICAM_STATUS        0x8C8
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#define CXADEC_DEMATRIX_CTL        0x8CC
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#define CXADEC_PATH1_CTL1          0x8D0
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#define CXADEC_PATH1_VOL_CTL       0x8D4
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#define CXADEC_PATH1_EQ_CTL        0x8D8
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#define CXADEC_PATH1_SC_CTL        0x8DC
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#define CXADEC_PATH2_CTL1          0x8E0
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#define CXADEC_PATH2_VOL_CTL       0x8E4
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#define CXADEC_PATH2_EQ_CTL        0x8E8
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#define CXADEC_PATH2_SC_CTL        0x8EC
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301
#define CXADEC_SRC_CTL             0x8F0
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#define CXADEC_SRC_LF_COEF         0x8F4
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#define CXADEC_SRC1_CTL            0x8F8
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#define CXADEC_SRC2_CTL            0x8FC
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#define CXADEC_SRC3_CTL            0x900
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#define CXADEC_SRC4_CTL            0x904
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#define CXADEC_SRC5_CTL            0x908
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#define CXADEC_SRC6_CTL            0x90C
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#define CXADEC_BASEBAND_OUT_SEL    0x910
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#define CXADEC_I2S_IN_CTL          0x914
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#define CXADEC_I2S_OUT_CTL         0x918
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#define CXADEC_AC97_CTL            0x91C
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#define CXADEC_QAM_PDF             0x920
315
#define CXADEC_QAM_CONST_DEC       0x924
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#define CXADEC_QAM_ROTATOR_FREQ    0x948
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318
/* Bit definitions / settings used in Mako Audio */
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#define CXADEC_PREF_MODE_MONO_LANGA        0
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#define CXADEC_PREF_MODE_MONO_LANGB        1
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#define CXADEC_PREF_MODE_MONO_LANGC        2
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#define CXADEC_PREF_MODE_FALLBACK          3
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#define CXADEC_PREF_MODE_STEREO            4
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#define CXADEC_PREF_MODE_DUAL_LANG_AC      5
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#define CXADEC_PREF_MODE_DUAL_LANG_BC      6
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#define CXADEC_PREF_MODE_DUAL_LANG_AB      7
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328

329
#define CXADEC_DETECT_STEREO               1
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#define CXADEC_DETECT_DUAL                 2
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#define CXADEC_DETECT_TRI                  4
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#define CXADEC_DETECT_SAP                  0x10
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#define CXADEC_DETECT_NO_SIGNAL            0xFF
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#define CXADEC_SELECT_AUDIO_STANDARD_BG    0xF0  /* NICAM BG and A2 BG */
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#define CXADEC_SELECT_AUDIO_STANDARD_DK1   0xF1  /* NICAM DK and A2 DK */
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#define CXADEC_SELECT_AUDIO_STANDARD_DK2   0xF2
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#define CXADEC_SELECT_AUDIO_STANDARD_DK3   0xF3
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#define CXADEC_SELECT_AUDIO_STANDARD_I     0xF4  /* NICAM I and A1 */
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#define CXADEC_SELECT_AUDIO_STANDARD_L     0xF5  /* NICAM L and System L AM */
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#define CXADEC_SELECT_AUDIO_STANDARD_BTSC  0xF6
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#define CXADEC_SELECT_AUDIO_STANDARD_EIAJ  0xF7
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#define CXADEC_SELECT_AUDIO_STANDARD_A2_M  0xF8  /* A2 M */
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#define CXADEC_SELECT_AUDIO_STANDARD_FM    0xF9  /* FM radio */
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#define CXADEC_SELECT_AUDIO_STANDARD_AUTO  0xFF  /* Auto detect */
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static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd)
348
{
349
	return container_of(sd, struct cx18_av_state, sd);
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}
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352
static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
353
{
354
	return &container_of(ctrl->handler, struct cx18_av_state, hdl)->sd;
355
}
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357
/* ----------------------------------------------------------------------- */
358
/* cx18_av-core.c 							   */
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int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
360
int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
361
int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
362
int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask);
363
int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval,
364
			  u32 mask);
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u8 cx18_av_read(struct cx18 *cx, u16 addr);
366
u32 cx18_av_read4(struct cx18 *cx, u16 addr);
367
int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
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int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
369
void cx18_av_std_setup(struct cx18 *cx);
370

371
int cx18_av_probe(struct cx18 *cx);
372

373
/* ----------------------------------------------------------------------- */
374
/* cx18_av-firmware.c                                                      */
375
int cx18_av_loadfw(struct cx18 *cx);
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377
/* ----------------------------------------------------------------------- */
378
/* cx18_av-audio.c                                                         */
379
int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
380
void cx18_av_audio_set_path(struct cx18 *cx);
381
extern const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops;
382

383
/* ----------------------------------------------------------------------- */
384
/* cx18_av-vbi.c                                                           */
385
int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
386
			   struct v4l2_decode_vbi_line *vbi);
387
int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt);
388
int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
389
int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
390

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#endif
392

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