Path: blob/master/drivers/media/video/cx18/cx18-irq.c
17751 views
/*1* cx18 interrupt handling2*3* Copyright (C) 2007 Hans Verkuil <[email protected]>4* Copyright (C) 2008 Andy Walls <[email protected]>5*6* This program is free software; you can redistribute it and/or modify7* it under the terms of the GNU General Public License as published by8* the Free Software Foundation; either version 2 of the License, or9* (at your option) any later version.10*11* This program is distributed in the hope that it will be useful,12* but WITHOUT ANY WARRANTY; without even the implied warranty of13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the14* GNU General Public License for more details.15*16* You should have received a copy of the GNU General Public License17* along with this program; if not, write to the Free Software18* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA19* 02111-1307 USA20*/2122#include "cx18-driver.h"23#include "cx18-io.h"24#include "cx18-irq.h"25#include "cx18-mailbox.h"26#include "cx18-scb.h"2728static void xpu_ack(struct cx18 *cx, u32 sw2)29{30if (sw2 & IRQ_CPU_TO_EPU_ACK)31wake_up(&cx->mb_cpu_waitq);32if (sw2 & IRQ_APU_TO_EPU_ACK)33wake_up(&cx->mb_apu_waitq);34}3536static void epu_cmd(struct cx18 *cx, u32 sw1)37{38if (sw1 & IRQ_CPU_TO_EPU)39cx18_api_epu_cmd_irq(cx, CPU);40if (sw1 & IRQ_APU_TO_EPU)41cx18_api_epu_cmd_irq(cx, APU);42}4344irqreturn_t cx18_irq_handler(int irq, void *dev_id)45{46struct cx18 *cx = (struct cx18 *)dev_id;47u32 sw1, sw2, hw2;4849sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;50sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;51hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;5253if (sw1)54cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);55if (sw2)56cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);57if (hw2)58cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);5960if (sw1 || sw2 || hw2)61CX18_DEBUG_HI_IRQ("received interrupts "62"SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);6364/*65* SW1 responses have to happen first. The sending XPU times out the66* incoming mailboxes on us rather rapidly.67*/68if (sw1)69epu_cmd(cx, sw1);7071/* To do: interrupt-based I2C handling72if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {73}74*/7576if (sw2)77xpu_ack(cx, sw2);7879return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;80}818283