Path: blob/master/drivers/media/video/cx231xx/cx231xx-reg.h
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/*1cx231xx-reg.h - driver for Conexant Cx23100/101/1022USB video capture devices34Copyright (C) 2008 <srinivasa.deevi at conexant dot com>56This program is free software; you can redistribute it and/or modify7it under the terms of the GNU General Public License as published by8the Free Software Foundation; either version 2 of the License, or9(at your option) any later version.1011This program is distributed in the hope that it will be useful,12but WITHOUT ANY WARRANTY; without even the implied warranty of13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the14GNU General Public License for more details.1516You should have received a copy of the GNU General Public License17along with this program; if not, write to the Free Software18Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.19*/2021#ifndef _CX231XX_REG_H22#define _CX231XX_REG_H2324/*****************************************************************************25* VBI codes *26*****************************************************************************/2728#define SAV_ACTIVE_VIDEO_FIELD1 0x8029#define EAV_ACTIVE_VIDEO_FIELD1 0x903031#define SAV_ACTIVE_VIDEO_FIELD2 0xc032#define EAV_ACTIVE_VIDEO_FIELD2 0xd03334#define SAV_VBLANK_FIELD1 0xa035#define EAV_VBLANK_FIELD1 0xb03637#define SAV_VBLANK_FIELD2 0xe038#define EAV_VBLANK_FIELD2 0xf03940#define SAV_VBI_FIELD1 0x2041#define EAV_VBI_FIELD1 0x304243#define SAV_VBI_FIELD2 0x6044#define EAV_VBI_FIELD2 0x704546/*****************************************************************************/47/* Audio ADC Registers */48#define CH_PWR_CTRL1 0x0000000e49#define CH_PWR_CTRL2 0x0000000f50/*****************************************************************************/5152#define HOST_REG1 0x00053#define FLD_FORCE_CHIP_SEL 0x8054#define FLD_AUTO_INC_DIS 0x2055#define FLD_PREFETCH_EN 0x1056/* Reserved [2:3] */57#define FLD_DIGITAL_PWR_DN 0x0258#define FLD_SLEEP 0x015960/*****************************************************************************/61#define HOST_REG2 0x0016263/*****************************************************************************/64#define HOST_REG3 0x0026566/*****************************************************************************/67/* added for polaris */68#define GPIO_PIN_CTL0 0x369#define GPIO_PIN_CTL1 0x470#define GPIO_PIN_CTL2 0x571#define GPIO_PIN_CTL3 0x672#define TS1_PIN_CTL0 0x773#define TS1_PIN_CTL1 0x874/*****************************************************************************/7576#define FLD_CLK_IN_EN 0x8077#define FLD_XTAL_CTRL 0x7078#define FLD_BB_CLK_MODE 0x0C79#define FLD_REF_DIV_PLL 0x0280#define FLD_REF_SEL_PLL1 0x018182/*****************************************************************************/83#define CHIP_CTRL 0x10084/* Reserved [27] */85/* Reserved [31:21] */86#define FLD_CHIP_ACFG_DIS 0x0010000087/* Reserved [19] */88#define FLD_DUAL_MODE_ADC2 0x0004000089#define FLD_SIF_EN 0x0002000090#define FLD_SOFT_RST 0x0001000091#define FLD_DEVICE_ID 0x0000ffff9293/*****************************************************************************/94#define AFE_CTRL 0x10495#define AFE_CTRL_C2HH_SRC_CTRL 0x10496#define FLD_DIF_OUT_SEL 0xc000000097#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c00000098#define FLD_UV_ORDER_MODE 0x0200000099#define FLD_FUNC_MODE 0x01800000100#define FLD_ROT1_PHASE_CTL 0x007f8000101#define FLD_AUD_IN_SEL 0x00004000102#define FLD_LUMA_IN_SEL 0x00002000103#define FLD_CHROMA_IN_SEL 0x00001000104/* reserve [11:10] */105#define FLD_INV_SPEC_DIS 0x00000200106#define FLD_VGA_SEL_CH3 0x00000100107#define FLD_VGA_SEL_CH2 0x00000080108#define FLD_VGA_SEL_CH1 0x00000040109#define FLD_DCR_BYP_CH1 0x00000020110#define FLD_DCR_BYP_CH2 0x00000010111#define FLD_DCR_BYP_CH3 0x00000008112#define FLD_EN_12DB_CH3 0x00000004113#define FLD_EN_12DB_CH2 0x00000002114#define FLD_EN_12DB_CH1 0x00000001115116/* redefine in Cx231xx */117/*****************************************************************************/118#define DC_CTRL1 0x108119/* reserve [31:30] */120#define FLD_CLAMP_LVL_CH1 0x3fff8000121#define FLD_CLAMP_LVL_CH2 0x00007fff122/*****************************************************************************/123124/*****************************************************************************/125#define DC_CTRL2 0x10c126/* reserve [31:28] */127#define FLD_CLAMP_LVL_CH3 0x00fffe00128#define FLD_CLAMP_WIND_LENTH 0x000001e0129#define FLD_C2HH_SAT_MIN 0x0000001e130#define FLD_FLT_BYP_SEL 0x00000001131/*****************************************************************************/132133/*****************************************************************************/134#define DC_CTRL3 0x110135/* reserve [31:16] */136#define FLD_ERR_GAIN_CTL 0x00070000137#define FLD_LPF_MIN 0x0000ffff138/*****************************************************************************/139140/*****************************************************************************/141#define DC_CTRL4 0x114142/* reserve [31:31] */143#define FLD_INTG_CH1 0x7fffffff144/*****************************************************************************/145146/*****************************************************************************/147#define DC_CTRL5 0x118148/* reserve [31:31] */149#define FLD_INTG_CH2 0x7fffffff150/*****************************************************************************/151152/*****************************************************************************/153#define DC_CTRL6 0x11c154/* reserve [31:31] */155#define FLD_INTG_CH3 0x7fffffff156/*****************************************************************************/157158/*****************************************************************************/159#define PIN_CTRL 0x120160#define FLD_OEF_AGC_RF 0x00000001161#define FLD_OEF_AGC_IFVGA 0x00000002162#define FLD_OEF_AGC_IF 0x00000004163#define FLD_REG_BO_PUD 0x80000000164#define FLD_IR_IRQ_STAT 0x40000000165#define FLD_AUD_IRQ_STAT 0x20000000166#define FLD_VID_IRQ_STAT 0x10000000167/* Reserved [27:26] */168#define FLD_IRQ_N_OUT_EN 0x02000000169#define FLD_IRQ_N_POLAR 0x01000000170/* Reserved [23:6] */171#define FLD_OE_AUX_PLL_CLK 0x00000020172#define FLD_OE_I2S_BCLK 0x00000010173#define FLD_OE_I2S_WCLK 0x00000008174#define FLD_OE_AGC_IF 0x00000004175#define FLD_OE_AGC_IFVGA 0x00000002176#define FLD_OE_AGC_RF 0x00000001177178/*****************************************************************************/179#define AUD_IO_CTRL 0x124180/* Reserved [31:8] */181#define FLD_I2S_PORT_DIR 0x00000080182#define FLD_I2S_OUT_SRC 0x00000040183#define FLD_AUD_CHAN3_SRC 0x00000030184#define FLD_AUD_CHAN2_SRC 0x0000000c185#define FLD_AUD_CHAN1_SRC 0x00000003186187/*****************************************************************************/188#define AUD_LOCK1 0x128189#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000190#define FLD_AUD_LOCK_KD_SHIFT 0x30000000191/* Reserved [27:25] */192#define FLD_EN_AV_LOCK 0x01000000193#define FLD_VID_COUNT 0x00ffffff194195/*****************************************************************************/196#define AUD_LOCK2 0x12c197#define FLD_AUD_LOCK_KI_MULT 0xf0000000198#define FLD_AUD_LOCK_KD_MULT 0x0F000000199/* Reserved [23:22] */200#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000201#define FLD_AUD_COUNT 0x000fffff202203/*****************************************************************************/204#define AFE_DIAG_CTRL1 0x134205/* Reserved [31:16] */206#define FLD_CUV_DLY_LENGTH 0x0000ff00207#define FLD_YC_DLY_LENGTH 0x000000ff208209/*****************************************************************************/210/* Poalris redefine */211#define AFE_DIAG_CTRL3 0x138212/* Reserved [31:26] */213#define FLD_AUD_DUAL_FLAG_POL 0x02000000214#define FLD_VID_DUAL_FLAG_POL 0x01000000215/* Reserved [23:23] */216#define FLD_COL_CLAMP_DIS_CH1 0x00400000217#define FLD_COL_CLAMP_DIS_CH2 0x00200000218#define FLD_COL_CLAMP_DIS_CH3 0x00100000219220#define TEST_CTRL1 0x144221/* Reserved [31:29] */222#define FLD_LBIST_EN 0x10000000223/* Reserved [27:10] */224#define FLD_FI_BIST_INTR_R 0x0000200225#define FLD_FI_BIST_INTR_L 0x0000100226#define FLD_BIST_FAIL_AUD_PLL 0x0000080227#define FLD_BIST_INTR_AUD_PLL 0x0000040228#define FLD_BIST_FAIL_VID_PLL 0x0000020229#define FLD_BIST_INTR_VID_PLL 0x0000010230/* Reserved [3:1] */231#define FLD_CIR_TEST_DIS 0x00000001232233/*****************************************************************************/234#define TEST_CTRL2 0x148235#define FLD_TSXCLK_POL_CTL 0x80000000236#define FLD_ISO_CTL_SEL 0x40000000237#define FLD_ISO_CTL_EN 0x20000000238#define FLD_BIST_DEBUGZ 0x10000000239#define FLD_AUD_BIST_TEST_H 0x0f000000240/* Reserved [23:22] */241#define FLD_FLTRN_BIST_TEST_H 0x00020000242#define FLD_VID_BIST_TEST_H 0x00010000243/* Reserved [19:17] */244#define FLD_BIST_TEST_H 0x00010000245/* Reserved [15:13] */246#define FLD_TAB_EN 0x00001000247/* Reserved [11:0] */248249/*****************************************************************************/250#define BIST_STAT 0x14c251#define FLD_AUD_BIST_FAIL_H 0xfff00000252#define FLD_FLTRN_BIST_FAIL_H 0x00180000253#define FLD_VID_BIST_FAIL_H 0x00070000254#define FLD_AUD_BIST_TST_DONE 0x0000fff0255#define FLD_FLTRN_BIST_TST_DONE 0x00000008256#define FLD_VID_BIST_TST_DONE 0x00000007257258/*****************************************************************************/259/* DirectIF registers definition have been moved to DIF_reg.h */260/*****************************************************************************/261#define MODE_CTRL 0x400262#define FLD_AFD_PAL60_DIS 0x20000000263#define FLD_AFD_FORCE_SECAM 0x10000000264#define FLD_AFD_FORCE_PALNC 0x08000000265#define FLD_AFD_FORCE_PAL 0x04000000266#define FLD_AFD_PALM_SEL 0x03000000267#define FLD_CKILL_MODE 0x00300000268#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */269#define FLD_CLR_LOCK_STAT 0x00020000270#define FLD_FAST_LOCK_MD 0x00010000271#define FLD_WCEN 0x00008000272#define FLD_CAGCEN 0x00004000273#define FLD_CKILLEN 0x00002000274#define FLD_AUTO_SC_LOCK 0x00001000275#define FLD_MAN_SC_FAST_LOCK 0x00000800276#define FLD_INPUT_MODE 0x00000600277#define FLD_AFD_ACQUIRE 0x00000100278#define FLD_AFD_NTSC_SEL 0x00000080279#define FLD_AFD_PAL_SEL 0x00000040280#define FLD_ACFG_DIS 0x00000020281#define FLD_SQ_PIXEL 0x00000010282#define FLD_VID_FMT_SEL 0x0000000f283284/*****************************************************************************/285#define OUT_CTRL1 0x404286#define FLD_POLAR 0x7f000000287/* Reserved [23] */288#define FLD_RND_MODE 0x00600000289#define FLD_VIPCLAMP_EN 0x00100000290#define FLD_VIPBLANK_EN 0x00080000291#define FLD_VIP_OPT_AL 0x00040000292#define FLD_IDID0_SOURCE 0x00020000293#define FLD_DCMODE 0x00010000294#define FLD_CLK_GATING 0x0000c000295#define FLD_CLK_INVERT 0x00002000296#define FLD_HSFMT 0x00001000297#define FLD_VALIDFMT 0x00000800298#define FLD_ACTFMT 0x00000400299#define FLD_SWAPRAW 0x00000200300#define FLD_CLAMPRAW_EN 0x00000100301#define FLD_BLUE_FIELD_EN 0x00000080302#define FLD_BLUE_FIELD_ACT 0x00000040303#define FLD_TASKBIT_VAL 0x00000020304#define FLD_ANC_DATA_EN 0x00000010305#define FLD_VBIHACTRAW_EN 0x00000008306#define FLD_MODE10B 0x00000004307#define FLD_OUT_MODE 0x00000003308309/*****************************************************************************/310#define OUT_CTRL2 0x408311#define FLD_AUD_GRP 0xc0000000312#define FLD_SAMPLE_RATE 0x30000000313#define FLD_AUD_ANC_EN 0x08000000314#define FLD_EN_C 0x04000000315#define FLD_EN_B 0x02000000316#define FLD_EN_A 0x01000000317/* Reserved [23:20] */318#define FLD_IDID1_LSB 0x000c0000319#define FLD_IDID0_LSB 0x00030000320#define FLD_IDID1_MSB 0x0000ff00321#define FLD_IDID0_MSB 0x000000ff322323/*****************************************************************************/324#define GEN_STAT 0x40c325#define FLD_VCR_DETECT 0x00800000326#define FLD_SPECIAL_PLAY_N 0x00400000327#define FLD_VPRES 0x00200000328#define FLD_AGC_LOCK 0x00100000329#define FLD_CSC_LOCK 0x00080000330#define FLD_VLOCK 0x00040000331#define FLD_SRC_LOCK 0x00020000332#define FLD_HLOCK 0x00010000333#define FLD_VSYNC_N 0x00008000334#define FLD_SRC_FIFO_UFLOW 0x00004000335#define FLD_SRC_FIFO_OFLOW 0x00002000336#define FLD_FIELD 0x00001000337#define FLD_AFD_FMT_STAT 0x00000f00338#define FLD_MV_TYPE2_PAIR 0x00000080339#define FLD_MV_T3CS 0x00000040340#define FLD_MV_CS 0x00000020341#define FLD_MV_PSP 0x00000010342/* Reserved [3] */343#define FLD_MV_CDAT 0x00000003344345/*****************************************************************************/346#define INT_STAT_MASK 0x410347#define FLD_COMB_3D_FIFO_MSK 0x80000000348#define FLD_WSS_DAT_AVAIL_MSK 0x40000000349#define FLD_GS2_DAT_AVAIL_MSK 0x20000000350#define FLD_GS1_DAT_AVAIL_MSK 0x10000000351#define FLD_CC_DAT_AVAIL_MSK 0x08000000352#define FLD_VPRES_CHANGE_MSK 0x04000000353#define FLD_MV_CHANGE_MSK 0x02000000354#define FLD_END_VBI_EVEN_MSK 0x01000000355#define FLD_END_VBI_ODD_MSK 0x00800000356#define FLD_FMT_CHANGE_MSK 0x00400000357#define FLD_VSYNC_TRAIL_MSK 0x00200000358#define FLD_HLOCK_CHANGE_MSK 0x00100000359#define FLD_VLOCK_CHANGE_MSK 0x00080000360#define FLD_CSC_LOCK_CHANGE_MSK 0x00040000361#define FLD_SRC_FIFO_UFLOW_MSK 0x00020000362#define FLD_SRC_FIFO_OFLOW_MSK 0x00010000363#define FLD_COMB_3D_FIFO_STAT 0x00008000364#define FLD_WSS_DAT_AVAIL_STAT 0x00004000365#define FLD_GS2_DAT_AVAIL_STAT 0x00002000366#define FLD_GS1_DAT_AVAIL_STAT 0x00001000367#define FLD_CC_DAT_AVAIL_STAT 0x00000800368#define FLD_VPRES_CHANGE_STAT 0x00000400369#define FLD_MV_CHANGE_STAT 0x00000200370#define FLD_END_VBI_EVEN_STAT 0x00000100371#define FLD_END_VBI_ODD_STAT 0x00000080372#define FLD_FMT_CHANGE_STAT 0x00000040373#define FLD_VSYNC_TRAIL_STAT 0x00000020374#define FLD_HLOCK_CHANGE_STAT 0x00000010375#define FLD_VLOCK_CHANGE_STAT 0x00000008376#define FLD_CSC_LOCK_CHANGE_STAT 0x00000004377#define FLD_SRC_FIFO_UFLOW_STAT 0x00000002378#define FLD_SRC_FIFO_OFLOW_STAT 0x00000001379380/*****************************************************************************/381#define LUMA_CTRL 0x414382#define BRIGHTNESS_CTRL_BYTE 0x414383#define CONTRAST_CTRL_BYTE 0x415384#define LUMA_CTRL_BYTE_3 0x416385#define FLD_LUMA_CORE_SEL 0x00c00000386#define FLD_RANGE 0x00300000387/* Reserved [19] */388#define FLD_PEAK_EN 0x00040000389#define FLD_PEAK_SEL 0x00030000390#define FLD_CNTRST 0x0000ff00391#define FLD_BRITE 0x000000ff392393/*****************************************************************************/394#define HSCALE_CTRL 0x418395#define FLD_HFILT 0x03000000396#define FLD_HSCALE 0x00ffffff397398/*****************************************************************************/399#define VSCALE_CTRL 0x41c400#define FLD_LINE_AVG_DIS 0x01000000401/* Reserved [23:20] */402#define FLD_VS_INTRLACE 0x00080000403#define FLD_VFILT 0x00070000404/* Reserved [15:13] */405#define FLD_VSCALE 0x00001fff406407/*****************************************************************************/408#define CHROMA_CTRL 0x420409#define USAT_CTRL_BYTE 0x420410#define VSAT_CTRL_BYTE 0x421411#define HUE_CTRL_BYTE 0x422412#define FLD_C_LPF_EN 0x20000000413#define FLD_CHR_DELAY 0x1c000000414#define FLD_C_CORE_SEL 0x03000000415#define FLD_HUE 0x00ff0000416#define FLD_VSAT 0x0000ff00417#define FLD_USAT 0x000000ff418419/*****************************************************************************/420#define VBI_LINE_CTRL1 0x424421#define FLD_VBI_MD_LINE4 0xff000000422#define FLD_VBI_MD_LINE3 0x00ff0000423#define FLD_VBI_MD_LINE2 0x0000ff00424#define FLD_VBI_MD_LINE1 0x000000ff425426/*****************************************************************************/427#define VBI_LINE_CTRL2 0x428428#define FLD_VBI_MD_LINE8 0xff000000429#define FLD_VBI_MD_LINE7 0x00ff0000430#define FLD_VBI_MD_LINE6 0x0000ff00431#define FLD_VBI_MD_LINE5 0x000000ff432433/*****************************************************************************/434#define VBI_LINE_CTRL3 0x42c435#define FLD_VBI_MD_LINE12 0xff000000436#define FLD_VBI_MD_LINE11 0x00ff0000437#define FLD_VBI_MD_LINE10 0x0000ff00438#define FLD_VBI_MD_LINE9 0x000000ff439440/*****************************************************************************/441#define VBI_LINE_CTRL4 0x430442#define FLD_VBI_MD_LINE16 0xff000000443#define FLD_VBI_MD_LINE15 0x00ff0000444#define FLD_VBI_MD_LINE14 0x0000ff00445#define FLD_VBI_MD_LINE13 0x000000ff446447/*****************************************************************************/448#define VBI_LINE_CTRL5 0x434449#define FLD_VBI_MD_LINE17 0x000000ff450451/*****************************************************************************/452#define VBI_FC_CFG 0x438453#define FLD_FC_ALT2 0xff000000454#define FLD_FC_ALT1 0x00ff0000455#define FLD_FC_ALT2_TYPE 0x0000f000456#define FLD_FC_ALT1_TYPE 0x00000f00457/* Reserved [7:1] */458#define FLD_FC_SEARCH_MODE 0x00000001459460/*****************************************************************************/461#define VBI_MISC_CFG1 0x43c462#define FLD_TTX_PKTADRU 0xfff00000463#define FLD_TTX_PKTADRL 0x000fff00464/* Reserved [7:6] */465#define FLD_MOJI_PACK_DIS 0x00000020466#define FLD_VPS_DEC_DIS 0x00000010467#define FLD_CRI_MARG_SCALE 0x0000000c468#define FLD_EDGE_RESYNC_EN 0x00000002469#define FLD_ADAPT_SLICE_DIS 0x00000001470471/*****************************************************************************/472#define VBI_MISC_CFG2 0x440473#define FLD_HAMMING_TYPE 0x0f000000474/* Reserved [23:20] */475#define FLD_WSS_FIFO_RST 0x00080000476#define FLD_GS2_FIFO_RST 0x00040000477#define FLD_GS1_FIFO_RST 0x00020000478#define FLD_CC_FIFO_RST 0x00010000479/* Reserved [15:12] */480#define FLD_VBI3_SDID 0x00000f00481#define FLD_VBI2_SDID 0x000000f0482#define FLD_VBI1_SDID 0x0000000f483484/*****************************************************************************/485#define VBI_PAY1 0x444486#define FLD_GS1_FIFO_DAT 0xFF000000487#define FLD_GS1_STAT 0x00FF0000488#define FLD_CC_FIFO_DAT 0x0000FF00489#define FLD_CC_STAT 0x000000FF490491/*****************************************************************************/492#define VBI_PAY2 0x448493#define FLD_WSS_FIFO_DAT 0xff000000494#define FLD_WSS_STAT 0x00ff0000495#define FLD_GS2_FIFO_DAT 0x0000ff00496#define FLD_GS2_STAT 0x000000ff497498/*****************************************************************************/499#define VBI_CUST1_CFG1 0x44c500/* Reserved [31] */501#define FLD_VBI1_CRIWIN 0x7f000000502#define FLD_VBI1_SLICE_DIST 0x00f00000503#define FLD_VBI1_BITINC 0x000fff00504#define FLD_VBI1_HDELAY 0x000000ff505506/*****************************************************************************/507#define VBI_CUST1_CFG2 0x450508#define FLD_VBI1_FC_LENGTH 0x1f000000509#define FLD_VBI1_FRAME_CODE 0x00ffffff510511/*****************************************************************************/512#define VBI_CUST1_CFG3 0x454513#define FLD_VBI1_HAM_EN 0x80000000514#define FLD_VBI1_FIFO_MODE 0x70000000515#define FLD_VBI1_FORMAT_TYPE 0x0f000000516#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000517#define FLD_VBI1_CRI_LENGTH 0x0000f000518#define FLD_VBI1_CRI_MARGIN 0x00000f00519#define FLD_VBI1_CRI_TIME 0x000000ff520521/*****************************************************************************/522#define VBI_CUST2_CFG1 0x458523/* Reserved [31] */524#define FLD_VBI2_CRIWIN 0x7f000000525#define FLD_VBI2_SLICE_DIST 0x00f00000526#define FLD_VBI2_BITINC 0x000fff00527#define FLD_VBI2_HDELAY 0x000000ff528529/*****************************************************************************/530#define VBI_CUST2_CFG2 0x45c531#define FLD_VBI2_FC_LENGTH 0x1f000000532#define FLD_VBI2_FRAME_CODE 0x00ffffff533534/*****************************************************************************/535#define VBI_CUST2_CFG3 0x460536#define FLD_VBI2_HAM_EN 0x80000000537#define FLD_VBI2_FIFO_MODE 0x70000000538#define FLD_VBI2_FORMAT_TYPE 0x0f000000539#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000540#define FLD_VBI2_CRI_LENGTH 0x0000f000541#define FLD_VBI2_CRI_MARGIN 0x00000f00542#define FLD_VBI2_CRI_TIME 0x000000ff543544/*****************************************************************************/545#define VBI_CUST3_CFG1 0x464546/* Reserved [31] */547#define FLD_VBI3_CRIWIN 0x7f000000548#define FLD_VBI3_SLICE_DIST 0x00f00000549#define FLD_VBI3_BITINC 0x000fff00550#define FLD_VBI3_HDELAY 0x000000ff551552/*****************************************************************************/553#define VBI_CUST3_CFG2 0x468554#define FLD_VBI3_FC_LENGTH 0x1f000000555#define FLD_VBI3_FRAME_CODE 0x00ffffff556557/*****************************************************************************/558#define VBI_CUST3_CFG3 0x46c559#define FLD_VBI3_HAM_EN 0x80000000560#define FLD_VBI3_FIFO_MODE 0x70000000561#define FLD_VBI3_FORMAT_TYPE 0x0f000000562#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000563#define FLD_VBI3_CRI_LENGTH 0x0000f000564#define FLD_VBI3_CRI_MARGIN 0x00000f00565#define FLD_VBI3_CRI_TIME 0x000000ff566567/*****************************************************************************/568#define HORIZ_TIM_CTRL 0x470569#define FLD_BGDEL_CNT 0xff000000570/* Reserved [23:22] */571#define FLD_HACTIVE_CNT 0x003ff000572/* Reserved [11:10] */573#define FLD_HBLANK_CNT 0x000003ff574575/*****************************************************************************/576#define VERT_TIM_CTRL 0x474577#define FLD_V656BLANK_CNT 0xff000000578/* Reserved [23:22] */579#define FLD_VACTIVE_CNT 0x003ff000580/* Reserved [11:10] */581#define FLD_VBLANK_CNT 0x000003ff582583/*****************************************************************************/584#define SRC_COMB_CFG 0x478585#define FLD_CCOMB_2LN_CHECK 0x80000000586#define FLD_CCOMB_3LN_EN 0x40000000587#define FLD_CCOMB_2LN_EN 0x20000000588#define FLD_CCOMB_3D_EN 0x10000000589/* Reserved [27] */590#define FLD_LCOMB_3LN_EN 0x04000000591#define FLD_LCOMB_2LN_EN 0x02000000592#define FLD_LCOMB_3D_EN 0x01000000593#define FLD_LUMA_LPF_SEL 0x00c00000594#define FLD_UV_LPF_SEL 0x00300000595#define FLD_BLEND_SLOPE 0x000f0000596#define FLD_CCOMB_REDUCE_EN 0x00008000597/* Reserved [14:10] */598#define FLD_SRC_DECIM_RATIO 0x000003ff599600/*****************************************************************************/601#define CHROMA_VBIOFF_CFG 0x47c602#define FLD_VBI_VOFFSET 0x1f000000603/* Reserved [23:20] */604#define FLD_SC_STEP 0x000fffff605606/*****************************************************************************/607#define FIELD_COUNT 0x480608#define FLD_FIELD_COUNT_FLD 0x000003ff609610/*****************************************************************************/611#define MISC_TIM_CTRL 0x484612#define FLD_DEBOUNCE_COUNT 0xc0000000613#define FLD_VT_LINE_CNT_HYST 0x30000000614/* Reserved [27] */615#define FLD_AFD_STAT 0x07ff0000616#define FLD_VPRES_VERT_EN 0x00008000617/* Reserved [14:12] */618#define FLD_HR32 0x00000800619#define FLD_TDALGN 0x00000400620#define FLD_TDFIELD 0x00000200621/* Reserved [8:6] */622#define FLD_TEMPDEC 0x0000003f623624/*****************************************************************************/625#define DFE_CTRL1 0x488626#define FLD_CLAMP_AUTO_EN 0x80000000627#define FLD_AGC_AUTO_EN 0x40000000628#define FLD_VGA_CRUSH_EN 0x20000000629#define FLD_VGA_AUTO_EN 0x10000000630#define FLD_VBI_GATE_EN 0x08000000631#define FLD_CLAMP_LEVEL 0x07000000632/* Reserved [23:22] */633#define FLD_CLAMP_SKIP_CNT 0x00300000634#define FLD_AGC_GAIN 0x000fff00635/* Reserved [7:6] */636#define FLD_VGA_GAIN 0x0000003f637638/*****************************************************************************/639#define DFE_CTRL2 0x48c640#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000641#define FLD_VGA_TRACK_RANGE 0x0000ff00642#define FLD_VGA_SYNC 0x000000ff643644/*****************************************************************************/645#define DFE_CTRL3 0x490646#define FLD_BP_PERCENT 0xff000000647#define FLD_DFT_THRESHOLD 0x00ff0000648/* Reserved [15:12] */649#define FLD_SYNC_WIDTH_SEL 0x00000600650#define FLD_BP_LOOP_GAIN 0x00000300651#define FLD_SYNC_LOOP_GAIN 0x000000c0652/* Reserved [5:4] */653#define FLD_AGC_LOOP_GAIN 0x0000000c654#define FLD_DCC_LOOP_GAIN 0x00000003655656/*****************************************************************************/657#define PLL_CTRL 0x494658#define FLD_PLL_KD 0xff000000659#define FLD_PLL_KI 0x00ff0000660#define FLD_PLL_MAX_OFFSET 0x0000ffff661662/*****************************************************************************/663#define HTL_CTRL 0x498664/* Reserved [31:24] */665#define FLD_AUTO_LOCK_SPD 0x00080000666#define FLD_MAN_FAST_LOCK 0x00040000667#define FLD_HTL_15K_EN 0x00020000668#define FLD_HTL_500K_EN 0x00010000669#define FLD_HTL_KD 0x0000ff00670#define FLD_HTL_KI 0x000000ff671672/*****************************************************************************/673#define COMB_CTRL 0x49c674#define FLD_COMB_PHASE_LIMIT 0xff000000675#define FLD_CCOMB_ERR_LIMIT 0x00ff0000676#define FLD_LUMA_THRESHOLD 0x0000ff00677#define FLD_LCOMB_ERR_LIMIT 0x000000ff678679/*****************************************************************************/680#define CRUSH_CTRL 0x4a0681#define FLD_WTW_EN 0x00400000682#define FLD_CRUSH_FREQ 0x00200000683#define FLD_MAJ_SEL_EN 0x00100000684#define FLD_MAJ_SEL 0x000c0000685/* Reserved [17:15] */686#define FLD_SYNC_TIP_REDUCE 0x00007e00687/* Reserved [8:6] */688#define FLD_SYNC_TIP_INC 0x0000003f689690/*****************************************************************************/691#define SOFT_RST_CTRL 0x4a4692#define FLD_VD_SOFT_RST 0x00008000693/* Reserved [14:12] */694#define FLD_REG_RST_MSK 0x00000800695#define FLD_VOF_RST_MSK 0x00000400696#define FLD_MVDET_RST_MSK 0x00000200697#define FLD_VBI_RST_MSK 0x00000100698#define FLD_SCALE_RST_MSK 0x00000080699#define FLD_CHROMA_RST_MSK 0x00000040700#define FLD_LUMA_RST_MSK 0x00000020701#define FLD_VTG_RST_MSK 0x00000010702#define FLD_YCSEP_RST_MSK 0x00000008703#define FLD_SRC_RST_MSK 0x00000004704#define FLD_DFE_RST_MSK 0x00000002705/* Reserved [0] */706707/*****************************************************************************/708#define MV_DT_CTRL1 0x4a8709/* Reserved [31:29] */710#define FLD_PSP_STOP_LINE 0x1f000000711/* Reserved [23:21] */712#define FLD_PSP_STRT_LINE 0x001f0000713/* Reserved [15] */714#define FLD_PSP_LLIMW 0x00007f00715/* Reserved [7] */716#define FLD_PSP_ULIMW 0x0000007f717718/*****************************************************************************/719#define MV_DT_CTRL2 0x4aC720#define FLD_CS_STOPWIN 0xff000000721#define FLD_CS_STRTWIN 0x00ff0000722#define FLD_CS_WIDTH 0x0000ff00723#define FLD_PSP_SPEC_VAL 0x000000ff724725/*****************************************************************************/726#define MV_DT_CTRL3 0x4B0727#define FLD_AUTO_RATE_DIS 0x80000000728#define FLD_HLOCK_DIS 0x40000000729#define FLD_SEL_FIELD_CNT 0x20000000730#define FLD_CS_TYPE2_SEL 0x10000000731#define FLD_CS_LINE_THRSH_SEL 0x08000000732#define FLD_CS_ATHRESH_SEL 0x04000000733#define FLD_PSP_SPEC_SEL 0x02000000734#define FLD_PSP_LINES_SEL 0x01000000735#define FLD_FIELD_CNT 0x00f00000736#define FLD_CS_TYPE2_CNT 0x000fc000737#define FLD_CS_LINE_CNT 0x00003f00738#define FLD_CS_ATHRESH_LEV 0x000000ff739740/*****************************************************************************/741#define CHIP_VERSION 0x4b4742/* Cx231xx redefine */743#define VERSION 0x4b4744#define FLD_REV_ID 0x000000ff745746/*****************************************************************************/747#define MISC_DIAG_CTRL 0x4b8748/* Reserved [31:24] */749#define FLD_SC_CONVERGE_THRESH 0x00ff0000750#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00751#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff752753/*****************************************************************************/754#define VBI_PASS_CTRL 0x4bc755#define FLD_VBI_PASS_MD 0x00200000756#define FLD_VBI_SETUP_DIS 0x00100000757#define FLD_PASS_LINE_CTRL 0x000fffff758759/*****************************************************************************/760/* Cx231xx redefine */761#define VCR_DET_CTRL 0x4c0762#define FLD_EN_FIELD_PHASE_DET 0x80000000763#define FLD_EN_HEAD_SW_DET 0x40000000764#define FLD_FIELD_PHASE_LENGTH 0x01ff0000765/* Reserved [29:25] */766#define FLD_FIELD_PHASE_DELAY 0x0000ff00767#define FLD_FIELD_PHASE_LIMIT 0x000000f0768#define FLD_HEAD_SW_DET_LIMIT 0x0000000f769770/*****************************************************************************/771#define DL_CTL 0x800772#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */773#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */774#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */775#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */776/* Reserved [31:5] */777#define FLD_START_8051 0x10000000778#define FLD_DL_ENABLE 0x08000000779#define FLD_DL_AUTO_INC 0x04000000780#define FLD_DL_MAP 0x03000000781782/*****************************************************************************/783#define STD_DET_STATUS 0x804784#define FLD_SPARE_STATUS1 0xff000000785#define FLD_SPARE_STATUS0 0x00ff0000786#define FLD_MOD_DET_STATUS1 0x0000ff00787#define FLD_MOD_DET_STATUS0 0x000000ff788789/*****************************************************************************/790#define AUD_BUILD_NUM 0x806791#define AUD_VER_NUM 0x807792#define STD_DET_CTL 0x808793#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */794#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */795#define FLD_SPARE_CTL0 0xff000000796#define FLD_DIS_DBX 0x00800000797#define FLD_DIS_BTSC 0x00400000798#define FLD_DIS_NICAM_A2 0x00200000799#define FLD_VIDEO_PRESENT 0x00100000800#define FLD_DW8051_VIDEO_FORMAT 0x000f0000801#define FLD_PREF_DEC_MODE 0x0000ff00802#define FLD_AUD_CONFIG 0x000000ff803804/*****************************************************************************/805#define DW8051_INT 0x80c806#define FLD_VIDEO_PRESENT_CHANGE 0x80000000807#define FLD_VIDEO_CHANGE 0x40000000808#define FLD_RDS_READY 0x20000000809#define FLD_AC97_INT 0x10000000810#define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000811#define FLD_NICAM_LOCK 0x04000000812#define FLD_NICAM_UNLOCK 0x02000000813#define FLD_DFT4_TH_CMP 0x01000000814/* Reserved [23:22] */815#define FLD_LOCK_IND_INT 0x00200000816#define FLD_DFT3_TH_CMP 0x00100000817#define FLD_DFT2_TH_CMP 0x00080000818#define FLD_DFT1_TH_CMP 0x00040000819#define FLD_FM2_DFT_TH_CMP 0x00020000820#define FLD_FM1_DFT_TH_CMP 0x00010000821#define FLD_VIDEO_PRESENT_EN 0x00008000822#define FLD_VIDEO_CHANGE_EN 0x00004000823#define FLD_RDS_READY_EN 0x00002000824#define FLD_AC97_INT_EN 0x00001000825#define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800826#define FLD_NICAM_LOCK_EN 0x00000400827#define FLD_NICAM_UNLOCK_EN 0x00000200828#define FLD_DFT4_TH_CMP_EN 0x00000100829/* Reserved [7] */830#define FLD_DW8051_INT6_CTL1 0x00000040831#define FLD_DW8051_INT5_CTL1 0x00000020832#define FLD_DW8051_INT4_CTL1 0x00000010833#define FLD_DW8051_INT3_CTL1 0x00000008834#define FLD_DW8051_INT2_CTL1 0x00000004835#define FLD_DW8051_INT1_CTL1 0x00000002836#define FLD_DW8051_INT0_CTL1 0x00000001837838/*****************************************************************************/839#define GENERAL_CTL 0x810840#define FLD_RDS_INT 0x80000000841#define FLD_NBER_INT 0x40000000842#define FLD_NLL_INT 0x20000000843#define FLD_IFL_INT 0x10000000844#define FLD_FDL_INT 0x08000000845#define FLD_AFC_INT 0x04000000846#define FLD_AMC_INT 0x02000000847#define FLD_AC97_INT_CTL 0x01000000848#define FLD_RDS_INT_DIS 0x00800000849#define FLD_NBER_INT_DIS 0x00400000850#define FLD_NLL_INT_DIS 0x00200000851#define FLD_IFL_INT_DIS 0x00100000852#define FLD_FDL_INT_DIS 0x00080000853#define FLD_FC_INT_DIS 0x00040000854#define FLD_AMC_INT_DIS 0x00020000855#define FLD_AC97_INT_DIS 0x00010000856#define FLD_REV_NUM 0x0000ff00857/* Reserved [7:5] */858#define FLD_DBX_SOFT_RESET_REG 0x00000010859#define FLD_AD_SOFT_RESET_REG 0x00000008860#define FLD_SRC_SOFT_RESET_REG 0x00000004861#define FLD_CDMOD_SOFT_RESET 0x00000002862#define FLD_8051_SOFT_RESET 0x00000001863864/*****************************************************************************/865#define AAGC_CTL 0x814866#define FLD_AFE_12DB_EN 0x80000000867#define FLD_AAGC_DEFAULT_EN 0x40000000868#define FLD_AAGC_DEFAULT 0x3f000000869/* Reserved [23] */870#define FLD_AAGC_GAIN 0x00600000871#define FLD_AAGC_TH 0x001f0000872/* Reserved [15:14] */873#define FLD_AAGC_HYST2 0x00003f00874/* Reserved [7:6] */875#define FLD_AAGC_HYST1 0x0000003f876877/*****************************************************************************/878#define IF_SRC_CTL 0x818879#define FLD_DBX_BYPASS 0x80000000880/* Reserved [30:25] */881#define FLD_IF_SRC_MODE 0x01000000882/* Reserved [23:18] */883#define FLD_IF_SRC_PHASE_INC 0x0001ffff884885/*****************************************************************************/886#define ANALOG_DEMOD_CTL 0x81c887#define FLD_ROT1_PHACC_PROG 0xffff0000888/* Reserved [15] */889#define FLD_FM1_DELAY_FIX 0x00007000890#define FLD_PDF4_SHIFT 0x00000c00891#define FLD_PDF3_SHIFT 0x00000300892#define FLD_PDF2_SHIFT 0x000000c0893#define FLD_PDF1_SHIFT 0x00000030894#define FLD_FMBYPASS_MODE2 0x00000008895#define FLD_FMBYPASS_MODE1 0x00000004896#define FLD_NICAM_MODE 0x00000002897#define FLD_BTSC_FMRADIO_MODE 0x00000001898899/*****************************************************************************/900#define ROT_FREQ_CTL 0x820901#define FLD_ROT3_PHACC_PROG 0xffff0000902#define FLD_ROT2_PHACC_PROG 0x0000ffff903904/*****************************************************************************/905#define FM_CTL 0x824906#define FLD_FM2_DC_FB_SHIFT 0xf0000000907#define FLD_FM2_DC_INT_SHIFT 0x0f000000908#define FLD_FM2_AFC_RESET 0x00800000909#define FLD_FM2_DC_PASS_IN 0x00400000910#define FLD_FM2_DAGC_SHIFT 0x00380000911#define FLD_FM2_CORDIC_SHIFT 0x00070000912#define FLD_FM1_DC_FB_SHIFT 0x0000f000913#define FLD_FM1_DC_INT_SHIFT 0x00000f00914#define FLD_FM1_AFC_RESET 0x00000080915#define FLD_FM1_DC_PASS_IN 0x00000040916#define FLD_FM1_DAGC_SHIFT 0x00000038917#define FLD_FM1_CORDIC_SHIFT 0x00000007918919/*****************************************************************************/920#define LPF_PDF_CTL 0x828921/* Reserved [31:30] */922#define FLD_LPF32_SHIFT1 0x30000000923#define FLD_LPF32_SHIFT2 0x0c000000924#define FLD_LPF160_SHIFTA 0x03000000925#define FLD_LPF160_SHIFTB 0x00c00000926#define FLD_LPF160_SHIFTC 0x00300000927#define FLD_LPF32_COEF_SEL2 0x000c0000928#define FLD_LPF32_COEF_SEL1 0x00030000929#define FLD_LPF160_COEF_SELC 0x0000c000930#define FLD_LPF160_COEF_SELB 0x00003000931#define FLD_LPF160_COEF_SELA 0x00000c00932#define FLD_LPF160_IN_EN_REG 0x00000300933#define FLD_PDF4_PDF_SEL 0x000000c0934#define FLD_PDF3_PDF_SEL 0x00000030935#define FLD_PDF2_PDF_SEL 0x0000000c936#define FLD_PDF1_PDF_SEL 0x00000003937938/*****************************************************************************/939#define DFT1_CTL1 0x82c940#define FLD_DFT1_DWELL 0xffff0000941#define FLD_DFT1_FREQ 0x0000ffff942943/*****************************************************************************/944#define DFT1_CTL2 0x830945#define FLD_DFT1_THRESHOLD 0xffffff00946#define FLD_DFT1_CMP_CTL 0x00000080947#define FLD_DFT1_AVG 0x00000070948/* Reserved [3:1] */949#define FLD_DFT1_START 0x00000001950951/*****************************************************************************/952#define DFT1_STATUS 0x834953#define FLD_DFT1_DONE 0x80000000954#define FLD_DFT1_TH_CMP_STAT 0x40000000955#define FLD_DFT1_RESULT 0x3fffffff956957/*****************************************************************************/958#define DFT2_CTL1 0x838959#define FLD_DFT2_DWELL 0xffff0000960#define FLD_DFT2_FREQ 0x0000ffff961962/*****************************************************************************/963#define DFT2_CTL2 0x83C964#define FLD_DFT2_THRESHOLD 0xffffff00965#define FLD_DFT2_CMP_CTL 0x00000080966#define FLD_DFT2_AVG 0x00000070967/* Reserved [3:1] */968#define FLD_DFT2_START 0x00000001969970/*****************************************************************************/971#define DFT2_STATUS 0x840972#define FLD_DFT2_DONE 0x80000000973#define FLD_DFT2_TH_CMP_STAT 0x40000000974#define FLD_DFT2_RESULT 0x3fffffff975976/*****************************************************************************/977#define DFT3_CTL1 0x844978#define FLD_DFT3_DWELL 0xffff0000979#define FLD_DFT3_FREQ 0x0000ffff980981/*****************************************************************************/982#define DFT3_CTL2 0x848983#define FLD_DFT3_THRESHOLD 0xffffff00984#define FLD_DFT3_CMP_CTL 0x00000080985#define FLD_DFT3_AVG 0x00000070986/* Reserved [3:1] */987#define FLD_DFT3_START 0x00000001988989/*****************************************************************************/990#define DFT3_STATUS 0x84c991#define FLD_DFT3_DONE 0x80000000992#define FLD_DFT3_TH_CMP_STAT 0x40000000993#define FLD_DFT3_RESULT 0x3fffffff994995/*****************************************************************************/996#define DFT4_CTL1 0x850997#define FLD_DFT4_DWELL 0xffff0000998#define FLD_DFT4_FREQ 0x0000ffff9991000/*****************************************************************************/1001#define DFT4_CTL2 0x8541002#define FLD_DFT4_THRESHOLD 0xffffff001003#define FLD_DFT4_CMP_CTL 0x000000801004#define FLD_DFT4_AVG 0x000000701005/* Reserved [3:1] */1006#define FLD_DFT4_START 0x0000000110071008/*****************************************************************************/1009#define DFT4_STATUS 0x8581010#define FLD_DFT4_DONE 0x800000001011#define FLD_DFT4_TH_CMP_STAT 0x400000001012#define FLD_DFT4_RESULT 0x3fffffff10131014/*****************************************************************************/1015#define AM_MTS_DET 0x85c1016#define FLD_AM_MTS_MODE 0x800000001017/* Reserved [30:26] */1018#define FLD_AM_SUB 0x020000001019#define FLD_AM_GAIN_EN 0x010000001020/* Reserved [23:16] */1021#define FLD_AMMTS_GAIN_SCALE 0x0000e0001022#define FLD_MTS_PDF_SHIFT 0x000018001023#define FLD_AM_REG_GAIN 0x000007001024#define FLD_AGC_REF 0x000000ff10251026/*****************************************************************************/1027#define ANALOG_MUX_CTL 0x8601028/* Reserved [31:29] */1029#define FLD_MUX21_SEL 0x100000001030#define FLD_MUX20_SEL 0x080000001031#define FLD_MUX19_SEL 0x040000001032#define FLD_MUX18_SEL 0x020000001033#define FLD_MUX17_SEL 0x010000001034#define FLD_MUX16_SEL 0x008000001035#define FLD_MUX15_SEL 0x004000001036#define FLD_MUX14_SEL 0x003000001037#define FLD_MUX13_SEL 0x000C00001038#define FLD_MUX12_SEL 0x000200001039#define FLD_MUX11_SEL 0x000180001040#define FLD_MUX10_SEL 0x000040001041#define FLD_MUX9_SEL 0x000020001042#define FLD_MUX8_SEL 0x000010001043#define FLD_MUX7_SEL 0x000008001044#define FLD_MUX6_SEL 0x000006001045#define FLD_MUX5_SEL 0x000001001046#define FLD_MUX4_SEL 0x000000c01047#define FLD_MUX3_SEL 0x000000301048#define FLD_MUX2_SEL 0x0000000c1049#define FLD_MUX1_SEL 0x0000000310501051/*****************************************************************************/1052/* Cx231xx redefine */1053#define DPLL_CTRL1 0x8641054#define DIG_PLL_CTL1 0x86410551056#define FLD_PLL_STATUS 0x070000001057#define FLD_BANDWIDTH_SELECT 0x000300001058#define FLD_PLL_SHIFT_REG 0x000070001059#define FLD_PHASE_SHIFT 0x000007ff10601061/*****************************************************************************/1062/* Cx231xx redefine */1063#define DPLL_CTRL2 0x8681064#define DIG_PLL_CTL2 0x8681065#define FLD_PLL_UNLOCK_THR 0xff0000001066#define FLD_PLL_LOCK_THR 0x00ff00001067/* Reserved [15:8] */1068#define FLD_AM_PDF_SEL2 0x000000c01069#define FLD_AM_PDF_SEL1 0x000000301070#define FLD_DPLL_FSM_CTRL 0x0000000c1071/* Reserved [1] */1072#define FLD_PLL_PILOT_DET 0x0000000110731074/*****************************************************************************/1075/* Cx231xx redefine */1076#define DPLL_CTRL3 0x86c1077#define DIG_PLL_CTL3 0x86c1078#define FLD_DISABLE_LOOP 0x010000001079#define FLD_A1_DS1_SEL 0x000c00001080#define FLD_A1_DS2_SEL 0x000300001081#define FLD_A1_KI 0x0000ff001082#define FLD_A1_KD 0x000000ff10831084/*****************************************************************************/1085/* Cx231xx redefine */1086#define DPLL_CTRL4 0x8701087#define DIG_PLL_CTL4 0x8701088#define FLD_A2_DS1_SEL 0x000c00001089#define FLD_A2_DS2_SEL 0x000300001090#define FLD_A2_KI 0x0000ff001091#define FLD_A2_KD 0x000000ff10921093/*****************************************************************************/1094/* Cx231xx redefine */1095#define DPLL_CTRL5 0x8741096#define DIG_PLL_CTL5 0x8741097#define FLD_TRK_DS1_SEL 0x000c00001098#define FLD_TRK_DS2_SEL 0x000300001099#define FLD_TRK_KI 0x0000ff001100#define FLD_TRK_KD 0x000000ff11011102/*****************************************************************************/1103#define DEEMPH_GAIN_CTL 0x8781104#define FLD_DEEMPH2_GAIN 0xFFFF00001105#define FLD_DEEMPH1_GAIN 0x0000FFFF11061107/*****************************************************************************/1108/* Cx231xx redefine */1109#define DEEMPH_COEFF1 0x87c1110#define DEEMPH_COEF1 0x87c1111#define FLD_DEEMPH_B0 0xffff00001112#define FLD_DEEMPH_A0 0x0000ffff11131114/*****************************************************************************/1115/* Cx231xx redefine */1116#define DEEMPH_COEFF2 0x8801117#define DEEMPH_COEF2 0x8801118#define FLD_DEEMPH_B1 0xFFFF00001119#define FLD_DEEMPH_A1 0x0000FFFF11201121/*****************************************************************************/1122#define DBX1_CTL1 0x8841123#define FLD_DBX1_WBE_GAIN 0xffff00001124#define FLD_DBX1_IN_GAIN 0x0000ffff11251126/*****************************************************************************/1127#define DBX1_CTL2 0x8881128#define FLD_DBX1_SE_BYPASS 0xffff00001129#define FLD_DBX1_SE_GAIN 0x0000ffff11301131/*****************************************************************************/1132#define DBX1_RMS_SE 0x88C1133#define FLD_DBX1_RMS_WBE 0xffff00001134#define FLD_DBX1_RMS_SE_FLD 0x0000ffff11351136/*****************************************************************************/1137#define DBX2_CTL1 0x8901138#define FLD_DBX2_WBE_GAIN 0xffff00001139#define FLD_DBX2_IN_GAIN 0x0000ffff11401141/*****************************************************************************/1142#define DBX2_CTL2 0x8941143#define FLD_DBX2_SE_BYPASS 0xffff00001144#define FLD_DBX2_SE_GAIN 0x0000ffff11451146/*****************************************************************************/1147#define DBX2_RMS_SE 0x8981148#define FLD_DBX2_RMS_WBE 0xffff00001149#define FLD_DBX2_RMS_SE_FLD 0x0000ffff11501151/*****************************************************************************/1152#define AM_FM_DIFF 0x89c1153/* Reserved [31] */1154#define FLD_FM_DIFF_OUT 0x7fff00001155/* Reserved [15] */1156#define FLD_AM_DIFF_OUT 0x00007fff11571158/*****************************************************************************/1159#define NICAM_FAW 0x8a01160#define FLD_FAWDETWINEND 0xFc0000001161#define FLD_FAWDETWINSTR 0x03ff00001162/* Reserved [15:12] */1163#define FLD_FAWDETTHRSHLD3 0x00000f001164#define FLD_FAWDETTHRSHLD2 0x000000f01165#define FLD_FAWDETTHRSHLD1 0x0000000f11661167/*****************************************************************************/1168/* Cx231xx redefine */1169#define DEEMPH_GAIN 0x8a41170#define NICAM_DEEMPHGAIN 0x8a41171/* Reserved [31:18] */1172#define FLD_DEEMPHGAIN 0x0003ffff11731174/*****************************************************************************/1175/* Cx231xx redefine */1176#define DEEMPH_NUMER1 0x8a81177#define NICAM_DEEMPHNUMER1 0x8a81178/* Reserved [31:18] */1179#define FLD_DEEMPHNUMER1 0x0003ffff11801181/*****************************************************************************/1182/* Cx231xx redefine */1183#define DEEMPH_NUMER2 0x8ac1184#define NICAM_DEEMPHNUMER2 0x8ac1185/* Reserved [31:18] */1186#define FLD_DEEMPHNUMER2 0x0003ffff11871188/*****************************************************************************/1189/* Cx231xx redefine */1190#define DEEMPH_DENOM1 0x8b01191#define NICAM_DEEMPHDENOM1 0x8b01192/* Reserved [31:18] */1193#define FLD_DEEMPHDENOM1 0x0003ffff11941195/*****************************************************************************/1196/* Cx231xx redefine */1197#define DEEMPH_DENOM2 0x8b41198#define NICAM_DEEMPHDENOM2 0x8b41199/* Reserved [31:18] */1200#define FLD_DEEMPHDENOM2 0x0003ffff12011202/*****************************************************************************/1203#define NICAM_ERRLOG_CTL1 0x8B81204/* Reserved [31:28] */1205#define FLD_ERRINTRPTTHSHLD1 0x0fff00001206/* Reserved [15:12] */1207#define FLD_ERRLOGPERIOD 0x00000fff12081209/*****************************************************************************/1210#define NICAM_ERRLOG_CTL2 0x8bc1211/* Reserved [31:28] */1212#define FLD_ERRINTRPTTHSHLD3 0x0fff00001213/* Reserved [15:12] */1214#define FLD_ERRINTRPTTHSHLD2 0x00000fff12151216/*****************************************************************************/1217#define NICAM_ERRLOG_STS1 0x8c01218/* Reserved [31:28] */1219#define FLD_ERRLOG2 0x0fff00001220/* Reserved [15:12] */1221#define FLD_ERRLOG1 0x00000fff12221223/*****************************************************************************/1224#define NICAM_ERRLOG_STS2 0x8c41225/* Reserved [31:12] */1226#define FLD_ERRLOG3 0x00000fff12271228/*****************************************************************************/1229#define NICAM_STATUS 0x8c81230/* Reserved [31:20] */1231#define FLD_NICAM_CIB 0x000c00001232#define FLD_NICAM_LOCK_STAT 0x000200001233#define FLD_NICAM_MUTE 0x000100001234#define FLD_NICAMADDIT_DATA 0x0000ffe01235#define FLD_NICAMCNTRL 0x0000001f12361237/*****************************************************************************/1238#define DEMATRIX_CTL 0x8cc1239#define FLD_AC97_IN_SHIFT 0xf00000001240#define FLD_I2S_IN_SHIFT 0x0f0000001241#define FLD_DEMATRIX_SEL_CTL 0x00ff00001242/* Reserved [15:11] */1243#define FLD_DMTRX_BYPASS 0x000004001244#define FLD_DEMATRIX_MODE 0x000003001245/* Reserved [7:6] */1246#define FLD_PH_DBX_SEL 0x000000201247#define FLD_PH_CH_SEL 0x000000101248#define FLD_PHASE_FIX 0x0000000f12491250/*****************************************************************************/1251#define PATH1_CTL1 0x8d01252/* Reserved [31:29] */1253#define FLD_PATH1_MUTE_CTL 0x1f0000001254/* Reserved [23:22] */1255#define FLD_PATH1_AVC_CG 0x003000001256#define FLD_PATH1_AVC_RT 0x000f00001257#define FLD_PATH1_AVC_AT 0x0000f0001258#define FLD_PATH1_AVC_STEREO 0x000008001259#define FLD_PATH1_AVC_CR 0x000007001260#define FLD_PATH1_AVC_RMS_CON 0x000000f01261#define FLD_PATH1_SEL_CTL 0x0000000f12621263/*****************************************************************************/1264#define PATH1_VOL_CTL 0x8d41265#define FLD_PATH1_AVC_THRESHOLD 0x7fff00001266#define FLD_PATH1_BAL_LEFT 0x000080001267#define FLD_PATH1_BAL_LEVEL 0x00007f001268#define FLD_PATH1_VOLUME 0x000000ff12691270/*****************************************************************************/1271#define PATH1_EQ_CTL 0x8d81272/* Reserved [31:30] */1273#define FLD_PATH1_EQ_TREBLE_VOL 0x3f0000001274/* Reserved [23:22] */1275#define FLD_PATH1_EQ_MID_VOL 0x003f00001276/* Reserved [15:14] */1277#define FLD_PATH1_EQ_BASS_VOL 0x00003f001278/* Reserved [7:1] */1279#define FLD_PATH1_EQ_BAND_SEL 0x0000000112801281/*****************************************************************************/1282#define PATH1_SC_CTL 0x8dc1283#define FLD_PATH1_SC_THRESHOLD 0x7fff00001284#define FLD_PATH1_SC_RT 0x0000f0001285#define FLD_PATH1_SC_AT 0x00000f001286#define FLD_PATH1_SC_STEREO 0x000000801287#define FLD_PATH1_SC_CR 0x000000701288#define FLD_PATH1_SC_RMS_CON 0x0000000f12891290/*****************************************************************************/1291#define PATH2_CTL1 0x8e01292/* Reserved [31:26] */1293#define FLD_PATH2_MUTE_CTL 0x030000001294/* Reserved [23:22] */1295#define FLD_PATH2_AVC_CG 0x003000001296#define FLD_PATH2_AVC_RT 0x000f00001297#define FLD_PATH2_AVC_AT 0x0000f0001298#define FLD_PATH2_AVC_STEREO 0x000008001299#define FLD_PATH2_AVC_CR 0x000007001300#define FLD_PATH2_AVC_RMS_CON 0x000000f01301#define FLD_PATH2_SEL_CTL 0x0000000f13021303/*****************************************************************************/1304#define PATH2_VOL_CTL 0x8e41305#define FLD_PATH2_AVC_THRESHOLD 0xffff00001306#define FLD_PATH2_BAL_LEFT 0x000080001307#define FLD_PATH2_BAL_LEVEL 0x00007f001308#define FLD_PATH2_VOLUME 0x000000ff13091310/*****************************************************************************/1311#define PATH2_EQ_CTL 0x8e81312/* Reserved [31:30] */1313#define FLD_PATH2_EQ_TREBLE_VOL 0x3f0000001314/* Reserved [23:22] */1315#define FLD_PATH2_EQ_MID_VOL 0x003f00001316/* Reserved [15:14] */1317#define FLD_PATH2_EQ_BASS_VOL 0x00003f001318/* Reserved [7:1] */1319#define FLD_PATH2_EQ_BAND_SEL 0x0000000113201321/*****************************************************************************/1322#define PATH2_SC_CTL 0x8eC1323#define FLD_PATH2_SC_THRESHOLD 0xffff00001324#define FLD_PATH2_SC_RT 0x0000f0001325#define FLD_PATH2_SC_AT 0x00000f001326#define FLD_PATH2_SC_STEREO 0x000000801327#define FLD_PATH2_SC_CR 0x000000701328#define FLD_PATH2_SC_RMS_CON 0x0000000f13291330/*****************************************************************************/1331#define SRC_CTL 0x8f01332#define FLD_SRC_STATUS 0xffffff001333#define FLD_FIFO_LF_EN 0x000000fc1334#define FLD_BYPASS_LI 0x000000021335#define FLD_BYPASS_PF 0x0000000113361337/*****************************************************************************/1338#define SRC_LF_COEF 0x8f41339#define FLD_LOOP_FILTER_COEF2 0xffff00001340#define FLD_LOOP_FILTER_COEF1 0x0000ffff13411342/*****************************************************************************/1343#define SRC1_CTL 0x8f81344/* Reserved [31:28] */1345#define FLD_SRC1_FIFO_RD_TH 0x0f0000001346/* Reserved [23:18] */1347#define FLD_SRC1_PHASE_INC 0x0003ffff13481349/*****************************************************************************/1350#define SRC2_CTL 0x8fc1351/* Reserved [31:28] */1352#define FLD_SRC2_FIFO_RD_TH 0x0f0000001353/* Reserved [23:18] */1354#define FLD_SRC2_PHASE_INC 0x0003ffff13551356/*****************************************************************************/1357#define SRC3_CTL 0x9001358/* Reserved [31:28] */1359#define FLD_SRC3_FIFO_RD_TH 0x0f0000001360/* Reserved [23:18] */1361#define FLD_SRC3_PHASE_INC 0x0003ffff13621363/*****************************************************************************/1364#define SRC4_CTL 0x9041365/* Reserved [31:28] */1366#define FLD_SRC4_FIFO_RD_TH 0x0f0000001367/* Reserved [23:18] */1368#define FLD_SRC4_PHASE_INC 0x0003ffff13691370/*****************************************************************************/1371#define SRC5_CTL 0x9081372/* Reserved [31:28] */1373#define FLD_SRC5_FIFO_RD_TH 0x0f0000001374/* Reserved [23:18] */1375#define FLD_SRC5_PHASE_INC 0x0003ffff13761377/*****************************************************************************/1378#define SRC6_CTL 0x90c1379/* Reserved [31:28] */1380#define FLD_SRC6_FIFO_RD_TH 0x0f0000001381/* Reserved [23:18] */1382#define FLD_SRC6_PHASE_INC 0x0003ffff13831384/*****************************************************************************/1385#define BAND_OUT_SEL 0x9101386#define FLD_SRC6_IN_SEL 0xc00000001387#define FLD_SRC6_CLK_SEL 0x300000001388#define FLD_SRC5_IN_SEL 0x0c0000001389#define FLD_SRC5_CLK_SEL 0x030000001390#define FLD_SRC4_IN_SEL 0x00c000001391#define FLD_SRC4_CLK_SEL 0x003000001392#define FLD_SRC3_IN_SEL 0x000c00001393#define FLD_SRC3_CLK_SEL 0x000300001394#define FLD_BASEBAND_BYPASS_CTL 0x0000ff001395#define FLD_AC97_SRC_SEL 0x000000c01396#define FLD_I2S_SRC_SEL 0x000000301397#define FLD_PARALLEL2_SRC_SEL 0x0000000c1398#define FLD_PARALLEL1_SRC_SEL 0x0000000313991400/*****************************************************************************/1401#define I2S_IN_CTL 0x9141402/* Reserved [31:11] */1403#define FLD_I2S_UP2X_BW20K 0x000004001404#define FLD_I2S_UP2X_BYPASS 0x000002001405#define FLD_I2S_IN_MASTER_MODE 0x000001001406#define FLD_I2S_IN_SONY_MODE 0x000000801407#define FLD_I2S_IN_RIGHT_JUST 0x000000401408#define FLD_I2S_IN_WS_SEL 0x000000201409#define FLD_I2S_IN_BCN_DEL 0x0000001f14101411/*****************************************************************************/1412#define I2S_OUT_CTL 0x9181413/* Reserved [31:17] */1414#define FLD_I2S_OUT_SOFT_RESET_EN 0x000100001415/* Reserved [15:9] */1416#define FLD_I2S_OUT_MASTER_MODE 0x000001001417#define FLD_I2S_OUT_SONY_MODE 0x000000801418#define FLD_I2S_OUT_RIGHT_JUST 0x000000401419#define FLD_I2S_OUT_WS_SEL 0x000000201420#define FLD_I2S_OUT_BCN_DEL 0x0000001f14211422/*****************************************************************************/1423#define AC97_CTL 0x91c1424/* Reserved [31:26] */1425#define FLD_AC97_UP2X_BW20K 0x020000001426#define FLD_AC97_UP2X_BYPASS 0x010000001427/* Reserved [23:17] */1428#define FLD_AC97_RST_ACL 0x000100001429/* Reserved [15:9] */1430#define FLD_AC97_WAKE_UP_SYNC 0x000001001431/* Reserved [7:1] */1432#define FLD_AC97_SHUTDOWN 0x0000000114331434/* Cx231xx redefine */1435#define QPSK_IAGC_CTL1 0x94c1436#define QPSK_IAGC_CTL2 0x9501437#define QPSK_FEPR_FREQ 0x9541438#define QPSK_BTL_CTL1 0x9581439#define QPSK_BTL_CTL2 0x95c1440#define QPSK_CTL_CTL1 0x9601441#define QPSK_CTL_CTL2 0x9641442#define QPSK_MF_FAGC_CTL 0x9681443#define QPSK_EQ_CTL 0x96c1444#define QPSK_LOCK_CTL 0x97014451446/*****************************************************************************/1447#define FM1_DFT_CTL 0x9a81448#define FLD_FM1_DFT_THRESHOLD 0xffff00001449/* Reserved [15:8] */1450#define FLD_FM1_DFT_CMP_CTL 0x000000801451#define FLD_FM1_DFT_AVG 0x000000701452/* Reserved [3:1] */1453#define FLD_FM1_DFT_START 0x0000000114541455/*****************************************************************************/1456#define FM1_DFT_STATUS 0x9ac1457#define FLD_FM1_DFT_DONE 0x800000001458/* Reserved [30:19] */1459#define FLD_FM_DFT_TH_CMP 0x000400001460#define FLD_FM1_DFT 0x0003ffff14611462/*****************************************************************************/1463#define FM2_DFT_CTL 0x9b01464#define FLD_FM2_DFT_THRESHOLD 0xffff00001465/* Reserved [15:8] */1466#define FLD_FM2_DFT_CMP_CTL 0x000000801467#define FLD_FM2_DFT_AVG 0x000000701468/* Reserved [3:1] */1469#define FLD_FM2_DFT_START 0x0000000114701471/*****************************************************************************/1472#define FM2_DFT_STATUS 0x9b41473#define FLD_FM2_DFT_DONE 0x800000001474/* Reserved [30:19] */1475#define FLD_FM2_DFT_TH_CMP_STAT 0x000400001476#define FLD_FM2_DFT 0x0003ffff14771478/*****************************************************************************/1479/* Cx231xx redefine */1480#define AAGC_STATUS_REG 0x9b81481#define AAGC_STATUS 0x9b81482/* Reserved [31:27] */1483#define FLD_FM2_DAGC_OUT 0x070000001484/* Reserved [23:19] */1485#define FLD_FM1_DAGC_OUT 0x000700001486/* Reserved [15:6] */1487#define FLD_AFE_VGA_OUT 0x0000003f14881489/*****************************************************************************/1490#define MTS_GAIN_STATUS 0x9bc1491/* Reserved [31:14] */1492#define FLD_MTS_GAIN 0x00003fff14931494#define RDS_OUT 0x9c01495#define FLD_RDS_Q 0xffff00001496#define FLD_RDS_I 0x0000ffff14971498/*****************************************************************************/1499#define AUTOCONFIG_REG 0x9c41500/* Reserved [31:4] */1501#define FLD_AUTOCONFIG_MODE 0x0000000f15021503#define FM_AFC 0x9c81504#define FLD_FM2_AFC 0xffff00001505#define FLD_FM1_AFC 0x0000ffff15061507/*****************************************************************************/1508/* Cx231xx redefine */1509#define NEW_SPARE 0x9cc1510#define NEW_SPARE_REG 0x9cc15111512/*****************************************************************************/1513#define DBX_ADJ 0x9d01514/* Reserved [31:28] */1515#define FLD_DBX2_ADJ 0x0fff00001516/* Reserved [15:12] */1517#define FLD_DBX1_ADJ 0x00000fff15181519#define VID_FMT_AUTO 01520#define VID_FMT_NTSC_M 11521#define VID_FMT_NTSC_J 21522#define VID_FMT_NTSC_443 31523#define VID_FMT_PAL_BDGHI 41524#define VID_FMT_PAL_M 51525#define VID_FMT_PAL_N 61526#define VID_FMT_PAL_NC 71527#define VID_FMT_PAL_60 81528#define VID_FMT_SECAM 121529#define VID_FMT_SECAM_60 1315301531#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */1532#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */1533#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */1534#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */15351536#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */1537#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */1538#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */15391540#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */1541#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */1542#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */15431544#define TWO_TAP_FILT 01545#define THREE_TAP_FILT 11546#define FOUR_TAP_FILT 21547#define FIVE_TAP_FILT 315481549#define AUD_CHAN_SRC_PARALLEL 01550#define AUD_CHAN_SRC_I2S_INPUT 11551#define AUD_CHAN_SRC_FLATIRON 21552#define AUD_CHAN_SRC_PARALLEL3 315531554#define OUT_MODE_601 01555#define OUT_MODE_656 11556#define OUT_MODE_VIP11 21557#define OUT_MODE_VIP20 315581559#define PHASE_INC_49MHZ 0x0df221560#define PHASE_INC_56MHZ 0x0fa5b1561#define PHASE_INC_28MHZ 0x01000015621563#endif156415651566