Path: blob/master/drivers/media/video/cx23885/cx23885.h
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/*1* Driver for the Conexant CX23885 PCIe bridge2*3* Copyright (c) 2006 Steven Toth <[email protected]>4*5* This program is free software; you can redistribute it and/or modify6* it under the terms of the GNU General Public License as published by7* the Free Software Foundation; either version 2 of the License, or8* (at your option) any later version.9*10* This program is distributed in the hope that it will be useful,11* but WITHOUT ANY WARRANTY; without even the implied warranty of12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the13*14* GNU General Public License for more details.15*16* You should have received a copy of the GNU General Public License17* along with this program; if not, write to the Free Software18* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.19*/2021#include <linux/pci.h>22#include <linux/i2c.h>23#include <linux/i2c-algo-bit.h>24#include <linux/kdev_t.h>25#include <linux/slab.h>2627#include <media/v4l2-device.h>28#include <media/tuner.h>29#include <media/tveeprom.h>30#include <media/videobuf-dma-sg.h>31#include <media/videobuf-dvb.h>32#include <media/rc-core.h>3334#include "btcx-risc.h"35#include "cx23885-reg.h"36#include "media/cx2341x.h"3738#include <linux/version.h>39#include <linux/mutex.h>4041#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)4243#define UNSET (-1U)4445#define CX23885_MAXBOARDS 84647/* Max number of inputs by card */48#define MAX_CX23885_INPUT 849#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])50#define RESOURCE_OVERLAY 151#define RESOURCE_VIDEO 252#define RESOURCE_VBI 45354#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */5556#define CX23885_BOARD_NOAUTO UNSET57#define CX23885_BOARD_UNKNOWN 058#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 159#define CX23885_BOARD_HAUPPAUGE_HVR1800 260#define CX23885_BOARD_HAUPPAUGE_HVR1250 361#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 462#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 563#define CX23885_BOARD_HAUPPAUGE_HVR1500 664#define CX23885_BOARD_HAUPPAUGE_HVR1200 765#define CX23885_BOARD_HAUPPAUGE_HVR1700 866#define CX23885_BOARD_HAUPPAUGE_HVR1400 967#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 1068#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 1169#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 1270#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 1371#define CX23885_BOARD_TBS_6920 1472#define CX23885_BOARD_TEVII_S470 1573#define CX23885_BOARD_DVBWORLD_2005 1674#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 1775#define CX23885_BOARD_HAUPPAUGE_HVR1270 1876#define CX23885_BOARD_HAUPPAUGE_HVR1275 1977#define CX23885_BOARD_HAUPPAUGE_HVR1255 2078#define CX23885_BOARD_HAUPPAUGE_HVR1210 2179#define CX23885_BOARD_MYGICA_X8506 2280#define CX23885_BOARD_MAGICPRO_PROHDTVE2 2381#define CX23885_BOARD_HAUPPAUGE_HVR1850 2482#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 2583#define CX23885_BOARD_HAUPPAUGE_HVR1290 2684#define CX23885_BOARD_MYGICA_X8558PRO 2785#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 2886#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 2987#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 308889#define GPIO_0 0x0000000190#define GPIO_1 0x0000000291#define GPIO_2 0x0000000492#define GPIO_3 0x0000000893#define GPIO_4 0x0000001094#define GPIO_5 0x0000002095#define GPIO_6 0x0000004096#define GPIO_7 0x0000008097#define GPIO_8 0x0000010098#define GPIO_9 0x0000020099#define GPIO_10 0x00000400100#define GPIO_11 0x00000800101#define GPIO_12 0x00001000102#define GPIO_13 0x00002000103#define GPIO_14 0x00004000104#define GPIO_15 0x00008000105106/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */107#define CX23885_NORMS (\108V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \109V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \110V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \111V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)112113struct cx23885_fmt {114char *name;115u32 fourcc; /* v4l2 format id */116int depth;117int flags;118u32 cxformat;119};120121struct cx23885_ctrl {122struct v4l2_queryctrl v;123u32 off;124u32 reg;125u32 mask;126u32 shift;127};128129struct cx23885_tvnorm {130char *name;131v4l2_std_id id;132u32 cxiformat;133u32 cxoformat;134};135136struct cx23885_fh {137struct cx23885_dev *dev;138enum v4l2_buf_type type;139int radio;140u32 resources;141142/* video overlay */143struct v4l2_window win;144struct v4l2_clip *clips;145unsigned int nclips;146147/* video capture */148struct cx23885_fmt *fmt;149unsigned int width, height;150151/* vbi capture */152struct videobuf_queue vidq;153struct videobuf_queue vbiq;154155/* MPEG Encoder specifics ONLY */156struct videobuf_queue mpegq;157atomic_t v4l_reading;158};159160enum cx23885_itype {161CX23885_VMUX_COMPOSITE1 = 1,162CX23885_VMUX_COMPOSITE2,163CX23885_VMUX_COMPOSITE3,164CX23885_VMUX_COMPOSITE4,165CX23885_VMUX_SVIDEO,166CX23885_VMUX_COMPONENT,167CX23885_VMUX_TELEVISION,168CX23885_VMUX_CABLE,169CX23885_VMUX_DVB,170CX23885_VMUX_DEBUG,171CX23885_RADIO,172};173174enum cx23885_src_sel_type {175CX23885_SRC_SEL_EXT_656_VIDEO = 0,176CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO177};178179/* buffer for one video frame */180struct cx23885_buffer {181/* common v4l buffer stuff -- must be first */182struct videobuf_buffer vb;183184/* cx23885 specific */185unsigned int bpl;186struct btcx_riscmem risc;187struct cx23885_fmt *fmt;188u32 count;189};190191struct cx23885_input {192enum cx23885_itype type;193unsigned int vmux;194u32 gpio0, gpio1, gpio2, gpio3;195};196197typedef enum {198CX23885_MPEG_UNDEFINED = 0,199CX23885_MPEG_DVB,200CX23885_ANALOG_VIDEO,201CX23885_MPEG_ENCODER,202} port_t;203204struct cx23885_board {205char *name;206port_t porta, portb, portc;207int num_fds_portb, num_fds_portc;208unsigned int tuner_type;209unsigned int radio_type;210unsigned char tuner_addr;211unsigned char radio_addr;212unsigned int tuner_bus;213214/* Vendors can and do run the PCIe bridge at different215* clock rates, driven physically by crystals on the PCBs.216* The core has to accommodate this. This allows the user217* to add new boards with new frequencys. The value is218* expressed in Hz.219*220* The core framework will default this value based on221* current designs, but it can vary.222*/223u32 clk_freq;224struct cx23885_input input[MAX_CX23885_INPUT];225int ci_type; /* for NetUP */226};227228struct cx23885_subid {229u16 subvendor;230u16 subdevice;231u32 card;232};233234struct cx23885_i2c {235struct cx23885_dev *dev;236237int nr;238239/* i2c i/o */240struct i2c_adapter i2c_adap;241struct i2c_algo_bit_data i2c_algo;242struct i2c_client i2c_client;243u32 i2c_rc;244245/* 885 registers used for raw addess */246u32 i2c_period;247u32 reg_ctrl;248u32 reg_stat;249u32 reg_addr;250u32 reg_rdata;251u32 reg_wdata;252};253254struct cx23885_dmaqueue {255struct list_head active;256struct list_head queued;257struct timer_list timeout;258struct btcx_riscmem stopper;259u32 count;260};261262struct cx23885_tsport {263struct cx23885_dev *dev;264265int nr;266int sram_chno;267268struct videobuf_dvb_frontends frontends;269270/* dma queues */271struct cx23885_dmaqueue mpegq;272u32 ts_packet_size;273u32 ts_packet_count;274275int width;276int height;277278spinlock_t slock;279280/* registers */281u32 reg_gpcnt;282u32 reg_gpcnt_ctl;283u32 reg_dma_ctl;284u32 reg_lngth;285u32 reg_hw_sop_ctrl;286u32 reg_gen_ctrl;287u32 reg_bd_pkt_status;288u32 reg_sop_status;289u32 reg_fifo_ovfl_stat;290u32 reg_vld_misc;291u32 reg_ts_clk_en;292u32 reg_ts_int_msk;293u32 reg_ts_int_stat;294u32 reg_src_sel;295296/* Default register vals */297int pci_irqmask;298u32 dma_ctl_val;299u32 ts_int_msk_val;300u32 gen_ctrl_val;301u32 ts_clk_en_val;302u32 src_sel_val;303u32 vld_misc_val;304u32 hw_sop_ctrl_val;305306/* Allow a single tsport to have multiple frontends */307u32 num_frontends;308void (*gate_ctrl)(struct cx23885_tsport *port, int open);309void *port_priv;310};311312struct cx23885_kernel_ir {313struct cx23885_dev *cx;314char *name;315char *phys;316317struct rc_dev *rc;318};319320struct cx23885_dev {321atomic_t refcount;322struct v4l2_device v4l2_dev;323324/* pci stuff */325struct pci_dev *pci;326unsigned char pci_rev, pci_lat;327int pci_bus, pci_slot;328u32 __iomem *lmmio;329u8 __iomem *bmmio;330int pci_irqmask;331spinlock_t pci_irqmask_lock; /* protects mask reg too */332int hwrevision;333334/* This valud is board specific and is used to configure the335* AV core so we see nice clean and stable video and audio. */336u32 clk_freq;337338/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */339struct cx23885_i2c i2c_bus[3];340341int nr;342struct mutex lock;343struct mutex gpio_lock;344345/* board details */346unsigned int board;347char name[32];348349struct cx23885_tsport ts1, ts2;350351/* sram configuration */352struct sram_channel *sram_channels;353354enum {355CX23885_BRIDGE_UNDEFINED = 0,356CX23885_BRIDGE_885 = 885,357CX23885_BRIDGE_887 = 887,358CX23885_BRIDGE_888 = 888,359} bridge;360361/* Analog video */362u32 resources;363unsigned int input;364u32 tvaudio;365v4l2_std_id tvnorm;366unsigned int tuner_type;367unsigned char tuner_addr;368unsigned int tuner_bus;369unsigned int radio_type;370unsigned char radio_addr;371unsigned int has_radio;372struct v4l2_subdev *sd_cx25840;373struct work_struct cx25840_work;374375/* Infrared */376struct v4l2_subdev *sd_ir;377struct work_struct ir_rx_work;378unsigned long ir_rx_notifications;379struct work_struct ir_tx_work;380unsigned long ir_tx_notifications;381382struct cx23885_kernel_ir *kernel_ir;383atomic_t ir_input_stopping;384385/* V4l */386u32 freq;387struct video_device *video_dev;388struct video_device *vbi_dev;389struct video_device *radio_dev;390391struct cx23885_dmaqueue vidq;392struct cx23885_dmaqueue vbiq;393spinlock_t slock;394395/* MPEG Encoder ONLY settings */396u32 cx23417_mailbox;397struct cx2341x_mpeg_params mpeg_params;398struct video_device *v4l_device;399atomic_t v4l_reader_count;400struct cx23885_tvnorm encodernorm;401402};403404static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)405{406return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);407}408409#define call_all(dev, o, f, args...) \410v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)411412#define CX23885_HW_888_IR (1 << 0)413#define CX23885_HW_AV_CORE (1 << 1)414415#define call_hw(dev, grpid, o, f, args...) \416v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)417418extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);419420#define SRAM_CH01 0 /* Video A */421#define SRAM_CH02 1 /* VBI A */422#define SRAM_CH03 2 /* Video B */423#define SRAM_CH04 3 /* Transport via B */424#define SRAM_CH05 4 /* VBI B */425#define SRAM_CH06 5 /* Video C */426#define SRAM_CH07 6 /* Transport via C */427#define SRAM_CH08 7 /* Audio Internal A */428#define SRAM_CH09 8 /* Audio Internal B */429#define SRAM_CH10 9 /* Audio External */430#define SRAM_CH11 10 /* COMB_3D_N */431#define SRAM_CH12 11 /* Comb 3D N1 */432#define SRAM_CH13 12 /* Comb 3D N2 */433#define SRAM_CH14 13 /* MOE Vid */434#define SRAM_CH15 14 /* MOE RSLT */435436struct sram_channel {437char *name;438u32 cmds_start;439u32 ctrl_start;440u32 cdt;441u32 fifo_start;442u32 fifo_size;443u32 ptr1_reg;444u32 ptr2_reg;445u32 cnt1_reg;446u32 cnt2_reg;447u32 jumponly;448};449450/* ----------------------------------------------------------- */451452#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))453#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))454455#define cx_andor(reg, mask, value) \456writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\457((value) & (mask)), dev->lmmio+((reg)>>2))458459#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))460#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)461462/* ----------------------------------------------------------- */463/* cx23885-core.c */464465extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,466struct sram_channel *ch,467unsigned int bpl, u32 risc);468469extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,470struct sram_channel *ch);471472extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,473u32 reg, u32 mask, u32 value);474475extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,476struct scatterlist *sglist,477unsigned int top_offset, unsigned int bottom_offset,478unsigned int bpl, unsigned int padding, unsigned int lines);479480void cx23885_cancel_buffers(struct cx23885_tsport *port);481482extern int cx23885_restart_queue(struct cx23885_tsport *port,483struct cx23885_dmaqueue *q);484485extern void cx23885_wakeup(struct cx23885_tsport *port,486struct cx23885_dmaqueue *q, u32 count);487488extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);489extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);490extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);491extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,492int asoutput);493494extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);495extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);496extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);497extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);498499/* ----------------------------------------------------------- */500/* cx23885-cards.c */501extern struct cx23885_board cx23885_boards[];502extern const unsigned int cx23885_bcount;503504extern struct cx23885_subid cx23885_subids[];505extern const unsigned int cx23885_idcount;506507extern int cx23885_tuner_callback(void *priv, int component,508int command, int arg);509extern void cx23885_card_list(struct cx23885_dev *dev);510extern int cx23885_ir_init(struct cx23885_dev *dev);511extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);512extern void cx23885_ir_fini(struct cx23885_dev *dev);513extern void cx23885_gpio_setup(struct cx23885_dev *dev);514extern void cx23885_card_setup(struct cx23885_dev *dev);515extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);516517extern int cx23885_dvb_register(struct cx23885_tsport *port);518extern int cx23885_dvb_unregister(struct cx23885_tsport *port);519520extern int cx23885_buf_prepare(struct videobuf_queue *q,521struct cx23885_tsport *port,522struct cx23885_buffer *buf,523enum v4l2_field field);524extern void cx23885_buf_queue(struct cx23885_tsport *port,525struct cx23885_buffer *buf);526extern void cx23885_free_buffer(struct videobuf_queue *q,527struct cx23885_buffer *buf);528529/* ----------------------------------------------------------- */530/* cx23885-video.c */531/* Video */532extern int cx23885_video_register(struct cx23885_dev *dev);533extern void cx23885_video_unregister(struct cx23885_dev *dev);534extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);535536/* ----------------------------------------------------------- */537/* cx23885-vbi.c */538extern int cx23885_vbi_fmt(struct file *file, void *priv,539struct v4l2_format *f);540extern void cx23885_vbi_timeout(unsigned long data);541extern struct videobuf_queue_ops cx23885_vbi_qops;542543/* cx23885-i2c.c */544extern int cx23885_i2c_register(struct cx23885_i2c *bus);545extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);546extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);547548/* ----------------------------------------------------------- */549/* cx23885-417.c */550extern int cx23885_417_register(struct cx23885_dev *dev);551extern void cx23885_417_unregister(struct cx23885_dev *dev);552extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);553extern void cx23885_417_check_encoder(struct cx23885_dev *dev);554extern void cx23885_mc417_init(struct cx23885_dev *dev);555extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);556extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);557extern int mc417_register_read(struct cx23885_dev *dev,558u16 address, u32 *value);559extern int mc417_register_write(struct cx23885_dev *dev,560u16 address, u32 value);561extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);562extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);563extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);564565566/* ----------------------------------------------------------- */567/* tv norms */568569static inline unsigned int norm_maxw(v4l2_std_id norm)570{571return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;572}573574static inline unsigned int norm_maxh(v4l2_std_id norm)575{576return (norm & V4L2_STD_625_50) ? 576 : 480;577}578579static inline unsigned int norm_swidth(v4l2_std_id norm)580{581return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;582}583584585