/*1* Copyright (c) 2007 Dave Airlie <[email protected]>2* Copyright (c) 2007 Jakob Bornecrantz <[email protected]>3* Copyright (c) 2008 Red Hat Inc.4* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA5* Copyright (c) 2007-2008 Intel Corporation6*7* Permission is hereby granted, free of charge, to any person obtaining a8* copy of this software and associated documentation files (the "Software"),9* to deal in the Software without restriction, including without limitation10* the rights to use, copy, modify, merge, publish, distribute, sublicense,11* and/or sell copies of the Software, and to permit persons to whom the12* Software is furnished to do so, subject to the following conditions:13*14* The above copyright notice and this permission notice shall be included in15* all copies or substantial portions of the Software.16*17* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR18* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,19* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE20* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER21* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING22* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS23* IN THE SOFTWARE.24*/2526#ifndef _DRM_MODE_H27#define _DRM_MODE_H2829#define DRM_DISPLAY_INFO_LEN 3230#define DRM_CONNECTOR_NAME_LEN 3231#define DRM_DISPLAY_MODE_LEN 3232#define DRM_PROP_NAME_LEN 323334#define DRM_MODE_TYPE_BUILTIN (1<<0)35#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)36#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)37#define DRM_MODE_TYPE_PREFERRED (1<<3)38#define DRM_MODE_TYPE_DEFAULT (1<<4)39#define DRM_MODE_TYPE_USERDEF (1<<5)40#define DRM_MODE_TYPE_DRIVER (1<<6)4142/* Video mode flags */43/* bit compatible with the xorg definitions. */44#define DRM_MODE_FLAG_PHSYNC (1<<0)45#define DRM_MODE_FLAG_NHSYNC (1<<1)46#define DRM_MODE_FLAG_PVSYNC (1<<2)47#define DRM_MODE_FLAG_NVSYNC (1<<3)48#define DRM_MODE_FLAG_INTERLACE (1<<4)49#define DRM_MODE_FLAG_DBLSCAN (1<<5)50#define DRM_MODE_FLAG_CSYNC (1<<6)51#define DRM_MODE_FLAG_PCSYNC (1<<7)52#define DRM_MODE_FLAG_NCSYNC (1<<8)53#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */54#define DRM_MODE_FLAG_BCAST (1<<10)55#define DRM_MODE_FLAG_PIXMUX (1<<11)56#define DRM_MODE_FLAG_DBLCLK (1<<12)57#define DRM_MODE_FLAG_CLKDIV2 (1<<13)5859/* DPMS flags */60/* bit compatible with the xorg definitions. */61#define DRM_MODE_DPMS_ON 062#define DRM_MODE_DPMS_STANDBY 163#define DRM_MODE_DPMS_SUSPEND 264#define DRM_MODE_DPMS_OFF 36566/* Scaling mode options */67#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or68software can still scale) */69#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */70#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */71#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */7273/* Dithering mode options */74#define DRM_MODE_DITHERING_OFF 075#define DRM_MODE_DITHERING_ON 176#define DRM_MODE_DITHERING_AUTO 27778/* Dirty info options */79#define DRM_MODE_DIRTY_OFF 080#define DRM_MODE_DIRTY_ON 181#define DRM_MODE_DIRTY_ANNOTATE 28283struct drm_mode_modeinfo {84__u32 clock;85__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;86__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;8788__u32 vrefresh;8990__u32 flags;91__u32 type;92char name[DRM_DISPLAY_MODE_LEN];93};9495struct drm_mode_card_res {96__u64 fb_id_ptr;97__u64 crtc_id_ptr;98__u64 connector_id_ptr;99__u64 encoder_id_ptr;100__u32 count_fbs;101__u32 count_crtcs;102__u32 count_connectors;103__u32 count_encoders;104__u32 min_width, max_width;105__u32 min_height, max_height;106};107108struct drm_mode_crtc {109__u64 set_connectors_ptr;110__u32 count_connectors;111112__u32 crtc_id; /**< Id */113__u32 fb_id; /**< Id of framebuffer */114115__u32 x, y; /**< Position on the frameuffer */116117__u32 gamma_size;118__u32 mode_valid;119struct drm_mode_modeinfo mode;120};121122#define DRM_MODE_ENCODER_NONE 0123#define DRM_MODE_ENCODER_DAC 1124#define DRM_MODE_ENCODER_TMDS 2125#define DRM_MODE_ENCODER_LVDS 3126#define DRM_MODE_ENCODER_TVDAC 4127128struct drm_mode_get_encoder {129__u32 encoder_id;130__u32 encoder_type;131132__u32 crtc_id; /**< Id of crtc */133134__u32 possible_crtcs;135__u32 possible_clones;136};137138/* This is for connectors with multiple signal types. */139/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */140#define DRM_MODE_SUBCONNECTOR_Automatic 0141#define DRM_MODE_SUBCONNECTOR_Unknown 0142#define DRM_MODE_SUBCONNECTOR_DVID 3143#define DRM_MODE_SUBCONNECTOR_DVIA 4144#define DRM_MODE_SUBCONNECTOR_Composite 5145#define DRM_MODE_SUBCONNECTOR_SVIDEO 6146#define DRM_MODE_SUBCONNECTOR_Component 8147#define DRM_MODE_SUBCONNECTOR_SCART 9148149#define DRM_MODE_CONNECTOR_Unknown 0150#define DRM_MODE_CONNECTOR_VGA 1151#define DRM_MODE_CONNECTOR_DVII 2152#define DRM_MODE_CONNECTOR_DVID 3153#define DRM_MODE_CONNECTOR_DVIA 4154#define DRM_MODE_CONNECTOR_Composite 5155#define DRM_MODE_CONNECTOR_SVIDEO 6156#define DRM_MODE_CONNECTOR_LVDS 7157#define DRM_MODE_CONNECTOR_Component 8158#define DRM_MODE_CONNECTOR_9PinDIN 9159#define DRM_MODE_CONNECTOR_DisplayPort 10160#define DRM_MODE_CONNECTOR_HDMIA 11161#define DRM_MODE_CONNECTOR_HDMIB 12162#define DRM_MODE_CONNECTOR_TV 13163#define DRM_MODE_CONNECTOR_eDP 14164165struct drm_mode_get_connector {166167__u64 encoders_ptr;168__u64 modes_ptr;169__u64 props_ptr;170__u64 prop_values_ptr;171172__u32 count_modes;173__u32 count_props;174__u32 count_encoders;175176__u32 encoder_id; /**< Current Encoder */177__u32 connector_id; /**< Id */178__u32 connector_type;179__u32 connector_type_id;180181__u32 connection;182__u32 mm_width, mm_height; /**< HxW in millimeters */183__u32 subpixel;184};185186#define DRM_MODE_PROP_PENDING (1<<0)187#define DRM_MODE_PROP_RANGE (1<<1)188#define DRM_MODE_PROP_IMMUTABLE (1<<2)189#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */190#define DRM_MODE_PROP_BLOB (1<<4)191192struct drm_mode_property_enum {193__u64 value;194char name[DRM_PROP_NAME_LEN];195};196197struct drm_mode_get_property {198__u64 values_ptr; /* values and blob lengths */199__u64 enum_blob_ptr; /* enum and blob id ptrs */200201__u32 prop_id;202__u32 flags;203char name[DRM_PROP_NAME_LEN];204205__u32 count_values;206__u32 count_enum_blobs;207};208209struct drm_mode_connector_set_property {210__u64 value;211__u32 prop_id;212__u32 connector_id;213};214215struct drm_mode_get_blob {216__u32 blob_id;217__u32 length;218__u64 data;219};220221struct drm_mode_fb_cmd {222__u32 fb_id;223__u32 width, height;224__u32 pitch;225__u32 bpp;226__u32 depth;227/* driver specific handle */228__u32 handle;229};230231#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01232#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02233#define DRM_MODE_FB_DIRTY_FLAGS 0x03234235/*236* Mark a region of a framebuffer as dirty.237*238* Some hardware does not automatically update display contents239* as a hardware or software draw to a framebuffer. This ioctl240* allows userspace to tell the kernel and the hardware what241* regions of the framebuffer have changed.242*243* The kernel or hardware is free to update more then just the244* region specified by the clip rects. The kernel or hardware245* may also delay and/or coalesce several calls to dirty into a246* single update.247*248* Userspace may annotate the updates, the annotates are a249* promise made by the caller that the change is either a copy250* of pixels or a fill of a single color in the region specified.251*252* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then253* the number of updated regions are half of num_clips given,254* where the clip rects are paired in src and dst. The width and255* height of each one of the pairs must match.256*257* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller258* promises that the region specified of the clip rects is filled259* completely with a single color as given in the color argument.260*/261262struct drm_mode_fb_dirty_cmd {263__u32 fb_id;264__u32 flags;265__u32 color;266__u32 num_clips;267__u64 clips_ptr;268};269270struct drm_mode_mode_cmd {271__u32 connector_id;272struct drm_mode_modeinfo mode;273};274275#define DRM_MODE_CURSOR_BO (1<<0)276#define DRM_MODE_CURSOR_MOVE (1<<1)277278/*279* depending on the value in flags different members are used.280*281* CURSOR_BO uses282* crtc283* width284* height285* handle - if 0 turns the cursor of286*287* CURSOR_MOVE uses288* crtc289* x290* y291*/292struct drm_mode_cursor {293__u32 flags;294__u32 crtc_id;295__s32 x;296__s32 y;297__u32 width;298__u32 height;299/* driver specific handle */300__u32 handle;301};302303struct drm_mode_crtc_lut {304__u32 crtc_id;305__u32 gamma_size;306307/* pointers to arrays */308__u64 red;309__u64 green;310__u64 blue;311};312313#define DRM_MODE_PAGE_FLIP_EVENT 0x01314#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT315316/*317* Request a page flip on the specified crtc.318*319* This ioctl will ask KMS to schedule a page flip for the specified320* crtc. Once any pending rendering targeting the specified fb (as of321* ioctl time) has completed, the crtc will be reprogrammed to display322* that fb after the next vertical refresh. The ioctl returns323* immediately, but subsequent rendering to the current fb will block324* in the execbuffer ioctl until the page flip happens. If a page325* flip is already pending as the ioctl is called, EBUSY will be326* returned.327*328* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will329* request that drm sends back a vblank event (see drm.h: struct330* drm_event_vblank) when the page flip is done. The user_data field331* passed in with this ioctl will be returned as the user_data field332* in the vblank event struct.333*334* The reserved field must be zero until we figure out something335* clever to use it for.336*/337338struct drm_mode_crtc_page_flip {339__u32 crtc_id;340__u32 fb_id;341__u32 flags;342__u32 reserved;343__u64 user_data;344};345346/* create a dumb scanout buffer */347struct drm_mode_create_dumb {348uint32_t height;349uint32_t width;350uint32_t bpp;351uint32_t flags;352/* handle, pitch, size will be returned */353uint32_t handle;354uint32_t pitch;355uint64_t size;356};357358/* set up for mmap of a dumb scanout buffer */359struct drm_mode_map_dumb {360/** Handle for the object being mapped. */361__u32 handle;362__u32 pad;363/**364* Fake offset to use for subsequent mmap call365*366* This is a fixed-size type for 32/64 compatibility.367*/368__u64 offset;369};370371struct drm_mode_destroy_dumb {372uint32_t handle;373};374375#endif376377378