/**************************************************************************1*2* Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA3* All Rights Reserved.4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the7* "Software"), to deal in the Software without restriction, including8* without limitation the rights to use, copy, modify, merge, publish,9* distribute, sub license, and/or sell copies of the Software, and to10* permit persons to whom the Software is furnished to do so, subject to11* the following conditions:12*13* The above copyright notice and this permission notice (including the14* next paragraph) shall be included in all copies or substantial portions15* of the Software.16*17* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR18* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,19* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL20* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,21* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR22* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE23* USE OR OTHER DEALINGS IN THE SOFTWARE.24*25**************************************************************************/26/*27* Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>28*/2930#ifndef _TTM_PLACEMENT_H_31#define _TTM_PLACEMENT_H_32/*33* Memory regions for data placement.34*/3536#define TTM_PL_SYSTEM 037#define TTM_PL_TT 138#define TTM_PL_VRAM 239#define TTM_PL_PRIV0 340#define TTM_PL_PRIV1 441#define TTM_PL_PRIV2 542#define TTM_PL_PRIV3 643#define TTM_PL_PRIV4 744#define TTM_PL_PRIV5 845#define TTM_PL_SWAPPED 154647#define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM)48#define TTM_PL_FLAG_TT (1 << TTM_PL_TT)49#define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM)50#define TTM_PL_FLAG_PRIV0 (1 << TTM_PL_PRIV0)51#define TTM_PL_FLAG_PRIV1 (1 << TTM_PL_PRIV1)52#define TTM_PL_FLAG_PRIV2 (1 << TTM_PL_PRIV2)53#define TTM_PL_FLAG_PRIV3 (1 << TTM_PL_PRIV3)54#define TTM_PL_FLAG_PRIV4 (1 << TTM_PL_PRIV4)55#define TTM_PL_FLAG_PRIV5 (1 << TTM_PL_PRIV5)56#define TTM_PL_FLAG_SWAPPED (1 << TTM_PL_SWAPPED)57#define TTM_PL_MASK_MEM 0x0000FFFF5859/*60* Other flags that affects data placement.61* TTM_PL_FLAG_CACHED indicates cache-coherent mappings62* if available.63* TTM_PL_FLAG_SHARED means that another application may64* reference the buffer.65* TTM_PL_FLAG_NO_EVICT means that the buffer may never66* be evicted to make room for other buffers.67*/6869#define TTM_PL_FLAG_CACHED (1 << 16)70#define TTM_PL_FLAG_UNCACHED (1 << 17)71#define TTM_PL_FLAG_WC (1 << 18)72#define TTM_PL_FLAG_SHARED (1 << 20)73#define TTM_PL_FLAG_NO_EVICT (1 << 21)7475#define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \76TTM_PL_FLAG_UNCACHED | \77TTM_PL_FLAG_WC)7879#define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING)8081/*82* Access flags to be used for CPU- and GPU- mappings.83* The idea is that the TTM synchronization mechanism will84* allow concurrent READ access and exclusive write access.85* Currently GPU- and CPU accesses are exclusive.86*/8788#define TTM_ACCESS_READ (1 << 0)89#define TTM_ACCESS_WRITE (1 << 1)9091#endif929394