#ifndef __SOUND_EMU10K1_H1#define __SOUND_EMU10K1_H23#include <linux/types.h>45/*6* Copyright (c) by Jaroslav Kysela <[email protected]>,7* Creative Labs, Inc.8* Definitions for EMU10K1 (SB Live!) chips9*10*11* This program is free software; you can redistribute it and/or modify12* it under the terms of the GNU General Public License as published by13* the Free Software Foundation; either version 2 of the License, or14* (at your option) any later version.15*16* This program is distributed in the hope that it will be useful,17* but WITHOUT ANY WARRANTY; without even the implied warranty of18* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the19* GNU General Public License for more details.20*21* You should have received a copy of the GNU General Public License22* along with this program; if not, write to the Free Software23* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA24*25*/2627#ifdef __KERNEL__2829#include <sound/pcm.h>30#include <sound/rawmidi.h>31#include <sound/hwdep.h>32#include <sound/ac97_codec.h>33#include <sound/util_mem.h>34#include <sound/pcm-indirect.h>35#include <sound/timer.h>36#include <linux/interrupt.h>37#include <linux/mutex.h>3839#include <asm/io.h>4041/* ------------------- DEFINES -------------------- */4243#define EMUPAGESIZE 409644#define MAXREQVOICES 845#define MAXPAGES 819246#define RESERVED 047#define NUM_MIDI 1648#define NUM_G 64 /* use all channels */49#define NUM_FXSENDS 450#define NUM_EFX_PLAYBACK 165152/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */53#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */54#define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */55/* See ALSA bug #1276 - rlrevell */5657#define TMEMSIZE 256*102458#define TMEMSIZEREG 45960#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))6162// Audigy specify registers are prefixed with 'A_'6364/************************************************************************************************/65/* PCI function 0 registers, address = <val> + PCIBASE0 */66/************************************************************************************************/6768#define PTR 0x00 /* Indexed register set pointer register */69/* NOTE: The CHANNELNUM and ADDRESS words can */70/* be modified independently of each other. */71#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */72/* channel number of the register to be */73/* accessed. For non per-channel registers the */74/* value should be set to zero. */75#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */76#define A_PTR_ADDRESS_MASK 0x0fff00007778#define DATA 0x04 /* Indexed register set data register */7980#define IPR 0x08 /* Global interrupt pending register */81/* Clear pending interrupts by writing a 1 to */82/* the relevant bits and zero to the other bits */83#define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes84to interrupt */85#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure86which INTE bits enable it) */8788/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */89#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */90#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */9192#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */93#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */9495#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */96#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */97#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */98#define IPR_PCIERROR 0x00200000 /* PCI bus error */99#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */100#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */101#define IPR_MUTE 0x00040000 /* Mute button pressed */102#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */103#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */104#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */105#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */106#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */107#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */108#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */109#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */110#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */111#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */112#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */113#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */114#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */115/* highest set channel in CLIPL, CLIPH, HLIPL, */116/* or HLIPH. When IP is written with CL set, */117/* the bit in H/CLIPL or H/CLIPH corresponding */118/* to the CIN value written will be cleared. */119120#define INTE 0x0c /* Interrupt enable register */121#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */122#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */123#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */124#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */125#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */126#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */127#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */128#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */129#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */130#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */131#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */132#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */133#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */134#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */135#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */136#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */137#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */138#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */139140#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */141/* NOTE: There is no reason to use this under */142/* Linux, and it will cause odd hardware */143/* behavior and possibly random segfaults and */144/* lockups if enabled. */145146/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */147#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */148#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */149150151#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */152/* NOTE: This bit must always be enabled */153#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */154#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */155#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */156#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */157#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */158#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */159#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */160#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */161#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */162#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */163#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */164#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */165#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */166167#define WC 0x10 /* Wall Clock register */168#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */169#define WC_SAMPLECOUNTER 0x14060010170#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */171/* NOTE: Each channel takes 1/64th of a sample */172/* period to be serviced. */173174#define HCFG 0x14 /* Hardware config register */175/* NOTE: There is no reason to use the legacy */176/* SoundBlaster emulation stuff described below */177/* under Linux, and all kinds of weird hardware */178/* behavior can result if you try. Don't. */179#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */180#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */181#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */182#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */183#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */184#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */185#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */186#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */187#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */188#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */189#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */190#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */191/* NOTE: The rest of the bits in this register */192/* _are_ relevant under Linux. */193#define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */194#define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */195#define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */196#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */197198/* Specific to Alice2, CA0102 */199#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */200#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */201#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */202/* will automatically mute their output when */203/* they are not rate-locked to the external */204/* async audio source */205#define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */206/* will automatically mute their output when */207/* the SPDIF V-bit indicates invalid audio */208#define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */209#define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */210/* 0x00000800 not used on Alice2 */211#define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */212/* phase track the previous input. */213/* I2S0 can phase track the last S/PDIF input */214#define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */215/* conversion for the corresponding */216/* I2S format input */217/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */218219220221/* Older chips */222#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */223#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */224#define HCFG_GPINPUT0 0x00004000 /* External pin112 */225#define HCFG_GPINPUT1 0x00002000 /* External pin110 */226#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */227#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */228#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */229#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */230#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */231#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */232/* 1 = Force all 3 async digital inputs to use */233/* the same async sample rate tracker (ZVIDEO) */234#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */235#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */236#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */237#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */238#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */239/* will automatically mute their output when */240/* they are not rate-locked to the external */241/* async audio source */242#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */243/* NOTE: This should generally never be used. */244#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */245/* NOTE: This should generally never be used. */246#define HCFG_LOCKTANKCACHE 0x01020014247#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */248/* NOTE: This is a 'cheap' way to implement a */249/* master mute function on the mute button, and */250/* in general should not be used unless a more */251/* sophisticated master mute function has not */252/* been written. */253#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */254/* Should be set to 1 when the EMU10K1 is */255/* completely initialized. */256257//For Audigy, MPU port move to 0x70-0x74 ptr register258259#define MUDATA 0x18 /* MPU401 data register (8 bits) */260261#define MUCMD 0x19 /* MPU401 command register (8 bits) */262#define MUCMD_RESET 0xff /* RESET command */263#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */264/* NOTE: All other commands are ignored */265266#define MUSTAT MUCMD /* MPU401 status register (8 bits) */267#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */268#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */269270#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */271#define A_GPINPUT_MASK 0xff00272#define A_GPOUTPUT_MASK 0x00ff273274// Audigy output/GPIO stuff taken from the kX drivers275#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */276#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */277#define A_IOCFG_ENABLE_DIGITAL 0x0004278#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080279#define A_IOCFG_UNKNOWN_20 0x0020280#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */281#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */282#define A_IOCFG_GPOUT2 0x0001 /* IR */283#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */284/* + digital for generic 10k2 */285#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */286#define A_IOCFG_FRONT_JACK 0x4000287#define A_IOCFG_REAR_JACK 0x8000288#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */289290/* outputs:291* for audigy2 platinum: 0xa00292* for a2 platinum ex: 0x1c00293* for a1 platinum: 0x0294*/295296#define TIMER 0x1a /* Timer terminal count register */297/* NOTE: After the rate is changed, a maximum */298/* of 1024 sample periods should be allowed */299/* before the new rate is guaranteed accurate. */300#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */301/* 0 == 1024 periods, [1..4] are not useful */302#define TIMER_RATE 0x0a00001a303304#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */305306#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */307#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */308#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */309310/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */311#define PTR2 0x20 /* Indexed register set pointer register */312#define DATA2 0x24 /* Indexed register set data register */313#define IPR2 0x28 /* P16V interrupt pending register */314#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */315#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */316#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */317#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */318/* 0x00000100 Playback. Only in once per period.319* 0x00110000 Capture. Int on half buffer.320*/321#define INTE2 0x2c /* P16V Interrupt enable register. */322#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */323#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */324#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */325#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */326#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */327#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */328#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */329#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */330#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */331#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */332#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */333/* 0x00000000 2-channel output. */334/* 0x00000200 8-channel output. */335/* 0x00000004 pauses stream/irq fail. */336/* Rest of bits no nothing to sound output */337/* bit 0: Enable P16V audio.338* bit 1: Lock P16V record memory cache.339* bit 2: Lock P16V playback memory cache.340* bit 3: Dummy record insert zero samples.341* bit 8: Record 8-channel in phase.342* bit 9: Playback 8-channel in phase.343* bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.344* bit 13: Playback mixer enable.345* bit 14: Route SRC48 mixer output to fx engine.346* bit 15: Enable IEEE 1394 chip.347*/348#define IPR3 0x38 /* Cdif interrupt pending register */349#define INTE3 0x3c /* Cdif interrupt enable register. */350/************************************************************************************************/351/* PCI function 1 registers, address = <val> + PCIBASE1 */352/************************************************************************************************/353354#define JOYSTICK1 0x00 /* Analog joystick port register */355#define JOYSTICK2 0x01 /* Analog joystick port register */356#define JOYSTICK3 0x02 /* Analog joystick port register */357#define JOYSTICK4 0x03 /* Analog joystick port register */358#define JOYSTICK5 0x04 /* Analog joystick port register */359#define JOYSTICK6 0x05 /* Analog joystick port register */360#define JOYSTICK7 0x06 /* Analog joystick port register */361#define JOYSTICK8 0x07 /* Analog joystick port register */362363/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */364/* When reading, use these bitfields: */365#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */366#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */367368369/********************************************************************************************************/370/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */371/********************************************************************************************************/372373#define CPF 0x00 /* Current pitch and fraction register */374#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */375#define CPF_CURRENTPITCH 0x10100000376#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */377#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */378#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */379380#define PTRX 0x01 /* Pitch target and send A/B amounts register */381#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */382#define PTRX_PITCHTARGET 0x10100001383#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */384#define PTRX_FXSENDAMOUNT_A 0x08080001385#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */386#define PTRX_FXSENDAMOUNT_B 0x08000001387388#define CVCF 0x02 /* Current volume and filter cutoff register */389#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */390#define CVCF_CURRENTVOL 0x10100002391#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */392#define CVCF_CURRENTFILTER 0x10000002393394#define VTFT 0x03 /* Volume target and filter cutoff target register */395#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */396#define VTFT_VOLUMETARGET 0x10100003397#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */398#define VTFT_FILTERTARGET 0x10000003399400#define Z1 0x05 /* Filter delay memory 1 register */401402#define Z2 0x04 /* Filter delay memory 2 register */403404#define PSST 0x06 /* Send C amount and loop start address register */405#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */406407#define PSST_FXSENDAMOUNT_C 0x08180006408409#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */410#define PSST_LOOPSTARTADDR 0x18000006411412#define DSL 0x07 /* Send D amount and loop start address register */413#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */414415#define DSL_FXSENDAMOUNT_D 0x08180007416417#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */418#define DSL_LOOPENDADDR 0x18000007419420#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */421#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */422#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */423/* 1 == full band, 7 == lowpass */424/* ROM 0 is used when pitch shifting downward or less */425/* then 3 semitones upward. Increasingly higher ROM */426/* numbers are used, typically in steps of 3 semitones, */427/* as upward pitch shifting is performed. */428#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */429#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */430#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */431#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */432#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */433#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */434#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */435#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */436#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */437#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */438#define CCCA_CURRADDR 0x18000008439440/* undefine CCR to avoid conflict with the definition for SH */441#undef CCR442#define CCR 0x09 /* Cache control register */443#define CCR_CACHEINVALIDSIZE 0x07190009444#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */445#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */446#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */447#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */448#define CCR_READADDRESS 0x06100009449#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */450#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */451/* NOTE: This is valid only if CACHELOOPFLAG is set */452#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */453#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */454455#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */456/* NOTE: This register is normally not used */457#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */458459#define FXRT 0x0b /* Effects send routing register */460/* NOTE: It is illegal to assign the same routing to */461/* two effects sends. */462#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */463#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */464#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */465#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */466467#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */468#define MAPA 0x0c /* Cache map A */469470#define MAPB 0x0d /* Cache map B */471472#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */473#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */474475/* 0x0e, 0x0f: Not used */476477#define ENVVOL 0x10 /* Volume envelope register */478#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */479/* 0x8000-n == 666*n usec delay */480481#define ATKHLDV 0x11 /* Volume envelope hold and attack register */482#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */483#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */484#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */485/* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */486487#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */488#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */489#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */490#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */491/* this channel and from writing to pitch, filter and */492/* volume targets. */493#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */494/* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */495496#define LFOVAL1 0x13 /* Modulation LFO value */497#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */498/* 0x8000-n == 666*n usec delay */499500#define ENVVAL 0x14 /* Modulation envelope register */501#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */502/* 0x8000-n == 666*n usec delay */503504#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */505#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */506#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */507#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */508/* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */509510#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */511#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */512#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */513#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */514/* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */515516#define LFOVAL2 0x17 /* Vibrato LFO register */517#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */518/* 0x8000-n == 666*n usec delay */519520#define IP 0x18 /* Initial pitch register */521#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */522/* 4 bits of octave, 12 bits of fractional octave */523#define IP_UNITY 0x0000e000 /* Unity pitch shift */524525#define IFATN 0x19 /* Initial filter cutoff and attenuation register */526#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */527/* 6 most significant bits are semitones */528/* 2 least significant bits are fractions */529#define IFATN_FILTERCUTOFF 0x08080019530#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */531#define IFATN_ATTENUATION 0x08000019532533534#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */535#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */536/* Signed 2's complement, +/- one octave peak extremes */537#define PEFE_PITCHAMOUNT 0x0808001a538#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */539/* Signed 2's complement, +/- six octaves peak extremes */540#define PEFE_FILTERAMOUNT 0x0800001a541#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */542#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */543/* Signed 2's complement, +/- one octave extremes */544#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */545/* Signed 2's complement, +/- three octave extremes */546547548#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */549#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */550/* Signed 2's complement, with +/- 12dB extremes */551552#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */553/* ??Hz steps, maximum of ?? Hz. */554#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */555#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */556/* Signed 2's complement, +/- one octave extremes */557#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */558/* 0.039Hz steps, maximum of 9.85 Hz. */559560#define TEMPENV 0x1e /* Tempory envelope register */561#define TEMPENV_MASK 0x0000ffff /* 16-bit value */562/* NOTE: All channels contain internal variables; do */563/* not write to these locations. */564565/* 0x1f: not used */566567#define CD0 0x20 /* Cache data 0 register */568#define CD1 0x21 /* Cache data 1 register */569#define CD2 0x22 /* Cache data 2 register */570#define CD3 0x23 /* Cache data 3 register */571#define CD4 0x24 /* Cache data 4 register */572#define CD5 0x25 /* Cache data 5 register */573#define CD6 0x26 /* Cache data 6 register */574#define CD7 0x27 /* Cache data 7 register */575#define CD8 0x28 /* Cache data 8 register */576#define CD9 0x29 /* Cache data 9 register */577#define CDA 0x2a /* Cache data A register */578#define CDB 0x2b /* Cache data B register */579#define CDC 0x2c /* Cache data C register */580#define CDD 0x2d /* Cache data D register */581#define CDE 0x2e /* Cache data E register */582#define CDF 0x2f /* Cache data F register */583584/* 0x30-3f seem to be the same as 0x20-2f */585586#define PTB 0x40 /* Page table base register */587#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */588589#define TCB 0x41 /* Tank cache base register */590#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */591592#define ADCCR 0x42 /* ADC sample rate/stereo control register */593#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */594#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */595/* NOTE: To guarantee phase coherency, both channels */596/* must be disabled prior to enabling both channels. */597#define A_ADCCR_RCHANENABLE 0x00000020598#define A_ADCCR_LCHANENABLE 0x00000010599600#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */601#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */602#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */603#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */604#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */605#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */606#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */607#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */608#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */609#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */610#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */611#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */612#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */613614#define FXWC 0x43 /* FX output write channels register */615/* When set, each bit enables the writing of the */616/* corresponding FX output channel (internal registers */617/* 0x20-0x3f) to host memory. This mode of recording */618/* is 16bit, 48KHz only. All 32 channels can be enabled */619/* simultaneously. */620621#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */622#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */623#define FXWC_DEFAULTROUTE_A (1<<12)624#define FXWC_DEFAULTROUTE_D (1<<13)625#define FXWC_ADCLEFT (1<<18)626#define FXWC_CDROMSPDIFLEFT (1<<18)627#define FXWC_ADCRIGHT (1<<19)628#define FXWC_CDROMSPDIFRIGHT (1<<19)629#define FXWC_MIC (1<<20)630#define FXWC_ZOOMLEFT (1<<20)631#define FXWC_ZOOMRIGHT (1<<21)632#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */633#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */634635#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */636637#define TCBS 0x44 /* Tank cache buffer size register */638#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */639#define TCBS_BUFFSIZE_16K 0x00000000640#define TCBS_BUFFSIZE_32K 0x00000001641#define TCBS_BUFFSIZE_64K 0x00000002642#define TCBS_BUFFSIZE_128K 0x00000003643#define TCBS_BUFFSIZE_256K 0x00000004644#define TCBS_BUFFSIZE_512K 0x00000005645#define TCBS_BUFFSIZE_1024K 0x00000006646#define TCBS_BUFFSIZE_2048K 0x00000007647648#define MICBA 0x45 /* AC97 microphone buffer address register */649#define MICBA_MASK 0xfffff000 /* 20 bit base address */650651#define ADCBA 0x46 /* ADC buffer address register */652#define ADCBA_MASK 0xfffff000 /* 20 bit base address */653654#define FXBA 0x47 /* FX Buffer Address */655#define FXBA_MASK 0xfffff000 /* 20 bit base address */656657#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */658659#define MICBS 0x49 /* Microphone buffer size register */660661#define ADCBS 0x4a /* ADC buffer size register */662663#define FXBS 0x4b /* FX buffer size register */664665/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */666667/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */668#define ADCBS_BUFSIZE_NONE 0x00000000669#define ADCBS_BUFSIZE_384 0x00000001670#define ADCBS_BUFSIZE_448 0x00000002671#define ADCBS_BUFSIZE_512 0x00000003672#define ADCBS_BUFSIZE_640 0x00000004673#define ADCBS_BUFSIZE_768 0x00000005674#define ADCBS_BUFSIZE_896 0x00000006675#define ADCBS_BUFSIZE_1024 0x00000007676#define ADCBS_BUFSIZE_1280 0x00000008677#define ADCBS_BUFSIZE_1536 0x00000009678#define ADCBS_BUFSIZE_1792 0x0000000a679#define ADCBS_BUFSIZE_2048 0x0000000b680#define ADCBS_BUFSIZE_2560 0x0000000c681#define ADCBS_BUFSIZE_3072 0x0000000d682#define ADCBS_BUFSIZE_3584 0x0000000e683#define ADCBS_BUFSIZE_4096 0x0000000f684#define ADCBS_BUFSIZE_5120 0x00000010685#define ADCBS_BUFSIZE_6144 0x00000011686#define ADCBS_BUFSIZE_7168 0x00000012687#define ADCBS_BUFSIZE_8192 0x00000013688#define ADCBS_BUFSIZE_10240 0x00000014689#define ADCBS_BUFSIZE_12288 0x00000015690#define ADCBS_BUFSIZE_14366 0x00000016691#define ADCBS_BUFSIZE_16384 0x00000017692#define ADCBS_BUFSIZE_20480 0x00000018693#define ADCBS_BUFSIZE_24576 0x00000019694#define ADCBS_BUFSIZE_28672 0x0000001a695#define ADCBS_BUFSIZE_32768 0x0000001b696#define ADCBS_BUFSIZE_40960 0x0000001c697#define ADCBS_BUFSIZE_49152 0x0000001d698#define ADCBS_BUFSIZE_57344 0x0000001e699#define ADCBS_BUFSIZE_65536 0x0000001f700701/* Current Send B, A Amounts */702#define A_CSBA 0x4c703704/* Current Send D, C Amounts */705#define A_CSDC 0x4d706707/* Current Send F, E Amounts */708#define A_CSFE 0x4e709710/* Current Send H, G Amounts */711#define A_CSHG 0x4f712713714#define CDCS 0x50 /* CD-ROM digital channel status register */715716#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/717718#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */719720/* S/PDIF Input C Channel Status */721#define A_SPSC 0x52722723#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */724725#define A_DBG 0x53726#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */727#define A_DBG_ZC 0x40000000 /* zero tram counter */728#define A_DBG_STEP_ADDR 0x000003ff729#define A_DBG_SATURATION_OCCURED 0x20000000730#define A_DBG_SATURATION_ADDR 0x0ffc0000731732// NOTE: 0x54,55,56: 64-bit733#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */734735#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */736737#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */738739#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */740#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */741#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */742#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */743#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */744#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */745#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */746#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */747#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */748#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */749#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */750#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */751#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */752#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */753#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */754#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */755#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */756#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */757#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */758#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */759#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */760#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */761#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */762763/* 0x57: Not used */764765/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */766#define CLIEL 0x58 /* Channel loop interrupt enable low register */767768#define CLIEH 0x59 /* Channel loop interrupt enable high register */769770#define CLIPL 0x5a /* Channel loop interrupt pending low register */771772#define CLIPH 0x5b /* Channel loop interrupt pending high register */773774#define SOLEL 0x5c /* Stop on loop enable low register */775776#define SOLEH 0x5d /* Stop on loop enable high register */777778#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */779#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */780#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */781/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */782#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */783784#define AC97SLOT 0x5f /* additional AC97 slots enable bits */785#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */786#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */787#define AC97SLOT_CNTR 0x10 /* Center enable */788#define AC97SLOT_LFE 0x20 /* LFE enable */789790/* PCB Revision */791#define A_PCB 0x5f792793// NOTE: 0x60,61,62: 64-bit794#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */795796#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */797798#define ZVSRCS 0x62 /* ZVideo sample rate converter status */799/* NOTE: This one has no SPDIFLOCKED field */800/* Assumes sample lock */801802/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */803#define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */804#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */805#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */806#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */807808/* Note that these values can vary +/- by a small amount */809#define SRCS_SPDIFRATE_44 0x0003acd9810#define SRCS_SPDIFRATE_48 0x00040000811#define SRCS_SPDIFRATE_96 0x00080000812813#define MICIDX 0x63 /* Microphone recording buffer index register */814#define MICIDX_MASK 0x0000ffff /* 16-bit value */815#define MICIDX_IDX 0x10000063816817#define ADCIDX 0x64 /* ADC recording buffer index register */818#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */819#define ADCIDX_IDX 0x10000064820821#define A_ADCIDX 0x63822#define A_ADCIDX_IDX 0x10000063823824#define A_MICIDX 0x64825#define A_MICIDX_IDX 0x10000064826827#define FXIDX 0x65 /* FX recording buffer index register */828#define FXIDX_MASK 0x0000ffff /* 16-bit value */829#define FXIDX_IDX 0x10000065830831/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */832#define HLIEL 0x66 /* Channel half loop interrupt enable low register */833834#define HLIEH 0x67 /* Channel half loop interrupt enable high register */835836#define HLIPL 0x68 /* Channel half loop interrupt pending low register */837838#define HLIPH 0x69 /* Channel half loop interrupt pending high register */839840/* S/PDIF Host Record Index (bypasses SRC) */841#define A_SPRI 0x6a842/* S/PDIF Host Record Address */843#define A_SPRA 0x6b844/* S/PDIF Host Record Control */845#define A_SPRC 0x6c846/* Delayed Interrupt Counter & Enable */847#define A_DICE 0x6d848/* Tank Table Base */849#define A_TTB 0x6e850/* Tank Delay Offset */851#define A_TDOF 0x6f852853/* This is the MPU port on the card (via the game port) */854#define A_MUDATA1 0x70855#define A_MUCMD1 0x71856#define A_MUSTAT1 A_MUCMD1857858/* This is the MPU port on the Audigy Drive */859#define A_MUDATA2 0x72860#define A_MUCMD2 0x73861#define A_MUSTAT2 A_MUCMD2862863/* The next two are the Audigy equivalent of FXWC */864/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */865/* Each bit selects a channel for recording */866#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */867#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */868869/* Extended Hardware Control */870#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */871#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */872#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */873#define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */874#define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */875#define A_SPDIF_48000 0x00000000876#define A_SPDIF_192000 0x00000020877#define A_SPDIF_96000 0x00000040878#define A_SPDIF_44100 0x00000080879880#define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */881#define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */882#define A_I2S_CAPTURE_192000 0x00000200883#define A_I2S_CAPTURE_96000 0x00000400884#define A_I2S_CAPTURE_44100 0x00000800885886#define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */887#define A_PCM_48000 0x00000000888#define A_PCM_192000 0x00002000889#define A_PCM_96000 0x00004000890#define A_PCM_44100 0x00008000891892/* I2S0 Sample Rate Tracker Status */893#define A_SRT3 0x77894895/* I2S1 Sample Rate Tracker Status */896#define A_SRT4 0x78897898/* I2S2 Sample Rate Tracker Status */899#define A_SRT5 0x79900/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */901902/* Tank Table DMA Address */903#define A_TTDA 0x7a904/* Tank Table DMA Data */905#define A_TTDD 0x7b906907#define A_FXRT2 0x7c908#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */909#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */910#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */911#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */912913#define A_SENDAMOUNTS 0x7d914#define A_FXSENDAMOUNT_E_MASK 0xFF000000915#define A_FXSENDAMOUNT_F_MASK 0x00FF0000916#define A_FXSENDAMOUNT_G_MASK 0x0000FF00917#define A_FXSENDAMOUNT_H_MASK 0x000000FF918/* 0x7c, 0x7e "high bit is used for filtering" */919920/* The send amounts for this one are the same as used with the emu10k1 */921#define A_FXRT1 0x7e922#define A_FXRT_CHANNELA 0x0000003f923#define A_FXRT_CHANNELB 0x00003f00924#define A_FXRT_CHANNELC 0x003f0000925#define A_FXRT_CHANNELD 0x3f000000926927/* 0x7f: Not used */928/* Each FX general purpose register is 32 bits in length, all bits are used */929#define FXGPREGBASE 0x100 /* FX general purpose registers base */930#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */931932#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */933#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */934935/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */936/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */937/* locations are for external TRAM. */938#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */939#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */940941/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */942#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */943#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */944#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */945#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */946#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */947#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */948949#define MICROCODEBASE 0x400 /* Microcode data base address */950951/* Each DSP microcode instruction is mapped into 2 doublewords */952/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */953#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */954#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */955#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */956#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */957#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */958959960/* Audigy Soundcard have a different instruction format */961#define A_MICROCODEBASE 0x600962#define A_LOWORD_OPY_MASK 0x000007ff963#define A_LOWORD_OPX_MASK 0x007ff000964#define A_HIWORD_OPCODE_MASK 0x0f000000965#define A_HIWORD_RESULT_MASK 0x007ff000966#define A_HIWORD_OPA_MASK 0x000007ff967968/************************************************************************************************/969/* EMU1010m HANA FPGA registers */970/************************************************************************************************/971#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */972#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */973#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */974#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */975#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */976#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */977#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */978/* Must be written after power on to reset DLL */979/* One is unable to detect the Audio dock without this */980#define EMU_HANA_WCLOCK_SRC_MASK 0x07981#define EMU_HANA_WCLOCK_INT_48K 0x00982#define EMU_HANA_WCLOCK_INT_44_1K 0x01983#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02984#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03985#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04986#define EMU_HANA_WCLOCK_2ND_HANA 0x05987#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06988#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */989#define EMU_HANA_WCLOCK_MULT_MASK 0x18990#define EMU_HANA_WCLOCK_1X 0x00991#define EMU_HANA_WCLOCK_2X 0x08992#define EMU_HANA_WCLOCK_4X 0x10993#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18994995#define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */996#define EMU_HANA_DEFCLOCK_48K 0x00997#define EMU_HANA_DEFCLOCK_44_1K 0x01998999#define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */1000#define EMU_MUTE 0x001001#define EMU_UNMUTE 0x0110021003#define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */1004#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */1005#define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */10061007#define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */1008#define EMU_HANA_IRQ_WCLK_CHANGED 0x011009#define EMU_HANA_IRQ_ADAT 0x021010#define EMU_HANA_IRQ_DOCK 0x041011#define EMU_HANA_IRQ_DOCK_LOST 0x0810121013#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */1014#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x001015#define EMU_HANA_SPDIF_MODE_TX_PRO 0x011016#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x021017#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x001018#define EMU_HANA_SPDIF_MODE_RX_PRO 0x041019#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x081020#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x1010211022#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */1023#define EMU_HANA_OPTICAL_IN_SPDIF 0x001024#define EMU_HANA_OPTICAL_IN_ADAT 0x011025#define EMU_HANA_OPTICAL_OUT_SPDIF 0x001026#define EMU_HANA_OPTICAL_OUT_ADAT 0x0210271028#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */1029#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */1030#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */10311032#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */1033#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */1034#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */1035#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */1036#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */10371038#define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */1039#define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */1040#define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */1041#define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */1042#define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */1043#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */1044#define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */10451046#define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */1047#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */1048#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */1049#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */1050#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */1051#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */1052#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */10531054#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */1055#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */1056#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */1057#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */1058#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */10591060#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */1061#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */1062#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */1063#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */1064#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */1065#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */1066#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */1067#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */1068#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */10691070#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */1071#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */1072#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */1073#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */1074#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */1075#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */10761077#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */1078#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */1079#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */1080#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */1081#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */1082#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */10831084/* 0x14 - 0x1f Unused R/W registers */1085#define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */1086#if 0 /* Already defined for reg 0x09 IRQ_ENABLE */1087#define EMU_HANA_IRQ_WCLK_CHANGED 0x011088#define EMU_HANA_IRQ_ADAT 0x021089#define EMU_HANA_IRQ_DOCK 0x041090#define EMU_HANA_IRQ_DOCK_LOST 0x081091#endif10921093#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */1094#define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */1095#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */1096#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */1097#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */10981099#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */11001101#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */1102#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */11031104#define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */1105#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */11061107#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */1108#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */1109#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */11101111#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */1112#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */11131114#define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */1115#define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */11161117#define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */1118#define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */11191120#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */1121#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */1122/* 0x30 - 0x3f Unused Read only registers */11231124/************************************************************************************************/1125/* EMU1010m HANA Destinations */1126/************************************************************************************************/1127/* Hana, original 1010,1212,1820 using Alice21128* Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz1129* 0x00, 0x00-0x0f: 16 EMU32 channels to Alice21130* 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock1131* 0x01, 0x00: Dock DAC 1 Left1132* 0x01, 0x04: Dock DAC 1 Right1133* 0x01, 0x08: Dock DAC 2 Left1134* 0x01, 0x0c: Dock DAC 2 Right1135* 0x01, 0x10: Dock DAC 3 Left1136* 0x01, 0x12: PHONES Left1137* 0x01, 0x14: Dock DAC 3 Right1138* 0x01, 0x16: PHONES Right1139* 0x01, 0x18: Dock DAC 4 Left1140* 0x01, 0x1a: S/PDIF Left1141* 0x01, 0x1c: Dock DAC 4 Right1142* 0x01, 0x1e: S/PDIF Right1143* 0x02, 0x00: Hana S/PDIF Left1144* 0x02, 0x01: Hana S/PDIF Right1145* 0x03, 0x00: Hanoa DAC Left1146* 0x03, 0x01: Hanoa DAC Right1147* 0x04, 0x00-0x07: Hana ADAT1148* 0x05, 0x00: I2S0 Left to Alice21149* 0x05, 0x01: I2S0 Right to Alice21150* 0x06, 0x00: I2S0 Left to Alice21151* 0x06, 0x01: I2S0 Right to Alice21152* 0x07, 0x00: I2S0 Left to Alice21153* 0x07, 0x01: I2S0 Right to Alice21154*1155* Hana2 never released, but used Tina1156* Not needed.1157*1158* Hana3, rev2 1010,1212,1616 using Tina1159* Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz1160* 0x00, 0x00-0x0f: 16 EMU32A channels to Tina1161* 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock1162* 0x01, 0x00: Dock DAC 1 Left1163* 0x01, 0x04: Dock DAC 1 Right1164* 0x01, 0x08: Dock DAC 2 Left1165* 0x01, 0x0c: Dock DAC 2 Right1166* 0x01, 0x10: Dock DAC 3 Left1167* 0x01, 0x12: Dock S/PDIF Left1168* 0x01, 0x14: Dock DAC 3 Right1169* 0x01, 0x16: Dock S/PDIF Right1170* 0x01, 0x18-0x1f: Dock ADAT 0-71171* 0x02, 0x00: Hana3 S/PDIF Left1172* 0x02, 0x01: Hana3 S/PDIF Right1173* 0x03, 0x00: Hanoa DAC Left1174* 0x03, 0x01: Hanoa DAC Right1175* 0x04, 0x00-0x07: Hana3 ADAT 0-71176* 0x05, 0x00-0x0f: 16 EMU32B channels to Tina1177* 0x06-0x07: Not used1178*1179* HanaLite, rev1 0404 using Alice21180* Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz1181* 0x00, 0x00-0x0f: 16 EMU32 channels to Alice21182* 0x01: Not used1183* 0x02, 0x00: S/PDIF Left1184* 0x02, 0x01: S/PDIF Right1185* 0x03, 0x00: DAC Left1186* 0x03, 0x01: DAC Right1187* 0x04-0x07: Not used1188*1189* HanaLiteLite, rev2 0404 using Alice21190* Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz1191* 0x00, 0x00-0x0f: 16 EMU32 channels to Alice21192* 0x01: Not used1193* 0x02, 0x00: S/PDIF Left1194* 0x02, 0x01: S/PDIF Right1195* 0x03, 0x00: DAC Left1196* 0x03, 0x01: DAC Right1197* 0x04-0x07: Not used1198*1199* Mana, Cardbus 1616 using Tina21200* Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz1201* 0x00, 0x00-0x0f: 16 EMU32A channels to Tina21202* 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock1203* 0x01, 0x00: Dock DAC 1 Left1204* 0x01, 0x04: Dock DAC 1 Right1205* 0x01, 0x08: Dock DAC 2 Left1206* 0x01, 0x0c: Dock DAC 2 Right1207* 0x01, 0x10: Dock DAC 3 Left1208* 0x01, 0x12: Dock S/PDIF Left1209* 0x01, 0x14: Dock DAC 3 Right1210* 0x01, 0x16: Dock S/PDIF Right1211* 0x01, 0x18-0x1f: Dock ADAT 0-71212* 0x02: Not used1213* 0x03, 0x00: Mana DAC Left1214* 0x03, 0x01: Mana DAC Right1215* 0x04, 0x00-0x0f: 16 EMU32B channels to Tina21216* 0x05-0x07: Not used1217*1218*1219*/1220/* 32-bit destinations of signal in the Hana FPGA. Destinations are either1221* physical outputs of Hana, or outputs going to Alice2 (audigy) for capture1222* - 16 x EMU_DST_ALICE2_EMU32_X.1223*/1224/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */1225/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.1226* Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on1227* setup of mixer control for each destination - see emumixer.c -1228* snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]1229*/1230#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */1231#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */1232#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */1233#define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */1234#define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */1235#define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */1236#define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */1237#define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */1238#define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */1239#define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */1240#define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */1241#define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */1242#define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */1243#define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */1244#define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */1245#define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */1246#define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */1247#define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */1248#define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */1249#define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */1250#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */1251#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */1252#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */1253#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */1254#define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */1255#define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */1256#define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */1257#define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */1258#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */1259#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */1260#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */1261#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */1262#define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */1263#define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */1264#define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */1265#define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */1266#define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */1267#define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */1268#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */1269#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */1270#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */1271#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */1272#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */1273#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */1274#define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */1275#define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */1276#define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */1277#define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */1278#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */1279#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */1280#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */1281#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */1282#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */1283#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */1284#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */1285#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */1286#define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */1287#define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */1288#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */1289#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */1290#define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */1291#define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */1292#define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */1293#define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */1294#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */1295#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */1296#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */1297#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */1298#define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */1299#define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */1300#define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */1301#define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */1302#define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */1303#define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */1304#define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */13051306/* Additional destinations for 1616(M)/Microdock */1307/* Microdock S/PDIF OUT Left, 1st or 48kHz only */1308#define EMU_DST_MDOCK_SPDIF_LEFT1 0x01121309/* Microdock S/PDIF OUT Left, 2nd or 96kHz */1310#define EMU_DST_MDOCK_SPDIF_LEFT2 0x01131311/* Microdock S/PDIF OUT Right, 1st or 48kHz only */1312#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x01161313/* Microdock S/PDIF OUT Right, 2nd or 96kHz */1314#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x01171315/* Microdock S/PDIF ADAT 8 channel out +8 to +f */1316#define EMU_DST_MDOCK_ADAT 0x011813171318/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */1319#define EMU_DST_MANA_DAC_LEFT 0x03001320/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */1321#define EMU_DST_MANA_DAC_RIGHT 0x030113221323/************************************************************************************************/1324/* EMU1010m HANA Sources */1325/************************************************************************************************/1326/* Hana, original 1010,1212,1820 using Alice21327* Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz1328* 0x00,0x00-0x1f: Silence1329* 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock1330* 0x01, 0x00: Dock Mic A1331* 0x01, 0x04: Dock Mic B1332* 0x01, 0x08: Dock ADC 1 Left1333* 0x01, 0x0c: Dock ADC 1 Right1334* 0x01, 0x10: Dock ADC 2 Left1335* 0x01, 0x14: Dock ADC 2 Right1336* 0x01, 0x18: Dock ADC 3 Left1337* 0x01, 0x1c: Dock ADC 3 Right1338* 0x02, 0x00: Hana ADC Left1339* 0x02, 0x01: Hana ADC Right1340* 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output1341* 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output1342* 0x04, 0x00-0x07: Hana ADAT1343* 0x05, 0x00: Hana S/PDIF Left1344* 0x05, 0x01: Hana S/PDIF Right1345* 0x06-0x07: Not used1346*1347* Hana2 never released, but used Tina1348* Not needed.1349*1350* Hana3, rev2 1010,1212,1616 using Tina1351* Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz1352* 0x00,0x00-0x1f: Silence1353* 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock1354* 0x01, 0x00: Dock Mic A1355* 0x01, 0x04: Dock Mic B1356* 0x01, 0x08: Dock ADC 1 Left1357* 0x01, 0x0c: Dock ADC 1 Right1358* 0x01, 0x10: Dock ADC 2 Left1359* 0x01, 0x12: Dock S/PDIF Left1360* 0x01, 0x14: Dock ADC 2 Right1361* 0x01, 0x16: Dock S/PDIF Right1362* 0x01, 0x18-0x1f: Dock ADAT 0-71363* 0x01, 0x18: Dock ADC 3 Left1364* 0x01, 0x1c: Dock ADC 3 Right1365* 0x02, 0x00: Hanoa ADC Left1366* 0x02, 0x01: Hanoa ADC Right1367* 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output1368* 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output1369* 0x04, 0x00-0x07: Hana3 ADAT1370* 0x05, 0x00: Hana3 S/PDIF Left1371* 0x05, 0x01: Hana3 S/PDIF Right1372* 0x06-0x07: Not used1373*1374* HanaLite, rev1 0404 using Alice21375* Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz1376* 0x00,0x00-0x1f: Silence1377* 0x01: Not used1378* 0x02, 0x00: ADC Left1379* 0x02, 0x01: ADC Right1380* 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output1381* 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output1382* 0x04: Not used1383* 0x05, 0x00: S/PDIF Left1384* 0x05, 0x01: S/PDIF Right1385* 0x06-0x07: Not used1386*1387* HanaLiteLite, rev2 0404 using Alice21388* Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz1389* 0x00,0x00-0x1f: Silence1390* 0x01: Not used1391* 0x02, 0x00: ADC Left1392* 0x02, 0x01: ADC Right1393* 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output1394* 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output1395* 0x04: Not used1396* 0x05, 0x00: S/PDIF Left1397* 0x05, 0x01: S/PDIF Right1398* 0x06-0x07: Not used1399*1400* Mana, Cardbus 1616 using Tina21401* Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz1402* 0x00,0x00-0x1f: Silence1403* 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock1404* 0x01, 0x00: Dock Mic A1405* 0x01, 0x04: Dock Mic B1406* 0x01, 0x08: Dock ADC 1 Left1407* 0x01, 0x0c: Dock ADC 1 Right1408* 0x01, 0x10: Dock ADC 2 Left1409* 0x01, 0x12: Dock S/PDIF Left1410* 0x01, 0x14: Dock ADC 2 Right1411* 0x01, 0x16: Dock S/PDIF Right1412* 0x01, 0x18-0x1f: Dock ADAT 0-71413* 0x01, 0x18: Dock ADC 3 Left1414* 0x01, 0x1c: Dock ADC 3 Right1415* 0x02: Not used1416* 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output1417* 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output1418* 0x04-0x07: Not used1419*1420*/14211422/* 32-bit sources of signal in the Hana FPGA. The sources are routed to1423* destinations using mixer control for each destination - see emumixer.c1424* Sources are either physical inputs of FPGA,1425* or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +1426* 16 x EMU_SRC_ALICE_EMU32B1427*/1428#define EMU_SRC_SILENCE 0x0000 /* Silence */1429#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */1430#define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */1431#define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */1432#define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */1433#define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */1434#define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */1435#define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */1436#define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */1437#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */1438#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */1439#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */1440#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */1441#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */1442#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */1443#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */1444#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */1445#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */1446#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */1447#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */1448#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */1449#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */1450#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */1451#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */1452#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */1453#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */1454#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */1455#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */1456#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */1457#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */1458#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */1459#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */1460#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */1461#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */1462#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */1463#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */1464#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */1465#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */1466#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */1467#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */1468#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */1469#define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */1470#define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */1471#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */1472#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */1473#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */1474#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */1475#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */14761477/* Additional inputs for 1616(M)/Microdock */1478/* Microdock S/PDIF Left, 1st or 48kHz only */1479#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x01121480/* Microdock S/PDIF Left, 2nd or 96kHz */1481#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x01131482/* Microdock S/PDIF Right, 1st or 48kHz only */1483#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x01161484/* Microdock S/PDIF Right, 2nd or 96kHz */1485#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x01171486/* Microdock ADAT 8 channel in +8 to +f */1487#define EMU_SRC_MDOCK_ADAT 0x011814881489/* 0x600 and 0x700 no used */14901491/* ------------------- STRUCTURES -------------------- */14921493enum {1494EMU10K1_EFX,1495EMU10K1_PCM,1496EMU10K1_SYNTH,1497EMU10K1_MIDI1498};14991500struct snd_emu10k1;15011502struct snd_emu10k1_voice {1503struct snd_emu10k1 *emu;1504int number;1505unsigned int use: 1,1506pcm: 1,1507efx: 1,1508synth: 1,1509midi: 1;1510void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);15111512struct snd_emu10k1_pcm *epcm;1513};15141515enum {1516PLAYBACK_EMUVOICE,1517PLAYBACK_EFX,1518CAPTURE_AC97ADC,1519CAPTURE_AC97MIC,1520CAPTURE_EFX1521};15221523struct snd_emu10k1_pcm {1524struct snd_emu10k1 *emu;1525int type;1526struct snd_pcm_substream *substream;1527struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];1528struct snd_emu10k1_voice *extra;1529unsigned short running;1530unsigned short first_ptr;1531struct snd_util_memblk *memblk;1532unsigned int start_addr;1533unsigned int ccca_start_addr;1534unsigned int capture_ipr; /* interrupt acknowledge mask */1535unsigned int capture_inte; /* interrupt enable mask */1536unsigned int capture_ba_reg; /* buffer address register */1537unsigned int capture_bs_reg; /* buffer size register */1538unsigned int capture_idx_reg; /* buffer index register */1539unsigned int capture_cr_val; /* control value */1540unsigned int capture_cr_val2; /* control value2 (for audigy) */1541unsigned int capture_bs_val; /* buffer size value */1542unsigned int capture_bufsize; /* buffer size in bytes */1543};15441545struct snd_emu10k1_pcm_mixer {1546/* mono, left, right x 8 sends (4 on emu10k1) */1547unsigned char send_routing[3][8];1548unsigned char send_volume[3][8];1549unsigned short attn[3];1550struct snd_emu10k1_pcm *epcm;1551};15521553#define snd_emu10k1_compose_send_routing(route) \1554((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)15551556#define snd_emu10k1_compose_audigy_fxrt1(route) \1557((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))15581559#define snd_emu10k1_compose_audigy_fxrt2(route) \1560((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))15611562struct snd_emu10k1_memblk {1563struct snd_util_memblk mem;1564/* private part */1565int first_page, last_page, pages, mapped_page;1566unsigned int map_locked;1567struct list_head mapped_link;1568struct list_head mapped_order_link;1569};15701571#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))15721573#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 1615741575struct snd_emu10k1_fx8010_ctl {1576struct list_head list; /* list link container */1577unsigned int vcount;1578unsigned int count; /* count of GPR (1..16) */1579unsigned short gpr[32]; /* GPR number(s) */1580unsigned int value[32];1581unsigned int min; /* minimum range */1582unsigned int max; /* maximum range */1583unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */1584struct snd_kcontrol *kcontrol;1585};15861587typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);15881589struct snd_emu10k1_fx8010_irq {1590struct snd_emu10k1_fx8010_irq *next;1591snd_fx8010_irq_handler_t *handler;1592unsigned short gpr_running;1593void *private_data;1594};15951596struct snd_emu10k1_fx8010_pcm {1597unsigned int valid: 1,1598opened: 1,1599active: 1;1600unsigned int channels; /* 16-bit channels count */1601unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */1602unsigned int buffer_size; /* count of buffered samples */1603unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */1604unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */1605unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */1606unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */1607unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */1608unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */1609unsigned char etram[32]; /* external TRAM address & data */1610struct snd_pcm_indirect pcm_rec;1611unsigned int tram_pos;1612unsigned int tram_shift;1613struct snd_emu10k1_fx8010_irq *irq;1614};16151616struct snd_emu10k1_fx8010 {1617unsigned short fxbus_mask; /* used FX buses (bitmask) */1618unsigned short extin_mask; /* used external inputs (bitmask) */1619unsigned short extout_mask; /* used external outputs (bitmask) */1620unsigned short pad1;1621unsigned int itram_size; /* internal TRAM size in samples */1622struct snd_dma_buffer etram_pages; /* external TRAM pages and size */1623unsigned int dbg; /* FX debugger register */1624unsigned char name[128];1625int gpr_size; /* size of allocated GPR controls */1626int gpr_count; /* count of used kcontrols */1627struct list_head gpr_ctl; /* GPR controls */1628struct mutex lock;1629struct snd_emu10k1_fx8010_pcm pcm[8];1630spinlock_t irq_lock;1631struct snd_emu10k1_fx8010_irq *irq_handlers;1632};16331634struct snd_emu10k1_midi {1635struct snd_emu10k1 *emu;1636struct snd_rawmidi *rmidi;1637struct snd_rawmidi_substream *substream_input;1638struct snd_rawmidi_substream *substream_output;1639unsigned int midi_mode;1640spinlock_t input_lock;1641spinlock_t output_lock;1642spinlock_t open_lock;1643int tx_enable, rx_enable;1644int port;1645int ipr_tx, ipr_rx;1646void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);1647};16481649enum {1650EMU_MODEL_SB,1651EMU_MODEL_EMU1010,1652EMU_MODEL_EMU1010B,1653EMU_MODEL_EMU1616,1654EMU_MODEL_EMU0404,1655};16561657struct snd_emu_chip_details {1658u32 vendor;1659u32 device;1660u32 subsystem;1661unsigned char revision;1662unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */1663unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */1664unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */1665unsigned char ca0108_chip; /* Audigy 2 Value */1666unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */1667unsigned char ca0151_chip; /* P16V */1668unsigned char spk71; /* Has 7.1 speakers */1669unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */1670unsigned char spdif_bug; /* Has Spdif phasing bug */1671unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */1672unsigned char ecard; /* APS EEPROM */1673unsigned char emu_model; /* EMU model type */1674unsigned char spi_dac; /* SPI interface for DAC */1675unsigned char i2c_adc; /* I2C interface for ADC */1676unsigned char adc_1361t; /* Use Philips 1361T ADC */1677unsigned char invert_shared_spdif; /* analog/digital switch inverted */1678const char *driver;1679const char *name;1680const char *id; /* for backward compatibility - can be NULL if not needed */1681};16821683struct snd_emu1010 {1684unsigned int output_source[64];1685unsigned int input_source[64];1686unsigned int adc_pads; /* bit mask */1687unsigned int dac_pads; /* bit mask */1688unsigned int internal_clock; /* 44100 or 48000 */1689unsigned int optical_in; /* 0:SPDIF, 1:ADAT */1690unsigned int optical_out; /* 0:SPDIF, 1:ADAT */1691struct task_struct *firmware_thread;1692};16931694struct snd_emu10k1 {1695int irq;16961697unsigned long port; /* I/O port number */1698unsigned int tos_link: 1, /* tos link detected */1699rear_ac97: 1, /* rear channels are on AC'97 */1700enable_ir: 1;1701unsigned int support_tlv :1;1702/* Contains profile of card capabilities */1703const struct snd_emu_chip_details *card_capabilities;1704unsigned int audigy; /* is Audigy? */1705unsigned int revision; /* chip revision */1706unsigned int serial; /* serial number */1707unsigned short model; /* subsystem id */1708unsigned int card_type; /* EMU10K1_CARD_* */1709unsigned int ecard_ctrl; /* ecard control bits */1710unsigned long dma_mask; /* PCI DMA mask */1711unsigned int delay_pcm_irq; /* in samples */1712int max_cache_pages; /* max memory size / PAGE_SIZE */1713struct snd_dma_buffer silent_page; /* silent page */1714struct snd_dma_buffer ptb_pages; /* page table pages */1715struct snd_dma_device p16v_dma_dev;1716struct snd_dma_buffer p16v_buffer;17171718struct snd_util_memhdr *memhdr; /* page allocation list */1719struct snd_emu10k1_memblk *reserved_page; /* reserved page */17201721struct list_head mapped_link_head;1722struct list_head mapped_order_link_head;1723void **page_ptr_table;1724unsigned long *page_addr_table;1725spinlock_t memblk_lock;17261727unsigned int spdif_bits[3]; /* s/pdif out setup */1728unsigned int i2c_capture_source;1729u8 i2c_capture_volume[4][2];17301731struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */1732int gpr_base;17331734struct snd_ac97 *ac97;17351736struct pci_dev *pci;1737struct snd_card *card;1738struct snd_pcm *pcm;1739struct snd_pcm *pcm_mic;1740struct snd_pcm *pcm_efx;1741struct snd_pcm *pcm_multi;1742struct snd_pcm *pcm_p16v;17431744spinlock_t synth_lock;1745void *synth;1746int (*get_synth_voice)(struct snd_emu10k1 *emu);17471748spinlock_t reg_lock;1749spinlock_t emu_lock;1750spinlock_t voice_lock;1751spinlock_t spi_lock; /* serialises access to spi port */1752spinlock_t i2c_lock; /* serialises access to i2c port */17531754struct snd_emu10k1_voice voices[NUM_G];1755struct snd_emu10k1_voice p16v_voices[4];1756struct snd_emu10k1_voice p16v_capture_voice;1757int p16v_device_offset;1758u32 p16v_capture_source;1759u32 p16v_capture_channel;1760struct snd_emu1010 emu1010;1761struct snd_emu10k1_pcm_mixer pcm_mixer[32];1762struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];1763struct snd_kcontrol *ctl_send_routing;1764struct snd_kcontrol *ctl_send_volume;1765struct snd_kcontrol *ctl_attn;1766struct snd_kcontrol *ctl_efx_send_routing;1767struct snd_kcontrol *ctl_efx_send_volume;1768struct snd_kcontrol *ctl_efx_attn;17691770void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);1771void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);1772void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);1773void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);1774void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);1775void (*dsp_interrupt)(struct snd_emu10k1 *emu);17761777struct snd_pcm_substream *pcm_capture_substream;1778struct snd_pcm_substream *pcm_capture_mic_substream;1779struct snd_pcm_substream *pcm_capture_efx_substream;1780struct snd_pcm_substream *pcm_playback_efx_substream;17811782struct snd_timer *timer;17831784struct snd_emu10k1_midi midi;1785struct snd_emu10k1_midi midi2; /* for audigy */17861787unsigned int efx_voices_mask[2];1788unsigned int next_free_voice;17891790#ifdef CONFIG_PM1791unsigned int *saved_ptr;1792unsigned int *saved_gpr;1793unsigned int *tram_val_saved;1794unsigned int *tram_addr_saved;1795unsigned int *saved_icode;1796unsigned int *p16v_saved;1797unsigned int saved_a_iocfg, saved_hcfg;1798#endif17991800};18011802int snd_emu10k1_create(struct snd_card *card,1803struct pci_dev *pci,1804unsigned short extin_mask,1805unsigned short extout_mask,1806long max_cache_bytes,1807int enable_ir,1808uint subsystem,1809struct snd_emu10k1 ** remu);18101811int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);1812int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);1813int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);1814int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);1815int snd_p16v_free(struct snd_emu10k1 * emu);1816int snd_p16v_mixer(struct snd_emu10k1 * emu);1817int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);1818int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);1819int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);1820int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);1821int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);18221823irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);18241825void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);1826int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);1827void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);1828int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);1829int snd_emu10k1_done(struct snd_emu10k1 * emu);18301831/* I/O functions */1832unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);1833void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);1834unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);1835void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);1836int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);1837int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);1838int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);1839int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);1840int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);1841unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);1842void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);1843void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);1844void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);1845void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);1846void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);1847void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);1848void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);1849void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);1850void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);1851void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);1852void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);1853static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }1854unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);1855void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);1856unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);18571858#ifdef CONFIG_PM1859void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);1860void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);1861void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);1862int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);1863void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);1864void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);1865void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);1866int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);1867void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);1868void snd_p16v_suspend(struct snd_emu10k1 *emu);1869void snd_p16v_resume(struct snd_emu10k1 *emu);1870#endif18711872/* memory allocation */1873struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);1874int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);1875struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);1876int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);1877int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);1878int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);1879int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);18801881/* voice allocation */1882int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);1883int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);18841885/* MIDI uart */1886int snd_emu10k1_midi(struct snd_emu10k1 * emu);1887int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);18881889/* proc interface */1890int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);18911892/* fx8010 irq handler */1893int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,1894snd_fx8010_irq_handler_t *handler,1895unsigned char gpr_running,1896void *private_data,1897struct snd_emu10k1_fx8010_irq **r_irq);1898int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,1899struct snd_emu10k1_fx8010_irq *irq);19001901#endif /* __KERNEL__ */19021903/*1904* ---- FX8010 ----1905*/19061907#define EMU10K1_CARD_CREATIVE 0x000000001908#define EMU10K1_CARD_EMUAPS 0x0000000119091910#define EMU10K1_FX8010_PCM_COUNT 819111912/* instruction set */1913#define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */1914#define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */1915#define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */1916#define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */1917#define iMACINT0 0x04 /* R = A + X * Y ; saturation */1918#define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */1919#define iACC3 0x06 /* R = A + X + Y ; saturation */1920#define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */1921#define iANDXOR 0x08 /* R = (A & X) ^ Y */1922#define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */1923#define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */1924#define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */1925#define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */1926#define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */1927#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */1928#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */19291930/* GPRs */1931#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */1932#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */1933#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */1934#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */1935/* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */19361937#define C_00000000 0x401938#define C_00000001 0x411939#define C_00000002 0x421940#define C_00000003 0x431941#define C_00000004 0x441942#define C_00000008 0x451943#define C_00000010 0x461944#define C_00000020 0x471945#define C_00000100 0x481946#define C_00010000 0x491947#define C_00080000 0x4a1948#define C_10000000 0x4b1949#define C_20000000 0x4c1950#define C_40000000 0x4d1951#define C_80000000 0x4e1952#define C_7fffffff 0x4f1953#define C_ffffffff 0x501954#define C_fffffffe 0x511955#define C_c0000000 0x521956#define C_4f1bbcdc 0x531957#define C_5a7ef9db 0x541958#define C_00100000 0x55 /* ?? */1959#define GPR_ACCU 0x56 /* ACCUM, accumulator */1960#define GPR_COND 0x57 /* CCR, condition register */1961#define GPR_NOISE0 0x58 /* noise source */1962#define GPR_NOISE1 0x59 /* noise source */1963#define GPR_IRQ 0x5a /* IRQ register */1964#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */1965#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */1966#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */1967#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */1968#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */1969#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */19701971#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */1972#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */1973#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */1974#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */1975#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */1976#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */19771978#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */1979#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */1980#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */1981#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */1982#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */1983#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */1984#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */1985#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */1986#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */1987#define A_GPR(x) (A_FXGPREGBASE + (x))19881989/* cc_reg constants */1990#define CC_REG_NORMALIZED C_000000011991#define CC_REG_BORROW C_000000021992#define CC_REG_MINUS C_000000041993#define CC_REG_ZERO C_000000081994#define CC_REG_SATURATE C_000000101995#define CC_REG_NONZERO C_0000010019961997/* FX buses */1998#define FXBUS_PCM_LEFT 0x001999#define FXBUS_PCM_RIGHT 0x012000#define FXBUS_PCM_LEFT_REAR 0x022001#define FXBUS_PCM_RIGHT_REAR 0x032002#define FXBUS_MIDI_LEFT 0x042003#define FXBUS_MIDI_RIGHT 0x052004#define FXBUS_PCM_CENTER 0x062005#define FXBUS_PCM_LFE 0x072006#define FXBUS_PCM_LEFT_FRONT 0x082007#define FXBUS_PCM_RIGHT_FRONT 0x092008#define FXBUS_MIDI_REVERB 0x0c2009#define FXBUS_MIDI_CHORUS 0x0d2010#define FXBUS_PCM_LEFT_SIDE 0x0e2011#define FXBUS_PCM_RIGHT_SIDE 0x0f2012#define FXBUS_PT_LEFT 0x142013#define FXBUS_PT_RIGHT 0x1520142015/* Inputs */2016#define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */2017#define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */2018#define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */2019#define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */2020#define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */2021#define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */2022#define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */2023#define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */2024#define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */2025#define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */2026#define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */2027#define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */2028#define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */2029#define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */20302031/* Outputs */2032#define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */2033#define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */2034#define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */2035#define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */2036#define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */2037#define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */2038#define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */2039#define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */2040#define EXTOUT_REAR_L 0x08 /* Rear channel - left */2041#define EXTOUT_REAR_R 0x09 /* Rear channel - right */2042#define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */2043#define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */2044#define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */2045#define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */2046#define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */2047#define EXTOUT_ACENTER 0x11 /* Analog Center */2048#define EXTOUT_ALFE 0x12 /* Analog LFE */20492050/* Audigy Inputs */2051#define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */2052#define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */2053#define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */2054#define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */2055#define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */2056#define A_EXTIN_OPT_SPDIF_R 0x05 /* right */2057#define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */2058#define A_EXTIN_LINE2_R 0x09 /* right */2059#define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */2060#define A_EXTIN_ADC_R 0x0b /* right */2061#define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */2062#define A_EXTIN_AUX2_R 0x0d /* - right */20632064/* Audigiy Outputs */2065#define A_EXTOUT_FRONT_L 0x00 /* digital front left */2066#define A_EXTOUT_FRONT_R 0x01 /* right */2067#define A_EXTOUT_CENTER 0x02 /* digital front center */2068#define A_EXTOUT_LFE 0x03 /* digital front lfe */2069#define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */2070#define A_EXTOUT_HEADPHONE_R 0x05 /* right */2071#define A_EXTOUT_REAR_L 0x06 /* digital rear left */2072#define A_EXTOUT_REAR_R 0x07 /* right */2073#define A_EXTOUT_AFRONT_L 0x08 /* analog front left */2074#define A_EXTOUT_AFRONT_R 0x09 /* right */2075#define A_EXTOUT_ACENTER 0x0a /* analog center */2076#define A_EXTOUT_ALFE 0x0b /* analog LFE */2077#define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */2078#define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */2079#define A_EXTOUT_AREAR_L 0x0e /* analog rear left */2080#define A_EXTOUT_AREAR_R 0x0f /* right */2081#define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */2082#define A_EXTOUT_AC97_R 0x11 /* right */2083#define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */2084#define A_EXTOUT_ADC_CAP_R 0x17 /* right */2085#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */20862087/* Audigy constants */2088#define A_C_00000000 0xc02089#define A_C_00000001 0xc12090#define A_C_00000002 0xc22091#define A_C_00000003 0xc32092#define A_C_00000004 0xc42093#define A_C_00000008 0xc52094#define A_C_00000010 0xc62095#define A_C_00000020 0xc72096#define A_C_00000100 0xc82097#define A_C_00010000 0xc92098#define A_C_00000800 0xca2099#define A_C_10000000 0xcb2100#define A_C_20000000 0xcc2101#define A_C_40000000 0xcd2102#define A_C_80000000 0xce2103#define A_C_7fffffff 0xcf2104#define A_C_ffffffff 0xd02105#define A_C_fffffffe 0xd12106#define A_C_c0000000 0xd22107#define A_C_4f1bbcdc 0xd32108#define A_C_5a7ef9db 0xd42109#define A_C_00100000 0xd52110#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */2111#define A_GPR_COND 0xd7 /* CCR, condition register */2112#define A_GPR_NOISE0 0xd8 /* noise source */2113#define A_GPR_NOISE1 0xd9 /* noise source */2114#define A_GPR_IRQ 0xda /* IRQ register */2115#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */2116#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */21172118/* definitions for debug register */2119#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */2120#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */2121#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */2122#define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */2123#define EMU10K1_DBG_STEP 0x00004000 /* start single step */2124#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */2125#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */21262127/* tank memory address line */2128#ifndef __KERNEL__2129#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */2130#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */2131#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */2132#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */2133#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */2134#endif21352136struct snd_emu10k1_fx8010_info {2137unsigned int internal_tram_size; /* in samples */2138unsigned int external_tram_size; /* in samples */2139char fxbus_names[16][32]; /* names of FXBUSes */2140char extin_names[16][32]; /* names of external inputs */2141char extout_names[32][32]; /* names of external outputs */2142unsigned int gpr_controls; /* count of GPR controls */2143};21442145#define EMU10K1_GPR_TRANSLATION_NONE 02146#define EMU10K1_GPR_TRANSLATION_TABLE100 12147#define EMU10K1_GPR_TRANSLATION_BASS 22148#define EMU10K1_GPR_TRANSLATION_TREBLE 32149#define EMU10K1_GPR_TRANSLATION_ONOFF 421502151struct snd_emu10k1_fx8010_control_gpr {2152struct snd_ctl_elem_id id; /* full control ID definition */2153unsigned int vcount; /* visible count */2154unsigned int count; /* count of GPR (1..16) */2155unsigned short gpr[32]; /* GPR number(s) */2156unsigned int value[32]; /* initial values */2157unsigned int min; /* minimum range */2158unsigned int max; /* maximum range */2159unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */2160const unsigned int *tlv;2161};21622163/* old ABI without TLV support */2164struct snd_emu10k1_fx8010_control_old_gpr {2165struct snd_ctl_elem_id id;2166unsigned int vcount;2167unsigned int count;2168unsigned short gpr[32];2169unsigned int value[32];2170unsigned int min;2171unsigned int max;2172unsigned int translation;2173};21742175struct snd_emu10k1_fx8010_code {2176char name[128];21772178DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */2179__u32 __user *gpr_map; /* initializers */21802181unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */2182struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */21832184unsigned int gpr_del_control_count; /* count of GPR controls to remove */2185struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */21862187unsigned int gpr_list_control_count; /* count of GPR controls to list */2188unsigned int gpr_list_control_total; /* total count of GPR controls */2189struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */21902191DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */2192__u32 __user *tram_data_map; /* data initializers */2193__u32 __user *tram_addr_map; /* map initializers */21942195DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */2196__u32 __user *code; /* one instruction - 64 bits */2197};21982199struct snd_emu10k1_fx8010_tram {2200unsigned int address; /* 31.bit == 1 -> external TRAM */2201unsigned int size; /* size in samples (4 bytes) */2202unsigned int *samples; /* pointer to samples (20-bit) */2203/* NULL->clear memory */2204};22052206struct snd_emu10k1_fx8010_pcm_rec {2207unsigned int substream; /* substream number */2208unsigned int res1; /* reserved */2209unsigned int channels; /* 16-bit channels count, zero = remove this substream */2210unsigned int tram_start; /* ring buffer position in TRAM (in samples) */2211unsigned int buffer_size; /* count of buffered samples */2212unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */2213unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */2214unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */2215unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */2216unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */2217unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */2218unsigned char pad; /* reserved */2219unsigned char etram[32]; /* external TRAM address & data (one per channel) */2220unsigned int res2; /* reserved */2221};22222223#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)22242225#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)2226#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)2227#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)2228#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)2229#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)2230#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)2231#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)2232#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)2233#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)2234#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)2235#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)2236#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)2237#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)2238#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)22392240/* typedefs for compatibility to user-space */2241typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;2242typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;2243typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;2244typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;2245typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;22462247#endif /* __SOUND_EMU10K1_H */224822492250