Path: blob/master/include/xen/interface/hvm/params.h
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/*1* Permission is hereby granted, free of charge, to any person obtaining a copy2* of this software and associated documentation files (the "Software"), to3* deal in the Software without restriction, including without limitation the4* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or5* sell copies of the Software, and to permit persons to whom the Software is6* furnished to do so, subject to the following conditions:7*8* The above copyright notice and this permission notice shall be included in9* all copies or substantial portions of the Software.10*11* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR12* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,13* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE14* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER15* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING16* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER17* DEALINGS IN THE SOFTWARE.18*/1920#ifndef __XEN_PUBLIC_HVM_PARAMS_H__21#define __XEN_PUBLIC_HVM_PARAMS_H__2223#include "hvm_op.h"2425/*26* Parameter space for HVMOP_{set,get}_param.27*/2829/*30* How should CPU0 event-channel notifications be delivered?31* val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).32* val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:33* Domain = val[47:32], Bus = val[31:16],34* DevFn = val[15: 8], IntX = val[ 1: 0]35* val[63:56] == 2: val[7:0] is a vector number.36* If val == 0 then CPU0 event-channel notifications are not delivered.37*/38#define HVM_PARAM_CALLBACK_IRQ 03940#define HVM_PARAM_STORE_PFN 141#define HVM_PARAM_STORE_EVTCHN 24243#define HVM_PARAM_PAE_ENABLED 44445#define HVM_PARAM_IOREQ_PFN 54647#define HVM_PARAM_BUFIOREQ_PFN 64849/*50* Set mode for virtual timers (currently x86 only):51* delay_for_missed_ticks (default):52* Do not advance a vcpu's time beyond the correct delivery time for53* interrupts that have been missed due to preemption. Deliver missed54* interrupts when the vcpu is rescheduled and advance the vcpu's virtual55* time stepwise for each one.56* no_delay_for_missed_ticks:57* As above, missed interrupts are delivered, but guest time always tracks58* wallclock (i.e., real) time while doing so.59* no_missed_ticks_pending:60* No missed interrupts are held pending. Instead, to ensure ticks are61* delivered at some non-zero rate, if we detect missed ticks then the62* internal tick alarm is not disabled if the VCPU is preempted during the63* next tick period.64* one_missed_tick_pending:65* Missed interrupts are collapsed together and delivered as one 'late tick'.66* Guest time always tracks wallclock (i.e., real) time.67*/68#define HVM_PARAM_TIMER_MODE 1069#define HVMPTM_delay_for_missed_ticks 070#define HVMPTM_no_delay_for_missed_ticks 171#define HVMPTM_no_missed_ticks_pending 272#define HVMPTM_one_missed_tick_pending 37374/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */75#define HVM_PARAM_HPET_ENABLED 117677/* Identity-map page directory used by Intel EPT when CR0.PG=0. */78#define HVM_PARAM_IDENT_PT 127980/* Device Model domain, defaults to 0. */81#define HVM_PARAM_DM_DOMAIN 138283/* ACPI S state: currently support S0 and S3 on x86. */84#define HVM_PARAM_ACPI_S_STATE 148586/* TSS used on Intel when CR0.PE=0. */87#define HVM_PARAM_VM86_TSS 158889/* Boolean: Enable aligning all periodic vpts to reduce interrupts */90#define HVM_PARAM_VPT_ALIGN 169192#define HVM_NR_PARAMS 179394#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */959697