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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/sound/pci/aw2/saa7146.h
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/*****************************************************************************

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 *

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 * Copyright (C) 2008 Cedric Bregardis <[email protected]> and

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 * Jean-Christian Hassler <[email protected]>

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 *

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 * This file is part of the Audiowerk2 ALSA driver

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 *

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 * The Audiowerk2 ALSA driver is free software; you can redistribute it and/or

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 * modify it under the terms of the GNU General Public License as published by

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 * the Free Software Foundation; version 2.

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 *

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 * The Audiowerk2 ALSA driver is distributed in the hope that it will be useful,

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 * but WITHOUT ANY WARRANTY; without even the implied warranty of

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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 * GNU General Public License for more details.

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 *

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 * You should have received a copy of the GNU General Public License

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 * along with the Audiowerk2 ALSA driver; if not, write to the Free Software

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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,

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 * USA.

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 *

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 *****************************************************************************/

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/* SAA7146 registers */

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#define PCI_BT_A	0x4C

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#define IICTFR		0x8C

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#define IICSTA		0x90

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#define BaseA1_in	0x94

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#define ProtA1_in	0x98

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#define PageA1_in	0x9C

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#define BaseA1_out	0xA0

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#define ProtA1_out	0xA4

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#define PageA1_out	0xA8

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#define BaseA2_in	0xAC

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#define ProtA2_in	0xB0

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#define PageA2_in	0xB4

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#define BaseA2_out	0xB8

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#define ProtA2_out	0xBC

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#define PageA2_out	0xC0

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#define IER		0xDC

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#define GPIO_CTRL	0xE0

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#define ACON1		0xF4

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#define ACON2		0xF8

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#define MC1		0xFC

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#define MC2		0x100

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#define ISR		0x10C

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#define PSR		0x110

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#define SSR		0x114

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#define PCI_ADP1	0x12C

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#define PCI_ADP2	0x130

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#define PCI_ADP3	0x134

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#define PCI_ADP4	0x138

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#define LEVEL_REP	0x140

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#define FB_BUFFER1	0x144

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#define FB_BUFFER2	0x148

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#define TSL1		0x180

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#define TSL2		0x1C0

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#define ME	(1UL << 11)

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#define LIMIT	(1UL << 4)

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#define PV	(1UL << 3)

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/* PSR/ISR/IER */

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#define PPEF		(1UL << 31)

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#define PABO		(1UL << 30)

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#define IIC_S		(1UL << 17)

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#define IIC_E		(1UL << 16)

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#define A2_in		(1UL << 15)

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#define A2_out		(1UL << 14)

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#define A1_in		(1UL << 13)

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#define A1_out		(1UL << 12)

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#define AFOU		(1UL << 11)

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#define PIN3		(1UL << 6)

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#define PIN2		(1UL << 5)

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#define PIN1		(1UL << 4)

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#define PIN0		(1UL << 3)

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#define ECS		(1UL << 2)

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#define EC3S		(1UL << 1)

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#define EC0S		(1UL << 0)

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/* SSR */

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#define PRQ		(1UL << 31)

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#define PMA		(1UL << 30)

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#define IIC_EA		(1UL << 21)

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#define IIC_EW		(1UL << 20)

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#define IIC_ER		(1UL << 19)

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#define IIC_EL		(1UL << 18)

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#define IIC_EF		(1UL << 17)

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#define AF2_in		(1UL << 10)

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#define AF2_out		(1UL << 9)

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#define AF1_in		(1UL << 8)

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#define AF1_out		(1UL << 7)

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#define EC5S		(1UL << 3)

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#define EC4S		(1UL << 2)

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#define EC2S		(1UL << 1)

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#define EC1S		(1UL << 0)

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/* PCI_BT_A */

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#define BurstA1_in	(1UL << 26)

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#define ThreshA1_in	(1UL << 24)

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#define BurstA1_out	(1UL << 18)

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#define ThreshA1_out	(1UL << 16)

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#define BurstA2_in	(1UL << 10)

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#define ThreshA2_in	(1UL << 8)

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#define BurstA2_out	(1UL << 2)

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#define ThreshA2_out	(1UL << 0)

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/* MC1 */

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#define MRST_N		(1UL << 15)

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#define EAP		(1UL << 9)

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#define EI2C		(1UL << 8)

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#define TR_E_A2_OUT	(1UL << 3)

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#define TR_E_A2_IN	(1UL << 2)

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#define TR_E_A1_OUT	(1UL << 1)

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#define TR_E_A1_IN	(1UL << 0)

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/* MC2 */

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#define UPLD_IIC	(1UL << 0)

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/* ACON1 */

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#define AUDIO_MODE	(1UL << 29)

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#define MAXLEVEL	(1UL << 22)

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#define A1_SWAP		(1UL << 21)

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#define A2_SWAP		(1UL << 20)

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#define WS0_CTRL	(1UL << 18)

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#define WS0_SYNC	(1UL << 16)

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#define WS1_CTRL	(1UL << 14)

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#define WS1_SYNC	(1UL << 12)

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#define WS2_CTRL	(1UL << 10)

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#define WS2_SYNC	(1UL << 8)

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#define WS3_CTRL	(1UL << 6)

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#define WS3_SYNC	(1UL << 4)

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#define WS4_CTRL	(1UL << 2)

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#define WS4_SYNC	(1UL << 0)

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/* ACON2 */

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#define A1_CLKSRC	(1UL << 27)

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#define A2_CLKSRC	(1UL << 22)

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#define INVERT_BCLK1	(1UL << 21)

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#define INVERT_BCLK2	(1UL << 20)

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#define BCLK1_OEN	(1UL << 19)

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#define BCLK2_OEN	(1UL << 18)

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/* IICSTA */

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#define IICCC		(1UL << 8)

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#define ABORT		(1UL << 7)

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#define SPERR		(1UL << 6)

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#define APERR		(1UL << 5)

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#define DTERR		(1UL << 4)

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#define DRERR		(1UL << 3)

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#define AL		(1UL << 2)

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#define ERR		(1UL << 1)

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#define BUSY		(1UL << 0)

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/* IICTFR */

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#define BYTE2		(1UL << 24)

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#define BYTE1		(1UL << 16)

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#define BYTE0		(1UL << 8)

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#define ATRR2		(1UL << 6)

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#define ATRR1		(1UL << 4)

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#define ATRR0		(1UL << 2)

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#define ERR		(1UL << 1)

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#define BUSY		(1UL << 0)

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#define START	3

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#define CONT	2

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#define STOP	1

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#define NOP	0

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