/*1* Audio support for PS32* Copyright (C) 2007 Sony Computer Entertainment Inc.3* Copyright 2006, 2007 Sony Corporation4* All rights reserved.5*6* This program is free software; you can redistribute it and/or modify7* it under the terms of the GNU General Public License8* as published by the Free Software Foundation; version 2 of the License.9*10* This program is distributed in the hope that it will be useful,11* but WITHOUT ANY WARRANTY; without even the implied warranty of12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the13* GNU General Public License for more details.14*15* You should have received a copy of the GNU General Public License16* along with this program; if not, write to the Free Software17* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA18*/1920/*21* interrupt / configure registers22*/2324#define PS3_AUDIO_INTR_0 (0x00000100)25#define PS3_AUDIO_INTR_EN_0 (0x00000140)26#define PS3_AUDIO_CONFIG (0x00000200)2728/*29* DMAC registers30* n:0..931*/32#define PS3_AUDIO_DMAC_REGBASE(x) (0x0000210 + 0x20 * (x))3334#define PS3_AUDIO_KICK(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x00)35#define PS3_AUDIO_SOURCE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x04)36#define PS3_AUDIO_DEST(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x08)37#define PS3_AUDIO_DMASIZE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C)3839/*40* mute control41*/42#define PS3_AUDIO_AX_MCTRL (0x00004000)43#define PS3_AUDIO_AX_ISBP (0x00004004)44#define PS3_AUDIO_AX_AOBP (0x00004008)45#define PS3_AUDIO_AX_IC (0x00004010)46#define PS3_AUDIO_AX_IE (0x00004014)47#define PS3_AUDIO_AX_IS (0x00004018)4849/*50* three wire serial51* n:0..352*/53#define PS3_AUDIO_AO_MCTRL (0x00006000)54#define PS3_AUDIO_AO_3WMCTRL (0x00006004)5556#define PS3_AUDIO_AO_3WCTRL(n) (0x00006200 + 0x200 * (n))5758/*59* S/PDIF60* n:0..161* x:0..1162* y:0..563*/64#define PS3_AUDIO_AO_SPD_REGBASE(n) (0x00007200 + 0x200 * (n))6566#define PS3_AUDIO_AO_SPDCTRL(n) \67(PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00)68#define PS3_AUDIO_AO_SPDUB(n, x) \69(PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x))70#define PS3_AUDIO_AO_SPDCS(n, y) \71(PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y))727374/*75PS3_AUDIO_INTR_0 register tells an interrupt handler which audio76DMA channel triggered the interrupt. The interrupt status for a channel77can be cleared by writing a '1' to the corresponding bit. A new interrupt78cannot be generated until the previous interrupt has been cleared.7980Note that the status reported by PS3_AUDIO_INTR_0 is independent of the81value of PS3_AUDIO_INTR_EN_0.828331 24 23 16 15 8 7 084+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+85|0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_086+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+87*/88#define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2))89#define PS3_AUDIO_INTR_0_CHAN9 PS3_AUDIO_INTR_0_CHAN(9)90#define PS3_AUDIO_INTR_0_CHAN8 PS3_AUDIO_INTR_0_CHAN(8)91#define PS3_AUDIO_INTR_0_CHAN7 PS3_AUDIO_INTR_0_CHAN(7)92#define PS3_AUDIO_INTR_0_CHAN6 PS3_AUDIO_INTR_0_CHAN(6)93#define PS3_AUDIO_INTR_0_CHAN5 PS3_AUDIO_INTR_0_CHAN(5)94#define PS3_AUDIO_INTR_0_CHAN4 PS3_AUDIO_INTR_0_CHAN(4)95#define PS3_AUDIO_INTR_0_CHAN3 PS3_AUDIO_INTR_0_CHAN(3)96#define PS3_AUDIO_INTR_0_CHAN2 PS3_AUDIO_INTR_0_CHAN(2)97#define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1)98#define PS3_AUDIO_INTR_0_CHAN0 PS3_AUDIO_INTR_0_CHAN(0)99100/*101The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate102an interrupt to the PU. Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the103corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together104to generate the Audio interrupt.10510631 24 23 16 15 8 7 0107+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+108|0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_0109+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+110111Bit assignments are same as PS3_AUDIO_INTR_0112*/113114/*115PS3_AUDIO_CONFIG11631 24 23 16 15 8 7 0117+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+118|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG119+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+120121*/122123/* The CLEAR field cancels all pending transfers, and stops any running DMA124transfers. Any interrupts associated with the canceled transfers125will occur as if the transfer had finished.126Since this bit is designed to recover from DMA related issues127which are caused by unpredictable situations, it is preferred to wait128for normal DMA transfer end without using this bit.129*/130#define PS3_AUDIO_CONFIG_CLEAR (1 << 8) /* RWIVF */131132/*133PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register13413531 24 23 16 15 8 7 0136+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+137|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL138+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+139*/140141/* 3 Wire Audio Serial Output Channel Mutes (0..3) */142#define PS3_AUDIO_AX_MCTRL_ASOMT(n) (1 << (3 - (n))) /* RWIVF */143#define PS3_AUDIO_AX_MCTRL_ASO3MT (1 << 0) /* RWIVF */144#define PS3_AUDIO_AX_MCTRL_ASO2MT (1 << 1) /* RWIVF */145#define PS3_AUDIO_AX_MCTRL_ASO1MT (1 << 2) /* RWIVF */146#define PS3_AUDIO_AX_MCTRL_ASO0MT (1 << 3) /* RWIVF */147148/* S/PDIF mutes (0,1)*/149#define PS3_AUDIO_AX_MCTRL_SPOMT(n) (1 << (5 - (n))) /* RWIVF */150#define PS3_AUDIO_AX_MCTRL_SPO1MT (1 << 4) /* RWIVF */151#define PS3_AUDIO_AX_MCTRL_SPO0MT (1 << 5) /* RWIVF */152153/* All 3 Wire Serial Outputs Mute */154#define PS3_AUDIO_AX_MCTRL_AASOMT (1 << 13) /* RWIVF */155156/* All S/PDIF Mute */157#define PS3_AUDIO_AX_MCTRL_ASPOMT (1 << 14) /* RWIVF */158159/* All Audio Outputs Mute */160#define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */161162/*163S/PDIF Outputs Buffer Read/Write Pointer Register16416531 24 23 16 15 8 7 0166+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+167|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP168+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+169170*/171/*172S/PDIF Output Channel Read Buffer Numbers173Buffer number is value of field.174Indicates current read access buffer ID from Audio Data175Transfer controller of S/PDIF Output176*/177178#define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */179#define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK (0x7 << 0) /* R-IUF */180#define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK (0x7 << 4) /* R-IUF */181182/*183S/PDIF Output Channel Buffer Write Numbers184Indicates current write access buffer ID from bus master.185*/186#define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 << 4 * (5 - (n))) /* R-IUF */187#define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK (0x7 << 16) /* R-IUF */188#define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK (0x7 << 20) /* R-IUF */189190/*1913 Wire Audio Serial Outputs Buffer Read/Write192Pointer Register193Buffer number is value of field19419531 24 23 16 15 8 7 0196+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+197|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP198+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+199*/200201/*2023 Wire Audio Serial Output Channel Buffer Read Numbers203Indicates current read access buffer Id from Audio Data Transfer204Controller of 3 Wire Audio Serial Output Channels205*/206#define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */207208#define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK (0x7 << 0) /* R-IUF */209#define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK (0x7 << 4) /* R-IUF */210#define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK (0x7 << 8) /* R-IUF */211#define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK (0x7 << 12) /* R-IUF */212213/*2143 Wire Audio Serial Output Channel Buffer Write Numbers215Indicates current write access buffer ID from bus master.216*/217#define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */218219#define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK (0x7 << 16) /* R-IUF */220#define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK (0x7 << 20) /* R-IUF */221#define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK (0x7 << 24) /* R-IUF */222#define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK (0x7 << 28) /* R-IUF */223224225226/*227Audio Port Interrupt Condition Register228For the fields in this register, the following values apply:2290 = Interrupt is generated every interrupt event.2301 = Interrupt is generated every 2 interrupt events.2312 = Interrupt is generated every 4 interrupt events.2323 = Reserved23323423531 24 23 16 15 8 7 0236+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+237|0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC238+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+239*/240/*241All 3-Wire Audio Serial Outputs Interrupt Mode242Configures the Interrupt and Signal Notification243condition of all 3-wire Audio Serial Outputs.244*/245#define PS3_AUDIO_AX_IC_AASOIMD_MASK (0x3 << 12) /* RWIVF */246#define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */247#define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */248#define PS3_AUDIO_AX_IC_AASOIMD_EVERY4 (0x2 << 12) /* RW--V */249250/*251S/PDIF Output Channel Interrupt Modes252Configures the Interrupt and signal Notification253conditions of S/PDIF output channels.254*/255#define PS3_AUDIO_AX_IC_SPO1IMD_MASK (0x3 << 16) /* RWIVF */256#define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1 (0x0 << 16) /* RWI-V */257#define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2 (0x1 << 16) /* RW--V */258#define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4 (0x2 << 16) /* RW--V */259260#define PS3_AUDIO_AX_IC_SPO0IMD_MASK (0x3 << 20) /* RWIVF */261#define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1 (0x0 << 20) /* RWI-V */262#define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2 (0x1 << 20) /* RW--V */263#define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4 (0x2 << 20) /* RW--V */264265/*266Audio Port interrupt Enable Register267Configures whether to enable or disable each Interrupt Generation.26826927031 24 23 16 15 8 7 0271+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+272|0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE273+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+274275*/276277/*2783 Wire Audio Serial Output Channel Buffer Underflow279Interrupt Enables280Select enable/disable of Buffer Underflow Interrupts for2813-Wire Audio Serial Output Channels282DISABLED=Interrupt generation disabled.283*/284#define PS3_AUDIO_AX_IE_ASOBUIE(n) (1 << (3 - (n))) /* RWIVF */285#define PS3_AUDIO_AX_IE_ASO3BUIE (1 << 0) /* RWIVF */286#define PS3_AUDIO_AX_IE_ASO2BUIE (1 << 1) /* RWIVF */287#define PS3_AUDIO_AX_IE_ASO1BUIE (1 << 2) /* RWIVF */288#define PS3_AUDIO_AX_IE_ASO0BUIE (1 << 3) /* RWIVF */289290/* S/PDIF Output Channel Buffer Underflow Interrupt Enables */291292#define PS3_AUDIO_AX_IE_SPOBUIE(n) (1 << (7 - (n))) /* RWIVF */293#define PS3_AUDIO_AX_IE_SPO1BUIE (1 << 6) /* RWIVF */294#define PS3_AUDIO_AX_IE_SPO0BUIE (1 << 7) /* RWIVF */295296/* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */297298#define PS3_AUDIO_AX_IE_SPOBTCIE(n) (1 << (11 - (n))) /* RWIVF */299#define PS3_AUDIO_AX_IE_SPO1BTCIE (1 << 10) /* RWIVF */300#define PS3_AUDIO_AX_IE_SPO0BTCIE (1 << 11) /* RWIVF */301302/* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */303304#define PS3_AUDIO_AX_IE_ASOBEIE(n) (1 << (19 - (n))) /* RWIVF */305#define PS3_AUDIO_AX_IE_ASO3BEIE (1 << 16) /* RWIVF */306#define PS3_AUDIO_AX_IE_ASO2BEIE (1 << 17) /* RWIVF */307#define PS3_AUDIO_AX_IE_ASO1BEIE (1 << 18) /* RWIVF */308#define PS3_AUDIO_AX_IE_ASO0BEIE (1 << 19) /* RWIVF */309310/* S/PDIF Output Channel Buffer Empty Interrupt Enables */311312#define PS3_AUDIO_AX_IE_SPOBEIE(n) (1 << (23 - (n))) /* RWIVF */313#define PS3_AUDIO_AX_IE_SPO1BEIE (1 << 22) /* RWIVF */314#define PS3_AUDIO_AX_IE_SPO0BEIE (1 << 23) /* RWIVF */315316/*317Audio Port Interrupt Status Register318Indicates Interrupt status, which interrupt has occurred, and can clear319each interrupt in this register.320Writing 1b to a field containing 1b clears field and de-asserts interrupt.321Writing 0b to a field has no effect.322Field vaules are the following:3230 - Interrupt hasn't occurred.3241 - Interrupt has occurred.32532632731 24 23 16 15 8 7 0328+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+329|0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS330+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+331332Bit assignment are same as AX_IE333*/334335/*336Audio Output Master Control Register337Configures Master Clock and other master Audio Output Settings33833934031 24 23 16 15 8 7 0341+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+342|0|SCKSE|0|SCKSE| MR0 | MR1 |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL343+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+344*/345346/*347MCLK Output Control348Controls mclko[1] output.3490 - Disable output (fixed at High)3501 - Output clock produced by clock selected351with scksel1 by mr13522 - Reserved3533 - Reserved354*/355356#define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK (0x3 << 12) /* RWIVF */357#define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED (0x0 << 12) /* RWI-V */358#define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED (0x1 << 12) /* RW--V */359#define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2 (0x2 << 12) /* RW--V */360#define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3 (0x3 << 12) /* RW--V */361362/*363MCLK Output Control364Controls mclko[0] output.3650 - Disable output (fixed at High)3661 - Output clock produced by clock selected367with SCKSEL0 by MR03682 - Reserved3693 - Reserved370*/371#define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK (0x3 << 14) /* RWIVF */372#define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED (0x0 << 14) /* RWI-V */373#define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED (0x1 << 14) /* RW--V */374#define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2 (0x2 << 14) /* RW--V */375#define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3 (0x3 << 14) /* RW--V */376/*377Master Clock Rate 1378Sets the divide ration of Master Clock1 (clock output from379mclko[1] for the input clock selected by scksel1.380*/381#define PS3_AUDIO_AO_MCTRL_MR1_MASK (0xf << 16)382#define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT (0x0 << 16) /* RWI-V */383/*384Master Clock Rate 0385Sets the divide ratio of Master Clock0 (clock output from386mclko[0] for the input clock selected by scksel0).387*/388#define PS3_AUDIO_AO_MCTRL_MR0_MASK (0xf << 20) /* RWIVF */389#define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT (0x0 << 20) /* RWI-V */390/*391System Clock Select 0/1392Selects the system clock to be used as Master Clock 0/1393Input the system clock that is appropriate for the sampling394rate.395*/396#define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK (0x7 << 24) /* RWIVF */397#define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT (0x2 << 24) /* RWI-V */398399#define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK (0x7 << 28) /* RWIVF */400#define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT (0x2 << 28) /* RWI-V */401402403/*4043-Wire Audio Output Master Control Register405Configures clock, 3-Wire Audio Serial Output Enable, and406other 3-Wire Audio Serial Output Master Settings40740840931 24 23 16 15 8 7 0410+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+411|A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL412+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+413*/414415416/*417LRCKO Polarity4180 - Reserved4191 - default420*/421#define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK (1 << 8) /* RWIVF */422#define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT (1 << 8) /* RW--V */423424/* LRCK Output Disable */425426#define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD (1 << 10) /* RWIVF */427#define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED (0 << 10) /* RW--V */428#define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED (1 << 10) /* RWI-V */429430/* Bit Clock Output Disable */431432#define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD (1 << 11) /* RWIVF */433#define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED (0 << 11) /* RW--V */434#define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED (1 << 11) /* RWI-V */435436/*4373-Wire Audio Serial Output Channel 0-3 Operational438Status. Each bit becomes 1 after each 3-Wire Audio439Serial Output Channel N is in action by setting 1 to440asoen.441Each bit becomes 0 after each 3-Wire Audio Serial Output442Channel N is out of action by setting 0 to asoen.443*/444#define PS3_AUDIO_AO_3WMCTRL_ASORUN(n) (1 << (15 - (n))) /* R-IVF */445#define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n) (0 << (15 - (n))) /* R-I-V */446#define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n) (1 << (15 - (n))) /* R---V */447#define PS3_AUDIO_AO_3WMCTRL_ASORUN0 \448PS3_AUDIO_AO_3WMCTRL_ASORUN(0)449#define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED \450PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0)451#define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING \452PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0)453#define PS3_AUDIO_AO_3WMCTRL_ASORUN1 \454PS3_AUDIO_AO_3WMCTRL_ASORUN(1)455#define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED \456PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1)457#define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING \458PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1)459#define PS3_AUDIO_AO_3WMCTRL_ASORUN2 \460PS3_AUDIO_AO_3WMCTRL_ASORUN(2)461#define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED \462PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2)463#define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING \464PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2)465#define PS3_AUDIO_AO_3WMCTRL_ASORUN3 \466PS3_AUDIO_AO_3WMCTRL_ASORUN(3)467#define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED \468PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3)469#define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING \470PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3)471472/*473Sampling Rate474Specifies the divide ratio of the bit clock (clock output475from bclko) used by the 3-wire Audio Output Clock, which476is applied to the master clock selected by mcksel.477Data output is synchronized with this clock.478*/479#define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK (0xf << 20) /* RWIVF */480#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2 (0x1 << 20) /* RWI-V */481#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4 (0x2 << 20) /* RW--V */482#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8 (0x4 << 20) /* RW--V */483#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12 (0x6 << 20) /* RW--V */484485/*486Master Clock Select4870 - Master Clock 04881 - Master Clock 1489*/490#define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL (1 << 24) /* RWIVF */491#define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0 (0 << 24) /* RWI-V */492#define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1 (1 << 24) /* RW--V */493494/*495Enables and disables 4ch 3-Wire Audio Serial Output496operation. Each Bit from 0 to 3 corresponds to an497output channel, which means that each output channel498can be enabled or disabled individually. When499multiple channels are enabled at the same time, output500operations are performed in synchronization.501Bit 0 - Output Channel 0 (SDOUT[0])502Bit 1 - Output Channel 1 (SDOUT[1])503Bit 2 - Output Channel 2 (SDOUT[2])504Bit 3 - Output Channel 3 (SDOUT[3])505*/506#define PS3_AUDIO_AO_3WMCTRL_ASOEN(n) (1 << (31 - (n))) /* RWIVF */507#define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n) (0 << (31 - (n))) /* RWI-V */508#define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n) (1 << (31 - (n))) /* RW--V */509510#define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \511PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */512#define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \513PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */514#define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \515PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */516#define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \517PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */518#define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \519PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */520#define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \521PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */522#define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \523PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */524#define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \525PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */526#define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \527PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */528#define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \529PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */530#define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \531PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */532#define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \533PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */534535/*5363-Wire Audio Serial output Channel 0-3 Control Register537Configures settings for 3-Wire Serial Audio Output Channel 0-353853954031 24 23 16 15 8 7 0541+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+542|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL543+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+544545*/546/*547Data Bit Mode548Specifies the number of data bits5490 - 16 bits5501 - reserved5512 - 20 bits5523 - 24 bits553*/554#define PS3_AUDIO_AO_3WCTRL_ASODB_MASK (0x3 << 8) /* RWIVF */555#define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */556#define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */557#define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */558#define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */559/*560Data Format Mode561Specifies the data format where (LSB side or MSB) the data(in 20 bit562or 24 bit resolution mode) is put in a 32 bit field.5630 - Data put on LSB side5641 - Data put on MSB side565*/566#define PS3_AUDIO_AO_3WCTRL_ASODF (1 << 11) /* RWIVF */567#define PS3_AUDIO_AO_3WCTRL_ASODF_LSB (0 << 11) /* RWI-V */568#define PS3_AUDIO_AO_3WCTRL_ASODF_MSB (1 << 11) /* RW--V */569/*570Buffer Reset571Performs buffer reset. Writing 1 to this bit initializes the572corresponding 3-Wire Audio Output buffers(both L and R).573*/574#define PS3_AUDIO_AO_3WCTRL_ASOBRST (1 << 16) /* CWIVF */575#define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE (0 << 16) /* -WI-V */576#define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET (1 << 16) /* -W--T */577578/*579S/PDIF Audio Output Channel 0/1 Control Register580Configures settings for S/PDIF Audio Output Channel 0/1.58158231 24 23 16 15 8 7 0583+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+584|S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL585+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+586*/587/*588Buffer reset. Writing 1 to this bit initializes the589corresponding S/PDIF output buffer pointer.590*/591#define PS3_AUDIO_AO_SPDCTRL_SPOBRST (1 << 0) /* CWIVF */592#define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE (0 << 0) /* -WI-V */593#define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET (1 << 0) /* -W--T */594595/*596Data Bit Mode597Specifies number of data bits5980 - 16 bits5991 - Reserved6002 - 20 bits6013 - 24 bits602*/603#define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK (0x3 << 8) /* RWIVF */604#define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT (0x0 << 8) /* RWI-V */605#define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD (0x1 << 8) /* RW--V */606#define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT (0x2 << 8) /* RW--V */607#define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT (0x3 << 8) /* RW--V */608/*609Data format Mode610Specifies the data format, where (LSB side or MSB)611the data(in 20 or 24 bit resolution) is put in the61232 bit field.6130 - LSB Side6141 - MSB Side615*/616#define PS3_AUDIO_AO_SPDCTRL_SPODF (1 << 11) /* RWIVF */617#define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB (0 << 11) /* RWI-V */618#define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB (1 << 11) /* RW--V */619/*620Source Select621Specifies the source of the S/PDIF output. When 0, output622operation is controlled by 3wen[0] of AO_3WMCTRL register.623The SR must have the same setting as the a0_3wmctrl reg.6240 - 3-Wire Audio OUT Ch0 Buffer6251 - S/PDIF buffer626*/627#define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK (0x3 << 16) /* RWIVF */628#define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN (0x0 << 16) /* RWI-V */629#define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF (0x1 << 16) /* RW--V */630/*631Sampling Rate632Specifies the divide ratio of the bit clock (clock output633from bclko) used by the S/PDIF Output Clock, which634is applied to the master clock selected by mcksel.635*/636#define PS3_AUDIO_AO_SPDCTRL_SPOSR (0xf << 20) /* RWIVF */637#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2 (0x1 << 20) /* RWI-V */638#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4 (0x2 << 20) /* RW--V */639#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8 (0x4 << 20) /* RW--V */640#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12 (0x6 << 20) /* RW--V */641/*642Master Clock Select6430 - Master Clock 06441 - Master Clock 1645*/646#define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL (1 << 24) /* RWIVF */647#define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0 (0 << 24) /* RWI-V */648#define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1 (1 << 24) /* RW--V */649650/*651S/PDIF Output Channel Operational Status652This bit becomes 1 after S/PDIF Output Channel is in653action by setting 1 to spoen. This bit becomes 0654after S/PDIF Output Channel is out of action by setting6550 to spoen.656*/657#define PS3_AUDIO_AO_SPDCTRL_SPORUN (1 << 27) /* R-IVF */658#define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED (0 << 27) /* R-I-V */659#define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING (1 << 27) /* R---V */660661/*662S/PDIF Audio Output Channel Output Enable663Enables and disables output operation. This bit is used664only when sposs = 1665*/666#define PS3_AUDIO_AO_SPDCTRL_SPOEN (1 << 31) /* RWIVF */667#define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED (0 << 31) /* RWI-V */668#define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED (1 << 31) /* RW--V */669670/*671S/PDIF Audio Output Channel Channel Status672Setting Registers.673Configures channel status bit settings for each block674(192 bits).675Output is performed from the MSB(AO_SPDCS0 register bit 31).676The same value is added for subframes within the same frame.67731 24 23 16 15 8 7 0678+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+679| SPOCS | AO_SPDCS680+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+681682S/PDIF Audio Output Channel User Bit Setting683Configures user bit settings for each block (384 bits).684Output is performed from the MSB(ao_spdub0 register bit 31).68568668731 24 23 16 15 8 7 0688+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+689| SPOUB | AO_SPDUB690+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+691*/692/*****************************************************************************693*694* DMAC register695*696*****************************************************************************/697/*698The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor699its status70070131 24 23 16 15 8 7 0702+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+703|0 0 0 0 0|STATU|0 0 0| EVENT |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK704+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+705*/706/*707The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT708occurs.709It will return to the DONE state when the request is completed.710The registers for a DMA channel should only be written if REQUEST is IDLE.711*/712713#define PS3_AUDIO_KICK_REQUEST (1 << 0) /* RWIVF */714#define PS3_AUDIO_KICK_REQUEST_IDLE (0 << 0) /* RWI-V */715#define PS3_AUDIO_KICK_REQUEST_ACTIVE (1 << 0) /* -W--T */716717/*718*The EVENT field is used to set the event in which719*the DMA request becomes active.720*/721#define PS3_AUDIO_KICK_EVENT_MASK (0x1f << 16) /* RWIVF */722#define PS3_AUDIO_KICK_EVENT_ALWAYS (0x00 << 16) /* RWI-V */723#define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */724#define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW (0x02 << 16) /* RW--V */725#define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY (0x03 << 16) /* RW--V */726#define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW (0x04 << 16) /* RW--V */727#define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY (0x05 << 16) /* RW--V */728#define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW (0x06 << 16) /* RW--V */729#define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY (0x07 << 16) /* RW--V */730#define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW (0x08 << 16) /* RW--V */731#define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \732(0x09 << 16) /* RW--V */733#define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW (0x0A << 16) /* RW--V */734#define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY (0x0B << 16) /* RW--V */735#define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \736(0x0C << 16) /* RW--V */737#define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW (0x0D << 16) /* RW--V */738#define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY (0x0E << 16) /* RW--V */739740#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \741((0x13 + (n)) << 16) /* RW--V */742#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0 (0x13 << 16) /* RW--V */743#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1 (0x14 << 16) /* RW--V */744#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2 (0x15 << 16) /* RW--V */745#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3 (0x16 << 16) /* RW--V */746#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4 (0x17 << 16) /* RW--V */747#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5 (0x18 << 16) /* RW--V */748#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6 (0x19 << 16) /* RW--V */749#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7 (0x1A << 16) /* RW--V */750#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8 (0x1B << 16) /* RW--V */751#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9 (0x1C << 16) /* RW--V */752753/*754The STATUS field can be used to monitor the progress of a DMA request.755DONE indicates the previous request has completed.756EVENT indicates that the DMA engine is waiting for the EVENT to occur.757PENDING indicates that the DMA engine has not started processing this758request, but the EVENT has occurred.759DMA indicates that the data transfer is in progress.760NOTIFY indicates that the notifier signalling end of transfer is being written.761CLEAR indicated that the previous transfer was cleared.762ERROR indicates the previous transfer requested an unsupported763source/destination combination.764*/765766#define PS3_AUDIO_KICK_STATUS_MASK (0x7 << 24) /* R-IVF */767#define PS3_AUDIO_KICK_STATUS_DONE (0x0 << 24) /* R-I-V */768#define PS3_AUDIO_KICK_STATUS_EVENT (0x1 << 24) /* R---V */769#define PS3_AUDIO_KICK_STATUS_PENDING (0x2 << 24) /* R---V */770#define PS3_AUDIO_KICK_STATUS_DMA (0x3 << 24) /* R---V */771#define PS3_AUDIO_KICK_STATUS_NOTIFY (0x4 << 24) /* R---V */772#define PS3_AUDIO_KICK_STATUS_CLEAR (0x5 << 24) /* R---V */773#define PS3_AUDIO_KICK_STATUS_ERROR (0x6 << 24) /* R---V */774775/*776The PS3_AUDIO_SOURCE register specifies the source address for transfers.77777877931 24 23 16 15 8 7 0780+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+781| START |0 0 0 0 0|TAR| SOURCE782+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+783*/784785/*786The Audio DMA engine uses 128-byte transfers, thus the address must be aligned787to a 128 byte boundary. The low seven bits are assumed to be 0.788*/789790#define PS3_AUDIO_SOURCE_START_MASK (0x01FFFFFF << 7) /* RWIUF */791792/*793The TARGET field specifies the memory space containing the source address.794*/795796#define PS3_AUDIO_SOURCE_TARGET_MASK (3 << 0) /* RWIVF */797#define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY (2 << 0) /* RW--V */798799/*800The PS3_AUDIO_DEST register specifies the destination address for transfers.80180280331 24 23 16 15 8 7 0804+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+805| START |0 0 0 0 0|TAR| DEST806+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+807*/808809/*810The Audio DMA engine uses 128-byte transfers, thus the address must be aligned811to a 128 byte boundary. The low seven bits are assumed to be 0.812*/813814#define PS3_AUDIO_DEST_START_MASK (0x01FFFFFF << 7) /* RWIUF */815816/*817The TARGET field specifies the memory space containing the destination address818AUDIOFIFO = Audio WriteData FIFO,819*/820821#define PS3_AUDIO_DEST_TARGET_MASK (3 << 0) /* RWIVF */822#define PS3_AUDIO_DEST_TARGET_AUDIOFIFO (1 << 0) /* RW--V */823824/*825PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer.826So a value of 0 means 128-bytes will get transferred.82782882931 24 23 16 15 8 7 0830+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+831|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| BLOCKS | DMASIZE832+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+833*/834835836#define PS3_AUDIO_DMASIZE_BLOCKS_MASK (0x7f << 0) /* RWIUF */837838/*839* source/destination address for internal fifos840*/841#define PS3_AUDIO_AO_3W_LDATA(n) (0x1000 + (0x100 * (n)))842#define PS3_AUDIO_AO_3W_RDATA(n) (0x1080 + (0x100 * (n)))843844#define PS3_AUDIO_AO_SPD_DATA(n) (0x2000 + (0x400 * (n)))845846847/*848* field attiribute849*850* Read851* ' ' = Other Information852* '-' = Field is part of a write-only register853* 'C' = Value read is always the same, constant value line follows (C)854* 'R' = Value is read855*856* Write857* ' ' = Other Information858* '-' = Must not be written (D), value ignored when written (R,A,F)859* 'W' = Can be written860*861* Internal State862* ' ' = Other Information863* '-' = No internal state864* 'X' = Internal state, initial value is unknown865* 'I' = Internal state, initial value is known and follows (I)866*867* Declaration/Size868* ' ' = Other Information869* '-' = Does Not Apply870* 'V' = Type is void871* 'U' = Type is unsigned integer872* 'S' = Type is signed integer873* 'F' = Type is IEEE floating point874* '1' = Byte size (008)875* '2' = Short size (016)876* '3' = Three byte size (024)877* '4' = Word size (032)878* '8' = Double size (064)879*880* Define Indicator881* ' ' = Other Information882* 'D' = Device883* 'M' = Memory884* 'R' = Register885* 'A' = Array of Registers886* 'F' = Field887* 'V' = Value888* 'T' = Task889*/890891892893