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awilliam
GitHub Repository: awilliam/linux-vfio
Path: blob/master/sound/soc/blackfin/bf5xx-sport.c
10817 views
1
/*
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* File: bf5xx_sport.c
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* Based on:
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* Author: Roy Huang <[email protected]>
5
*
6
* Created: Tue Sep 21 10:52:42 CEST 2004
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* Description:
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* Blackfin SPORT Driver
9
*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
29
30
#include <linux/kernel.h>
31
#include <linux/slab.h>
32
#include <linux/delay.h>
33
#include <linux/dma-mapping.h>
34
#include <linux/gpio.h>
35
#include <linux/bug.h>
36
#include <asm/portmux.h>
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#include <asm/dma.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
40
41
#include "bf5xx-sport.h"
42
/* delay between frame sync pulse and first data bit in multichannel mode */
43
#define FRAME_DELAY (1<<12)
44
45
/* note: multichannel is in units of 8 channels,
46
* tdm_count is # channels NOT / 8 ! */
47
int sport_set_multichannel(struct sport_device *sport,
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int tdm_count, u32 mask, int packed)
49
{
50
pr_debug("%s tdm_count=%d mask:0x%08x packed=%d\n", __func__,
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tdm_count, mask, packed);
52
53
if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
54
return -EBUSY;
55
56
if (tdm_count & 0x7)
57
return -EINVAL;
58
59
if (tdm_count > 32)
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return -EINVAL; /* Only support less than 32 channels now */
61
62
if (tdm_count) {
63
sport->regs->mcmc1 = ((tdm_count>>3)-1) << 12;
64
sport->regs->mcmc2 = FRAME_DELAY | MCMEN | \
65
(packed ? (MCDTXPE|MCDRXPE) : 0);
66
67
sport->regs->mtcs0 = mask;
68
sport->regs->mrcs0 = mask;
69
sport->regs->mtcs1 = 0;
70
sport->regs->mrcs1 = 0;
71
sport->regs->mtcs2 = 0;
72
sport->regs->mrcs2 = 0;
73
sport->regs->mtcs3 = 0;
74
sport->regs->mrcs3 = 0;
75
} else {
76
sport->regs->mcmc1 = 0;
77
sport->regs->mcmc2 = 0;
78
79
sport->regs->mtcs0 = 0;
80
sport->regs->mrcs0 = 0;
81
}
82
83
sport->regs->mtcs1 = 0; sport->regs->mtcs2 = 0; sport->regs->mtcs3 = 0;
84
sport->regs->mrcs1 = 0; sport->regs->mrcs2 = 0; sport->regs->mrcs3 = 0;
85
86
SSYNC();
87
88
return 0;
89
}
90
EXPORT_SYMBOL(sport_set_multichannel);
91
92
int sport_config_rx(struct sport_device *sport, unsigned int rcr1,
93
unsigned int rcr2, unsigned int clkdiv, unsigned int fsdiv)
94
{
95
if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
96
return -EBUSY;
97
98
sport->regs->rcr1 = rcr1;
99
sport->regs->rcr2 = rcr2;
100
sport->regs->rclkdiv = clkdiv;
101
sport->regs->rfsdiv = fsdiv;
102
103
SSYNC();
104
105
return 0;
106
}
107
EXPORT_SYMBOL(sport_config_rx);
108
109
int sport_config_tx(struct sport_device *sport, unsigned int tcr1,
110
unsigned int tcr2, unsigned int clkdiv, unsigned int fsdiv)
111
{
112
if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
113
return -EBUSY;
114
115
sport->regs->tcr1 = tcr1;
116
sport->regs->tcr2 = tcr2;
117
sport->regs->tclkdiv = clkdiv;
118
sport->regs->tfsdiv = fsdiv;
119
120
SSYNC();
121
122
return 0;
123
}
124
EXPORT_SYMBOL(sport_config_tx);
125
126
static void setup_desc(struct dmasg *desc, void *buf, int fragcount,
127
size_t fragsize, unsigned int cfg,
128
unsigned int x_count, unsigned int ycount, size_t wdsize)
129
{
130
131
int i;
132
133
for (i = 0; i < fragcount; ++i) {
134
desc[i].next_desc_addr = &(desc[i + 1]);
135
desc[i].start_addr = (unsigned long)buf + i*fragsize;
136
desc[i].cfg = cfg;
137
desc[i].x_count = x_count;
138
desc[i].x_modify = wdsize;
139
desc[i].y_count = ycount;
140
desc[i].y_modify = wdsize;
141
}
142
143
/* make circular */
144
desc[fragcount-1].next_desc_addr = desc;
145
146
pr_debug("setup desc: desc0=%p, next0=%p, desc1=%p,"
147
"next1=%p\nx_count=%x,y_count=%x,addr=0x%lx,cfs=0x%x\n",
148
desc, desc[0].next_desc_addr,
149
desc+1, desc[1].next_desc_addr,
150
desc[0].x_count, desc[0].y_count,
151
desc[0].start_addr, desc[0].cfg);
152
}
153
154
static int sport_start(struct sport_device *sport)
155
{
156
enable_dma(sport->dma_rx_chan);
157
enable_dma(sport->dma_tx_chan);
158
sport->regs->rcr1 |= RSPEN;
159
sport->regs->tcr1 |= TSPEN;
160
SSYNC();
161
162
return 0;
163
}
164
165
static int sport_stop(struct sport_device *sport)
166
{
167
sport->regs->tcr1 &= ~TSPEN;
168
sport->regs->rcr1 &= ~RSPEN;
169
SSYNC();
170
171
disable_dma(sport->dma_rx_chan);
172
disable_dma(sport->dma_tx_chan);
173
return 0;
174
}
175
176
static inline int sport_hook_rx_dummy(struct sport_device *sport)
177
{
178
struct dmasg *desc, temp_desc;
179
unsigned long flags;
180
181
BUG_ON(sport->dummy_rx_desc == NULL);
182
BUG_ON(sport->curr_rx_desc == sport->dummy_rx_desc);
183
184
/* Maybe the dummy buffer descriptor ring is damaged */
185
sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc + 1;
186
187
local_irq_save(flags);
188
desc = get_dma_next_desc_ptr(sport->dma_rx_chan);
189
/* Copy the descriptor which will be damaged to backup */
190
temp_desc = *desc;
191
desc->x_count = sport->dummy_count / 2;
192
desc->y_count = 0;
193
desc->next_desc_addr = sport->dummy_rx_desc;
194
local_irq_restore(flags);
195
/* Waiting for dummy buffer descriptor is already hooked*/
196
while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
197
sizeof(struct dmasg)) != sport->dummy_rx_desc)
198
continue;
199
sport->curr_rx_desc = sport->dummy_rx_desc;
200
/* Restore the damaged descriptor */
201
*desc = temp_desc;
202
203
return 0;
204
}
205
206
static inline int sport_rx_dma_start(struct sport_device *sport, int dummy)
207
{
208
if (dummy) {
209
sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc;
210
sport->curr_rx_desc = sport->dummy_rx_desc;
211
} else
212
sport->curr_rx_desc = sport->dma_rx_desc;
213
214
set_dma_next_desc_addr(sport->dma_rx_chan, sport->curr_rx_desc);
215
set_dma_x_count(sport->dma_rx_chan, 0);
216
set_dma_x_modify(sport->dma_rx_chan, 0);
217
set_dma_config(sport->dma_rx_chan, (DMAFLOW_LARGE | NDSIZE_9 | \
218
WDSIZE_32 | WNR));
219
set_dma_curr_addr(sport->dma_rx_chan, sport->curr_rx_desc->start_addr);
220
SSYNC();
221
222
return 0;
223
}
224
225
static inline int sport_tx_dma_start(struct sport_device *sport, int dummy)
226
{
227
if (dummy) {
228
sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc;
229
sport->curr_tx_desc = sport->dummy_tx_desc;
230
} else
231
sport->curr_tx_desc = sport->dma_tx_desc;
232
233
set_dma_next_desc_addr(sport->dma_tx_chan, sport->curr_tx_desc);
234
set_dma_x_count(sport->dma_tx_chan, 0);
235
set_dma_x_modify(sport->dma_tx_chan, 0);
236
set_dma_config(sport->dma_tx_chan,
237
(DMAFLOW_LARGE | NDSIZE_9 | WDSIZE_32));
238
set_dma_curr_addr(sport->dma_tx_chan, sport->curr_tx_desc->start_addr);
239
SSYNC();
240
241
return 0;
242
}
243
244
int sport_rx_start(struct sport_device *sport)
245
{
246
unsigned long flags;
247
pr_debug("%s enter\n", __func__);
248
if (sport->rx_run)
249
return -EBUSY;
250
if (sport->tx_run) {
251
/* tx is running, rx is not running */
252
BUG_ON(sport->dma_rx_desc == NULL);
253
BUG_ON(sport->curr_rx_desc != sport->dummy_rx_desc);
254
local_irq_save(flags);
255
while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
256
sizeof(struct dmasg)) != sport->dummy_rx_desc)
257
continue;
258
sport->dummy_rx_desc->next_desc_addr = sport->dma_rx_desc;
259
local_irq_restore(flags);
260
sport->curr_rx_desc = sport->dma_rx_desc;
261
} else {
262
sport_tx_dma_start(sport, 1);
263
sport_rx_dma_start(sport, 0);
264
sport_start(sport);
265
}
266
267
sport->rx_run = 1;
268
269
return 0;
270
}
271
EXPORT_SYMBOL(sport_rx_start);
272
273
int sport_rx_stop(struct sport_device *sport)
274
{
275
pr_debug("%s enter\n", __func__);
276
277
if (!sport->rx_run)
278
return 0;
279
if (sport->tx_run) {
280
/* TX dma is still running, hook the dummy buffer */
281
sport_hook_rx_dummy(sport);
282
} else {
283
/* Both rx and tx dma will be stopped */
284
sport_stop(sport);
285
sport->curr_rx_desc = NULL;
286
sport->curr_tx_desc = NULL;
287
}
288
289
sport->rx_run = 0;
290
291
return 0;
292
}
293
EXPORT_SYMBOL(sport_rx_stop);
294
295
static inline int sport_hook_tx_dummy(struct sport_device *sport)
296
{
297
struct dmasg *desc, temp_desc;
298
unsigned long flags;
299
300
BUG_ON(sport->dummy_tx_desc == NULL);
301
BUG_ON(sport->curr_tx_desc == sport->dummy_tx_desc);
302
303
sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc + 1;
304
305
/* Shorten the time on last normal descriptor */
306
local_irq_save(flags);
307
desc = get_dma_next_desc_ptr(sport->dma_tx_chan);
308
/* Store the descriptor which will be damaged */
309
temp_desc = *desc;
310
desc->x_count = sport->dummy_count / 2;
311
desc->y_count = 0;
312
desc->next_desc_addr = sport->dummy_tx_desc;
313
local_irq_restore(flags);
314
/* Waiting for dummy buffer descriptor is already hooked*/
315
while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - \
316
sizeof(struct dmasg)) != sport->dummy_tx_desc)
317
continue;
318
sport->curr_tx_desc = sport->dummy_tx_desc;
319
/* Restore the damaged descriptor */
320
*desc = temp_desc;
321
322
return 0;
323
}
324
325
int sport_tx_start(struct sport_device *sport)
326
{
327
unsigned long flags;
328
pr_debug("%s: tx_run:%d, rx_run:%d\n", __func__,
329
sport->tx_run, sport->rx_run);
330
if (sport->tx_run)
331
return -EBUSY;
332
if (sport->rx_run) {
333
BUG_ON(sport->dma_tx_desc == NULL);
334
BUG_ON(sport->curr_tx_desc != sport->dummy_tx_desc);
335
/* Hook the normal buffer descriptor */
336
local_irq_save(flags);
337
while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) -
338
sizeof(struct dmasg)) != sport->dummy_tx_desc)
339
continue;
340
sport->dummy_tx_desc->next_desc_addr = sport->dma_tx_desc;
341
local_irq_restore(flags);
342
sport->curr_tx_desc = sport->dma_tx_desc;
343
} else {
344
345
sport_tx_dma_start(sport, 0);
346
/* Let rx dma run the dummy buffer */
347
sport_rx_dma_start(sport, 1);
348
sport_start(sport);
349
}
350
sport->tx_run = 1;
351
return 0;
352
}
353
EXPORT_SYMBOL(sport_tx_start);
354
355
int sport_tx_stop(struct sport_device *sport)
356
{
357
if (!sport->tx_run)
358
return 0;
359
if (sport->rx_run) {
360
/* RX is still running, hook the dummy buffer */
361
sport_hook_tx_dummy(sport);
362
} else {
363
/* Both rx and tx dma stopped */
364
sport_stop(sport);
365
sport->curr_rx_desc = NULL;
366
sport->curr_tx_desc = NULL;
367
}
368
369
sport->tx_run = 0;
370
371
return 0;
372
}
373
EXPORT_SYMBOL(sport_tx_stop);
374
375
static inline int compute_wdsize(size_t wdsize)
376
{
377
switch (wdsize) {
378
case 1:
379
return WDSIZE_8;
380
case 2:
381
return WDSIZE_16;
382
case 4:
383
default:
384
return WDSIZE_32;
385
}
386
}
387
388
int sport_config_rx_dma(struct sport_device *sport, void *buf,
389
int fragcount, size_t fragsize)
390
{
391
unsigned int x_count;
392
unsigned int y_count;
393
unsigned int cfg;
394
dma_addr_t addr;
395
396
pr_debug("%s buf:%p, frag:%d, fragsize:0x%lx\n", __func__, \
397
buf, fragcount, fragsize);
398
399
x_count = fragsize / sport->wdsize;
400
y_count = 0;
401
402
/* for fragments larger than 64k words we use 2d dma,
403
* denote fragecount as two numbers' mutliply and both of them
404
* are less than 64k.*/
405
if (x_count >= 0x10000) {
406
int i, count = x_count;
407
408
for (i = 16; i > 0; i--) {
409
x_count = 1 << i;
410
if ((count & (x_count - 1)) == 0) {
411
y_count = count >> i;
412
if (y_count < 0x10000)
413
break;
414
}
415
}
416
if (i == 0)
417
return -EINVAL;
418
}
419
pr_debug("%s(x_count:0x%x, y_count:0x%x)\n", __func__,
420
x_count, y_count);
421
422
if (sport->dma_rx_desc)
423
dma_free_coherent(NULL, sport->rx_desc_bytes,
424
sport->dma_rx_desc, 0);
425
426
/* Allocate a new descritor ring as current one. */
427
sport->dma_rx_desc = dma_alloc_coherent(NULL, \
428
fragcount * sizeof(struct dmasg), &addr, 0);
429
sport->rx_desc_bytes = fragcount * sizeof(struct dmasg);
430
431
if (!sport->dma_rx_desc) {
432
pr_err("Failed to allocate memory for rx desc\n");
433
return -ENOMEM;
434
}
435
436
sport->rx_buf = buf;
437
sport->rx_fragsize = fragsize;
438
sport->rx_frags = fragcount;
439
440
cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | WNR | \
441
(DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
442
443
if (y_count != 0)
444
cfg |= DMA2D;
445
446
setup_desc(sport->dma_rx_desc, buf, fragcount, fragsize,
447
cfg|DMAEN, x_count, y_count, sport->wdsize);
448
449
return 0;
450
}
451
EXPORT_SYMBOL(sport_config_rx_dma);
452
453
int sport_config_tx_dma(struct sport_device *sport, void *buf, \
454
int fragcount, size_t fragsize)
455
{
456
unsigned int x_count;
457
unsigned int y_count;
458
unsigned int cfg;
459
dma_addr_t addr;
460
461
pr_debug("%s buf:%p, fragcount:%d, fragsize:0x%lx\n",
462
__func__, buf, fragcount, fragsize);
463
464
x_count = fragsize/sport->wdsize;
465
y_count = 0;
466
467
/* for fragments larger than 64k words we use 2d dma,
468
* denote fragecount as two numbers' mutliply and both of them
469
* are less than 64k.*/
470
if (x_count >= 0x10000) {
471
int i, count = x_count;
472
473
for (i = 16; i > 0; i--) {
474
x_count = 1 << i;
475
if ((count & (x_count - 1)) == 0) {
476
y_count = count >> i;
477
if (y_count < 0x10000)
478
break;
479
}
480
}
481
if (i == 0)
482
return -EINVAL;
483
}
484
pr_debug("%s x_count:0x%x, y_count:0x%x\n", __func__,
485
x_count, y_count);
486
487
488
if (sport->dma_tx_desc) {
489
dma_free_coherent(NULL, sport->tx_desc_bytes, \
490
sport->dma_tx_desc, 0);
491
}
492
493
sport->dma_tx_desc = dma_alloc_coherent(NULL, \
494
fragcount * sizeof(struct dmasg), &addr, 0);
495
sport->tx_desc_bytes = fragcount * sizeof(struct dmasg);
496
if (!sport->dma_tx_desc) {
497
pr_err("Failed to allocate memory for tx desc\n");
498
return -ENOMEM;
499
}
500
501
sport->tx_buf = buf;
502
sport->tx_fragsize = fragsize;
503
sport->tx_frags = fragcount;
504
cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | \
505
(DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
506
507
if (y_count != 0)
508
cfg |= DMA2D;
509
510
setup_desc(sport->dma_tx_desc, buf, fragcount, fragsize,
511
cfg|DMAEN, x_count, y_count, sport->wdsize);
512
513
return 0;
514
}
515
EXPORT_SYMBOL(sport_config_tx_dma);
516
517
/* setup dummy dma descriptor ring, which don't generate interrupts,
518
* the x_modify is set to 0 */
519
static int sport_config_rx_dummy(struct sport_device *sport)
520
{
521
struct dmasg *desc;
522
unsigned config;
523
524
pr_debug("%s entered\n", __func__);
525
if (L1_DATA_A_LENGTH)
526
desc = l1_data_sram_zalloc(2 * sizeof(*desc));
527
else {
528
dma_addr_t addr;
529
desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
530
memset(desc, 0, 2 * sizeof(*desc));
531
}
532
if (desc == NULL) {
533
pr_err("Failed to allocate memory for dummy rx desc\n");
534
return -ENOMEM;
535
}
536
sport->dummy_rx_desc = desc;
537
desc->start_addr = (unsigned long)sport->dummy_buf;
538
config = DMAFLOW_LARGE | NDSIZE_9 | compute_wdsize(sport->wdsize)
539
| WNR | DMAEN;
540
desc->cfg = config;
541
desc->x_count = sport->dummy_count/sport->wdsize;
542
desc->x_modify = sport->wdsize;
543
desc->y_count = 0;
544
desc->y_modify = 0;
545
memcpy(desc+1, desc, sizeof(*desc));
546
desc->next_desc_addr = desc + 1;
547
desc[1].next_desc_addr = desc;
548
return 0;
549
}
550
551
static int sport_config_tx_dummy(struct sport_device *sport)
552
{
553
struct dmasg *desc;
554
unsigned int config;
555
556
pr_debug("%s entered\n", __func__);
557
558
if (L1_DATA_A_LENGTH)
559
desc = l1_data_sram_zalloc(2 * sizeof(*desc));
560
else {
561
dma_addr_t addr;
562
desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
563
memset(desc, 0, 2 * sizeof(*desc));
564
}
565
if (!desc) {
566
pr_err("Failed to allocate memory for dummy tx desc\n");
567
return -ENOMEM;
568
}
569
sport->dummy_tx_desc = desc;
570
desc->start_addr = (unsigned long)sport->dummy_buf + \
571
sport->dummy_count;
572
config = DMAFLOW_LARGE | NDSIZE_9 |
573
compute_wdsize(sport->wdsize) | DMAEN;
574
desc->cfg = config;
575
desc->x_count = sport->dummy_count/sport->wdsize;
576
desc->x_modify = sport->wdsize;
577
desc->y_count = 0;
578
desc->y_modify = 0;
579
memcpy(desc+1, desc, sizeof(*desc));
580
desc->next_desc_addr = desc + 1;
581
desc[1].next_desc_addr = desc;
582
return 0;
583
}
584
585
unsigned long sport_curr_offset_rx(struct sport_device *sport)
586
{
587
unsigned long curr = get_dma_curr_addr(sport->dma_rx_chan);
588
589
return (unsigned char *)curr - sport->rx_buf;
590
}
591
EXPORT_SYMBOL(sport_curr_offset_rx);
592
593
unsigned long sport_curr_offset_tx(struct sport_device *sport)
594
{
595
unsigned long curr = get_dma_curr_addr(sport->dma_tx_chan);
596
597
return (unsigned char *)curr - sport->tx_buf;
598
}
599
EXPORT_SYMBOL(sport_curr_offset_tx);
600
601
void sport_incfrag(struct sport_device *sport, int *frag, int tx)
602
{
603
++(*frag);
604
if (tx == 1 && *frag == sport->tx_frags)
605
*frag = 0;
606
607
if (tx == 0 && *frag == sport->rx_frags)
608
*frag = 0;
609
}
610
EXPORT_SYMBOL(sport_incfrag);
611
612
void sport_decfrag(struct sport_device *sport, int *frag, int tx)
613
{
614
--(*frag);
615
if (tx == 1 && *frag == 0)
616
*frag = sport->tx_frags;
617
618
if (tx == 0 && *frag == 0)
619
*frag = sport->rx_frags;
620
}
621
EXPORT_SYMBOL(sport_decfrag);
622
623
static int sport_check_status(struct sport_device *sport,
624
unsigned int *sport_stat,
625
unsigned int *rx_stat,
626
unsigned int *tx_stat)
627
{
628
int status = 0;
629
630
if (sport_stat) {
631
SSYNC();
632
status = sport->regs->stat;
633
if (status & (TOVF|TUVF|ROVF|RUVF))
634
sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
635
SSYNC();
636
*sport_stat = status;
637
}
638
639
if (rx_stat) {
640
SSYNC();
641
status = get_dma_curr_irqstat(sport->dma_rx_chan);
642
if (status & (DMA_DONE|DMA_ERR))
643
clear_dma_irqstat(sport->dma_rx_chan);
644
SSYNC();
645
*rx_stat = status;
646
}
647
648
if (tx_stat) {
649
SSYNC();
650
status = get_dma_curr_irqstat(sport->dma_tx_chan);
651
if (status & (DMA_DONE|DMA_ERR))
652
clear_dma_irqstat(sport->dma_tx_chan);
653
SSYNC();
654
*tx_stat = status;
655
}
656
657
return 0;
658
}
659
660
int sport_dump_stat(struct sport_device *sport, char *buf, size_t len)
661
{
662
int ret;
663
664
ret = snprintf(buf, len,
665
"sts: 0x%04x\n"
666
"rx dma %d sts: 0x%04x tx dma %d sts: 0x%04x\n",
667
sport->regs->stat,
668
sport->dma_rx_chan,
669
get_dma_curr_irqstat(sport->dma_rx_chan),
670
sport->dma_tx_chan,
671
get_dma_curr_irqstat(sport->dma_tx_chan));
672
buf += ret;
673
len -= ret;
674
675
ret += snprintf(buf, len,
676
"curr_rx_desc:0x%p, curr_tx_desc:0x%p\n"
677
"dma_rx_desc:0x%p, dma_tx_desc:0x%p\n"
678
"dummy_rx_desc:0x%p, dummy_tx_desc:0x%p\n",
679
sport->curr_rx_desc, sport->curr_tx_desc,
680
sport->dma_rx_desc, sport->dma_tx_desc,
681
sport->dummy_rx_desc, sport->dummy_tx_desc);
682
683
return ret;
684
}
685
686
static irqreturn_t rx_handler(int irq, void *dev_id)
687
{
688
unsigned int rx_stat;
689
struct sport_device *sport = dev_id;
690
691
pr_debug("%s enter\n", __func__);
692
sport_check_status(sport, NULL, &rx_stat, NULL);
693
if (!(rx_stat & DMA_DONE))
694
pr_err("rx dma is already stopped\n");
695
696
if (sport->rx_callback) {
697
sport->rx_callback(sport->rx_data);
698
return IRQ_HANDLED;
699
}
700
701
return IRQ_NONE;
702
}
703
704
static irqreturn_t tx_handler(int irq, void *dev_id)
705
{
706
unsigned int tx_stat;
707
struct sport_device *sport = dev_id;
708
pr_debug("%s enter\n", __func__);
709
sport_check_status(sport, NULL, NULL, &tx_stat);
710
if (!(tx_stat & DMA_DONE)) {
711
pr_err("tx dma is already stopped\n");
712
return IRQ_HANDLED;
713
}
714
if (sport->tx_callback) {
715
sport->tx_callback(sport->tx_data);
716
return IRQ_HANDLED;
717
}
718
719
return IRQ_NONE;
720
}
721
722
static irqreturn_t err_handler(int irq, void *dev_id)
723
{
724
unsigned int status = 0;
725
struct sport_device *sport = dev_id;
726
727
pr_debug("%s\n", __func__);
728
if (sport_check_status(sport, &status, NULL, NULL)) {
729
pr_err("error checking status ??");
730
return IRQ_NONE;
731
}
732
733
if (status & (TOVF|TUVF|ROVF|RUVF)) {
734
pr_info("sport status error:%s%s%s%s\n",
735
status & TOVF ? " TOVF" : "",
736
status & TUVF ? " TUVF" : "",
737
status & ROVF ? " ROVF" : "",
738
status & RUVF ? " RUVF" : "");
739
if (status & TOVF || status & TUVF) {
740
disable_dma(sport->dma_tx_chan);
741
if (sport->tx_run)
742
sport_tx_dma_start(sport, 0);
743
else
744
sport_tx_dma_start(sport, 1);
745
enable_dma(sport->dma_tx_chan);
746
} else {
747
disable_dma(sport->dma_rx_chan);
748
if (sport->rx_run)
749
sport_rx_dma_start(sport, 0);
750
else
751
sport_rx_dma_start(sport, 1);
752
enable_dma(sport->dma_rx_chan);
753
}
754
}
755
status = sport->regs->stat;
756
if (status & (TOVF|TUVF|ROVF|RUVF))
757
sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
758
SSYNC();
759
760
if (sport->err_callback)
761
sport->err_callback(sport->err_data);
762
763
return IRQ_HANDLED;
764
}
765
766
int sport_set_rx_callback(struct sport_device *sport,
767
void (*rx_callback)(void *), void *rx_data)
768
{
769
BUG_ON(rx_callback == NULL);
770
sport->rx_callback = rx_callback;
771
sport->rx_data = rx_data;
772
773
return 0;
774
}
775
EXPORT_SYMBOL(sport_set_rx_callback);
776
777
int sport_set_tx_callback(struct sport_device *sport,
778
void (*tx_callback)(void *), void *tx_data)
779
{
780
BUG_ON(tx_callback == NULL);
781
sport->tx_callback = tx_callback;
782
sport->tx_data = tx_data;
783
784
return 0;
785
}
786
EXPORT_SYMBOL(sport_set_tx_callback);
787
788
int sport_set_err_callback(struct sport_device *sport,
789
void (*err_callback)(void *), void *err_data)
790
{
791
BUG_ON(err_callback == NULL);
792
sport->err_callback = err_callback;
793
sport->err_data = err_data;
794
795
return 0;
796
}
797
EXPORT_SYMBOL(sport_set_err_callback);
798
799
static int sport_config_pdev(struct platform_device *pdev, struct sport_param *param)
800
{
801
/* Extract settings from platform data */
802
struct device *dev = &pdev->dev;
803
struct bfin_snd_platform_data *pdata = dev->platform_data;
804
struct resource *res;
805
806
param->num = pdev->id;
807
808
if (!pdata) {
809
dev_err(dev, "no platform_data\n");
810
return -ENODEV;
811
}
812
param->pin_req = pdata->pin_req;
813
814
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815
if (!res) {
816
dev_err(dev, "no MEM resource\n");
817
return -ENODEV;
818
}
819
param->regs = (struct sport_register *)res->start;
820
821
/* first RX, then TX */
822
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
823
if (!res) {
824
dev_err(dev, "no rx DMA resource\n");
825
return -ENODEV;
826
}
827
param->dma_rx_chan = res->start;
828
829
res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
830
if (!res) {
831
dev_err(dev, "no tx DMA resource\n");
832
return -ENODEV;
833
}
834
param->dma_tx_chan = res->start;
835
836
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
837
if (!res) {
838
dev_err(dev, "no irq resource\n");
839
return -ENODEV;
840
}
841
param->err_irq = res->start;
842
843
return 0;
844
}
845
846
struct sport_device *sport_init(struct platform_device *pdev,
847
unsigned int wdsize, unsigned int dummy_count, size_t priv_size)
848
{
849
struct device *dev = &pdev->dev;
850
struct sport_param param;
851
struct sport_device *sport;
852
int ret;
853
854
dev_dbg(dev, "%s enter\n", __func__);
855
856
param.wdsize = wdsize;
857
param.dummy_count = dummy_count;
858
BUG_ON(param.wdsize == 0 || param.dummy_count == 0);
859
860
ret = sport_config_pdev(pdev, &param);
861
if (ret)
862
return NULL;
863
864
if (peripheral_request_list(param.pin_req, "soc-audio")) {
865
dev_err(dev, "requesting Peripherals failed\n");
866
return NULL;
867
}
868
869
sport = kzalloc(sizeof(*sport), GFP_KERNEL);
870
if (!sport) {
871
dev_err(dev, "failed to allocate for sport device\n");
872
goto __init_err0;
873
}
874
875
sport->num = param.num;
876
sport->dma_rx_chan = param.dma_rx_chan;
877
sport->dma_tx_chan = param.dma_tx_chan;
878
sport->err_irq = param.err_irq;
879
sport->regs = param.regs;
880
sport->pin_req = param.pin_req;
881
882
if (request_dma(sport->dma_rx_chan, "SPORT RX Data") == -EBUSY) {
883
dev_err(dev, "failed to request RX dma %d\n", sport->dma_rx_chan);
884
goto __init_err1;
885
}
886
if (set_dma_callback(sport->dma_rx_chan, rx_handler, sport) != 0) {
887
dev_err(dev, "failed to request RX irq %d\n", sport->dma_rx_chan);
888
goto __init_err2;
889
}
890
891
if (request_dma(sport->dma_tx_chan, "SPORT TX Data") == -EBUSY) {
892
dev_err(dev, "failed to request TX dma %d\n", sport->dma_tx_chan);
893
goto __init_err2;
894
}
895
896
if (set_dma_callback(sport->dma_tx_chan, tx_handler, sport) != 0) {
897
dev_err(dev, "failed to request TX irq %d\n", sport->dma_tx_chan);
898
goto __init_err3;
899
}
900
901
if (request_irq(sport->err_irq, err_handler, IRQF_SHARED, "SPORT err",
902
sport) < 0) {
903
dev_err(dev, "failed to request err irq %d\n", sport->err_irq);
904
goto __init_err3;
905
}
906
907
dev_info(dev, "dma rx:%d tx:%d, err irq:%d, regs:%p\n",
908
sport->dma_rx_chan, sport->dma_tx_chan,
909
sport->err_irq, sport->regs);
910
911
sport->wdsize = param.wdsize;
912
sport->dummy_count = param.dummy_count;
913
914
sport->private_data = kzalloc(priv_size, GFP_KERNEL);
915
if (!sport->private_data) {
916
dev_err(dev, "could not alloc priv data %zu bytes\n", priv_size);
917
goto __init_err4;
918
}
919
920
if (L1_DATA_A_LENGTH)
921
sport->dummy_buf = l1_data_sram_zalloc(param.dummy_count * 2);
922
else
923
sport->dummy_buf = kzalloc(param.dummy_count * 2, GFP_KERNEL);
924
if (sport->dummy_buf == NULL) {
925
dev_err(dev, "failed to allocate dummy buffer\n");
926
goto __error1;
927
}
928
929
ret = sport_config_rx_dummy(sport);
930
if (ret) {
931
dev_err(dev, "failed to config rx dummy ring\n");
932
goto __error2;
933
}
934
ret = sport_config_tx_dummy(sport);
935
if (ret) {
936
dev_err(dev, "failed to config tx dummy ring\n");
937
goto __error3;
938
}
939
940
platform_set_drvdata(pdev, sport);
941
942
return sport;
943
__error3:
944
if (L1_DATA_A_LENGTH)
945
l1_data_sram_free(sport->dummy_rx_desc);
946
else
947
dma_free_coherent(NULL, 2*sizeof(struct dmasg),
948
sport->dummy_rx_desc, 0);
949
__error2:
950
if (L1_DATA_A_LENGTH)
951
l1_data_sram_free(sport->dummy_buf);
952
else
953
kfree(sport->dummy_buf);
954
__error1:
955
kfree(sport->private_data);
956
__init_err4:
957
free_irq(sport->err_irq, sport);
958
__init_err3:
959
free_dma(sport->dma_tx_chan);
960
__init_err2:
961
free_dma(sport->dma_rx_chan);
962
__init_err1:
963
kfree(sport);
964
__init_err0:
965
peripheral_free_list(param.pin_req);
966
return NULL;
967
}
968
EXPORT_SYMBOL(sport_init);
969
970
void sport_done(struct sport_device *sport)
971
{
972
if (sport == NULL)
973
return;
974
975
sport_stop(sport);
976
if (sport->dma_rx_desc)
977
dma_free_coherent(NULL, sport->rx_desc_bytes,
978
sport->dma_rx_desc, 0);
979
if (sport->dma_tx_desc)
980
dma_free_coherent(NULL, sport->tx_desc_bytes,
981
sport->dma_tx_desc, 0);
982
983
#if L1_DATA_A_LENGTH != 0
984
l1_data_sram_free(sport->dummy_rx_desc);
985
l1_data_sram_free(sport->dummy_tx_desc);
986
l1_data_sram_free(sport->dummy_buf);
987
#else
988
dma_free_coherent(NULL, 2*sizeof(struct dmasg),
989
sport->dummy_rx_desc, 0);
990
dma_free_coherent(NULL, 2*sizeof(struct dmasg),
991
sport->dummy_tx_desc, 0);
992
kfree(sport->dummy_buf);
993
#endif
994
free_dma(sport->dma_rx_chan);
995
free_dma(sport->dma_tx_chan);
996
free_irq(sport->err_irq, sport);
997
998
kfree(sport->private_data);
999
peripheral_free_list(sport->pin_req);
1000
kfree(sport);
1001
}
1002
EXPORT_SYMBOL(sport_done);
1003
1004
/*
1005
* It is only used to send several bytes when dma is not enabled
1006
* sport controller is configured but not enabled.
1007
* Multichannel cannot works with pio mode */
1008
/* Used by ac97 to write and read codec register */
1009
int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \
1010
u8 *in_data, int len)
1011
{
1012
unsigned short dma_config;
1013
unsigned short status;
1014
unsigned long flags;
1015
unsigned long wait = 0;
1016
1017
pr_debug("%s enter, out_data:%p, in_data:%p len:%d\n", \
1018
__func__, out_data, in_data, len);
1019
pr_debug("tcr1:0x%04x, tcr2:0x%04x, tclkdiv:0x%04x, tfsdiv:0x%04x\n"
1020
"mcmc1:0x%04x, mcmc2:0x%04x\n",
1021
sport->regs->tcr1, sport->regs->tcr2,
1022
sport->regs->tclkdiv, sport->regs->tfsdiv,
1023
sport->regs->mcmc1, sport->regs->mcmc2);
1024
flush_dcache_range((unsigned)out_data, (unsigned)(out_data + len));
1025
1026
/* Enable tx dma */
1027
dma_config = (RESTART | WDSIZE_16 | DI_EN);
1028
set_dma_start_addr(sport->dma_tx_chan, (unsigned long)out_data);
1029
set_dma_x_count(sport->dma_tx_chan, len/2);
1030
set_dma_x_modify(sport->dma_tx_chan, 2);
1031
set_dma_config(sport->dma_tx_chan, dma_config);
1032
enable_dma(sport->dma_tx_chan);
1033
1034
if (in_data != NULL) {
1035
invalidate_dcache_range((unsigned)in_data, \
1036
(unsigned)(in_data + len));
1037
/* Enable rx dma */
1038
dma_config = (RESTART | WDSIZE_16 | WNR | DI_EN);
1039
set_dma_start_addr(sport->dma_rx_chan, (unsigned long)in_data);
1040
set_dma_x_count(sport->dma_rx_chan, len/2);
1041
set_dma_x_modify(sport->dma_rx_chan, 2);
1042
set_dma_config(sport->dma_rx_chan, dma_config);
1043
enable_dma(sport->dma_rx_chan);
1044
}
1045
1046
local_irq_save(flags);
1047
sport->regs->tcr1 |= TSPEN;
1048
sport->regs->rcr1 |= RSPEN;
1049
SSYNC();
1050
1051
status = get_dma_curr_irqstat(sport->dma_tx_chan);
1052
while (status & DMA_RUN) {
1053
udelay(1);
1054
status = get_dma_curr_irqstat(sport->dma_tx_chan);
1055
pr_debug("DMA status:0x%04x\n", status);
1056
if (wait++ > 100)
1057
goto __over;
1058
}
1059
status = sport->regs->stat;
1060
wait = 0;
1061
1062
while (!(status & TXHRE)) {
1063
pr_debug("sport status:0x%04x\n", status);
1064
udelay(1);
1065
status = *(unsigned short *)&sport->regs->stat;
1066
if (wait++ > 1000)
1067
goto __over;
1068
}
1069
/* Wait for the last byte sent out */
1070
udelay(20);
1071
pr_debug("sport status:0x%04x\n", status);
1072
1073
__over:
1074
sport->regs->tcr1 &= ~TSPEN;
1075
sport->regs->rcr1 &= ~RSPEN;
1076
SSYNC();
1077
disable_dma(sport->dma_tx_chan);
1078
/* Clear the status */
1079
clear_dma_irqstat(sport->dma_tx_chan);
1080
if (in_data != NULL) {
1081
disable_dma(sport->dma_rx_chan);
1082
clear_dma_irqstat(sport->dma_rx_chan);
1083
}
1084
SSYNC();
1085
local_irq_restore(flags);
1086
1087
return 0;
1088
}
1089
EXPORT_SYMBOL(sport_send_and_recv);
1090
1091
MODULE_AUTHOR("Roy Huang");
1092
MODULE_DESCRIPTION("SPORT driver for ADI Blackfin");
1093
MODULE_LICENSE("GPL");
1094
1095