Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
bytecodealliance
GitHub Repository: bytecodealliance/wasmtime
Path: blob/main/cranelift/assembler-x64/meta/src/instructions/bitmanip.rs
1693 views
1
use crate::dsl::{Eflags::*, Feature::*, Inst, Length::*, Location::*, TupleType::*};
2
use crate::dsl::{evex, fmt, implicit, inst, r, rex, rw, vex, w};
3
4
#[rustfmt::skip] // Keeps instructions on a single line.
5
pub fn list() -> Vec<Inst> {
6
vec![
7
inst("bsfw", fmt("RM", [w(r16), r(rm16)]), rex([0x66, 0x0F, 0xBC]).r(), _64b | compat),
8
inst("bsfl", fmt("RM", [w(r32), r(rm32)]), rex([0x0F, 0xBC]).r(), _64b | compat),
9
inst("bsfq", fmt("RM", [w(r64), r(rm64)]), rex([0x0F, 0xBC]).r().w(), _64b),
10
11
inst("bsrw", fmt("RM", [w(r16), r(rm16)]), rex([0x66, 0x0F, 0xBD]).r(), _64b | compat),
12
inst("bsrl", fmt("RM", [w(r32), r(rm32)]), rex([0x0F, 0xBD]).r(), _64b | compat),
13
inst("bsrq", fmt("RM", [w(r64), r(rm64)]), rex([0x0F, 0xBD]).r().w(), _64b),
14
15
inst("tzcntw", fmt("A", [w(r16), r(rm16)]), rex([0x66, 0xF3, 0x0F, 0xBC]).r(), (_64b | compat) & bmi1),
16
inst("tzcntl", fmt("A", [w(r32), r(rm32)]), rex([0xF3, 0x0F, 0xBC]).r(), (_64b | compat) & bmi1),
17
inst("tzcntq", fmt("A", [w(r64), r(rm64)]), rex([0xF3, 0x0F, 0xBC]).r().w(), _64b & bmi1),
18
19
inst("lzcntw", fmt("RM", [w(r16), r(rm16)]), rex([0x66, 0xF3, 0x0F, 0xBD]).r(), (_64b | compat) & lzcnt),
20
inst("lzcntl", fmt("RM", [w(r32), r(rm32)]), rex([0xF3, 0x0F, 0xBD]).r(), (_64b | compat) & lzcnt),
21
inst("lzcntq", fmt("RM", [w(r64), r(rm64)]), rex([0xF3, 0x0F, 0xBD]).r().w(), _64b & lzcnt),
22
23
inst("popcntw", fmt("RM", [w(r16), r(rm16)]), rex([0x66, 0xF3, 0x0F, 0xB8]).r(), (_64b | compat) & popcnt),
24
inst("popcntl", fmt("RM", [w(r32), r(rm32)]), rex([0xF3, 0x0F, 0xB8]).r(), (_64b | compat) & popcnt),
25
inst("popcntq", fmt("RM", [w(r64), r(rm64)]), rex([0xF3, 0x0F, 0xB8]).r().w(), _64b & popcnt),
26
27
inst("btw", fmt("MR", [r(rm16), r(r16)]).flags(W), rex([0x66, 0x0F, 0xA3]).r(), _64b | compat),
28
inst("btl", fmt("MR", [r(rm32), r(r32)]).flags(W), rex([0x0F, 0xA3]).r(), _64b | compat),
29
inst("btq", fmt("MR", [r(rm64), r(r64)]).flags(W), rex([0x0F, 0xA3]).w().r(), _64b),
30
inst("btw", fmt("MI", [r(rm16), r(imm8)]).flags(W), rex([0x66, 0x0F, 0xBA]).digit(4).ib(), _64b | compat),
31
inst("btl", fmt("MI", [r(rm32), r(imm8)]).flags(W), rex([0x0F, 0xBA]).digit(4).ib(), _64b | compat),
32
inst("btq", fmt("MI", [r(rm64), r(imm8)]).flags(W), rex([0x0F, 0xBA]).w().digit(4).ib(), _64b),
33
34
// Note that the Intel manual calls has different names for these
35
// instructions than Capstone gives them:
36
//
37
// * cbtw => cbw
38
// * cwtl => cwde
39
// * cltq => cwqe
40
// * cwtd => cwd
41
// * cltd => cdq
42
// * cqto => cqo
43
inst("cbtw", fmt("ZO", [rw(implicit(ax))]), rex([0x66, 0x98]), _64b | compat),
44
inst("cwtl", fmt("ZO", [rw(implicit(eax))]), rex([0x98]), _64b | compat),
45
inst("cltq", fmt("ZO", [rw(implicit(rax))]), rex([0x98]).w(), _64b),
46
inst("cwtd", fmt("ZO", [w(implicit(dx)), r(implicit(ax))]), rex([0x66, 0x99]), _64b | compat),
47
inst("cltd", fmt("ZO", [w(implicit(edx)), r(implicit(eax))]), rex([0x99]), _64b | compat),
48
inst("cqto", fmt("ZO", [w(implicit(rdx)), r(implicit(rax))]), rex([0x99]).w(), _64b),
49
50
inst("bswapl", fmt("O", [rw(r32)]), rex([0x0F, 0xC8]).rd(), _64b | compat),
51
inst("bswapq", fmt("O", [rw(r64)]), rex([0x0F, 0xC8]).w().ro(), _64b),
52
53
// BMI1 instructions
54
inst("blsrl", fmt("VM", [w(r32), r(rm32)]), vex(LZ)._0f38().w0().op(0xF3).digit(1), (_64b | compat) & bmi1),
55
inst("blsrq", fmt("VM", [w(r64), r(rm64)]), vex(LZ)._0f38().w1().op(0xF3).digit(1), _64b & bmi1),
56
inst("blsmskl", fmt("VM", [w(r32), r(rm32)]), vex(LZ)._0f38().w0().op(0xF3).digit(2), (_64b | compat) & bmi1),
57
inst("blsmskq", fmt("VM", [w(r64), r(rm64)]), vex(LZ)._0f38().w1().op(0xF3).digit(2), _64b & bmi1),
58
inst("blsil", fmt("VM", [w(r32), r(rm32)]), vex(LZ)._0f38().w0().op(0xF3).digit(3), (_64b | compat) & bmi1),
59
inst("blsiq", fmt("VM", [w(r64), r(rm64)]), vex(LZ)._0f38().w1().op(0xF3).digit(3), (_64b | compat) & bmi1),
60
61
// BMI2 instructions
62
inst("bzhil", fmt("RMV", [w(r32a), r(rm32), r(r32b)]), vex(LZ)._0f38().w0().op(0xF5), (_64b | compat) & bmi2),
63
inst("bzhiq", fmt("RMV", [w(r64a), r(rm64), r(r64b)]), vex(LZ)._0f38().w1().op(0xF5), _64b & bmi2),
64
65
inst("vpopcntb", fmt("A", [w(xmm1), r(xmm_m128)]), evex(L128, FullMem)._66()._0f38().w0().op(0x54).r(), (_64b | compat) & avx512vl & avx512bitalg),
66
inst("vpopcntw", fmt("A", [w(xmm1), r(xmm_m128)]), evex(L128, FullMem)._66()._0f38().w1().op(0x54).r(), (_64b | compat) & avx512vl & avx512bitalg),
67
// FIXME: uncomment when avx512vpopcntdq is bound in cranelift
68
// inst("vpopcntd", fmt("A", [w(xmm1), r(xmm_m128)]), evex(L128, Full)._66()._0f38().w0().op(0x55).r(), (_64b | compat) & avx512vl & avx512vpopcntdq),
69
// inst("vpopcntq", fmt("A", [w(xmm1), r(xmm_m128)]), evex(L128, Full)._66()._0f38().w1().op(0x55).r(), (_64b | compat) & avx512vl & avx512vpopcntdq),
70
]
71
}
72
73