Path: blob/main/cranelift/codegen/meta/src/isa/x86.rs
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use crate::cdsl::isa::TargetIsa;1use crate::cdsl::settings::SettingGroupBuilder;23pub(crate) fn define() -> TargetIsa {4let mut settings = SettingGroupBuilder::new("x86");56// CPUID.01H:ECX7let has_sse3 = settings.add_bool(8"has_sse3",9"Has support for SSE3.",10"SSE3: CPUID.01H:ECX.SSE3[bit 0]",11false,12);13let has_ssse3 = settings.add_bool(14"has_ssse3",15"Has support for SSSE3.",16"SSSE3: CPUID.01H:ECX.SSSE3[bit 9]",17false,18);19let has_cmpxchg16b = settings.add_bool(20"has_cmpxchg16b",21"Has support for CMPXCHG16b.",22"CMPXCHG16b: CPUID.01H:ECX.CMPXCHG16B[bit 13]",23false,24);25let has_sse41 = settings.add_bool(26"has_sse41",27"Has support for SSE4.1.",28"SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]",29false,30);31let has_sse42 = settings.add_bool(32"has_sse42",33"Has support for SSE4.2.",34"SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]",35false,36);37let has_avx = settings.add_bool(38"has_avx",39"Has support for AVX.",40"AVX: CPUID.01H:ECX.AVX[bit 28]",41false,42);43let has_avx2 = settings.add_bool(44"has_avx2",45"Has support for AVX2.",46"AVX2: CPUID.07H:EBX.AVX2[bit 5]",47false,48);49let has_fma = settings.add_bool(50"has_fma",51"Has support for FMA.",52"FMA: CPUID.01H:ECX.FMA[bit 12]",53false,54);55let has_avx512bitalg = settings.add_bool(56"has_avx512bitalg",57"Has support for AVX512BITALG.",58"AVX512BITALG: CPUID.07H:ECX.AVX512BITALG[bit 12]",59false,60);61let has_avx512dq = settings.add_bool(62"has_avx512dq",63"Has support for AVX512DQ.",64"AVX512DQ: CPUID.07H:EBX.AVX512DQ[bit 17]",65false,66);67let has_avx512vl = settings.add_bool(68"has_avx512vl",69"Has support for AVX512VL.",70"AVX512VL: CPUID.07H:EBX.AVX512VL[bit 31]",71false,72);73let has_avx512vbmi = settings.add_bool(74"has_avx512vbmi",75"Has support for AVX512VMBI.",76"AVX512VBMI: CPUID.07H:ECX.AVX512VBMI[bit 1]",77false,78);79let has_avx512f = settings.add_bool(80"has_avx512f",81"Has support for AVX512F.",82"AVX512F: CPUID.07H:EBX.AVX512F[bit 16]",83false,84);85let has_popcnt = settings.add_bool(86"has_popcnt",87"Has support for POPCNT.",88"POPCNT: CPUID.01H:ECX.POPCNT[bit 23]",89false,90);9192// CPUID.(EAX=07H, ECX=0H):EBX93let has_bmi1 = settings.add_bool(94"has_bmi1",95"Has support for BMI1.",96"BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",97false,98);99let has_bmi2 = settings.add_bool(100"has_bmi2",101"Has support for BMI2.",102"BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",103false,104);105106// CPUID.EAX=80000001H:ECX107let has_lzcnt = settings.add_bool(108"has_lzcnt",109"Has support for LZCNT.",110"LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",111false,112);113114let sse3 = settings.add_preset("sse3", "SSE3 and earlier.", preset!(has_sse3));115let ssse3 = settings.add_preset("ssse3", "SSSE3 and earlier.", preset!(sse3 && has_ssse3));116let sse41 = settings.add_preset("sse41", "SSE4.1 and earlier.", preset!(ssse3 && has_sse41));117let sse42 = settings.add_preset("sse42", "SSE4.2 and earlier.", preset!(sse41 && has_sse42));118119// Presets corresponding to x86 CPUs.120// Features and architecture names are from LLVM's x86 presets:121// https://github.com/llvm/llvm-project/blob/d4493dd1ed58ac3f1eab0c4ca6e363e2b15bfd1c/llvm/lib/Target/X86/X86.td#L1300-L1643122settings.add_preset(123"baseline",124"A baseline preset with no extensions enabled.",125preset!(),126);127128// Intel CPUs129130// Netburst131settings.add_preset(132"nocona",133"Nocona microarchitecture.",134preset!(sse3 && has_cmpxchg16b),135);136137// Intel Core 2 Solo/Duo138settings.add_preset(139"core2",140"Core 2 microarchitecture.",141preset!(sse3 && has_cmpxchg16b),142);143settings.add_preset(144"penryn",145"Penryn microarchitecture.",146preset!(sse41 && has_cmpxchg16b),147);148149// Intel Atom CPUs150let atom = settings.add_preset(151"atom",152"Atom microarchitecture.",153preset!(ssse3 && has_cmpxchg16b),154);155settings.add_preset("bonnell", "Bonnell microarchitecture.", preset!(atom));156let silvermont = settings.add_preset(157"silvermont",158"Silvermont microarchitecture.",159preset!(atom && sse42 && has_popcnt),160);161settings.add_preset("slm", "Silvermont microarchitecture.", preset!(silvermont));162let goldmont = settings.add_preset(163"goldmont",164"Goldmont microarchitecture.",165preset!(silvermont),166);167settings.add_preset(168"goldmont-plus",169"Goldmont Plus microarchitecture.",170preset!(goldmont),171);172let tremont = settings.add_preset("tremont", "Tremont microarchitecture.", preset!(goldmont));173174let alderlake = settings.add_preset(175"alderlake",176"Alderlake microarchitecture.",177preset!(tremont && has_bmi1 && has_bmi2 && has_lzcnt && has_fma),178);179let sierra_forest = settings.add_preset(180"sierraforest",181"Sierra Forest microarchitecture.",182preset!(alderlake),183);184settings.add_preset(185"grandridge",186"Grandridge microarchitecture.",187preset!(sierra_forest),188);189let nehalem = settings.add_preset(190"nehalem",191"Nehalem microarchitecture.",192preset!(sse42 && has_popcnt && has_cmpxchg16b),193);194settings.add_preset("corei7", "Core i7 microarchitecture.", preset!(nehalem));195let westmere = settings.add_preset("westmere", "Westmere microarchitecture.", preset!(nehalem));196let sandy_bridge = settings.add_preset(197"sandybridge",198"Sandy Bridge microarchitecture.",199preset!(westmere && has_avx),200);201settings.add_preset(202"corei7-avx",203"Core i7 AVX microarchitecture.",204preset!(sandy_bridge),205);206let ivy_bridge = settings.add_preset(207"ivybridge",208"Ivy Bridge microarchitecture.",209preset!(sandy_bridge),210);211settings.add_preset(212"core-avx-i",213"Intel Core CPU with 64-bit extensions.",214preset!(ivy_bridge),215);216let haswell = settings.add_preset(217"haswell",218"Haswell microarchitecture.",219preset!(ivy_bridge && has_avx2 && has_bmi1 && has_bmi2 && has_fma && has_lzcnt),220);221settings.add_preset(222"core-avx2",223"Intel Core CPU with AVX2 extensions.",224preset!(haswell),225);226let broadwell = settings.add_preset(227"broadwell",228"Broadwell microarchitecture.",229preset!(haswell),230);231let skylake = settings.add_preset("skylake", "Skylake microarchitecture.", preset!(broadwell));232let knights_landing = settings.add_preset(233"knl",234"Knights Landing microarchitecture.",235preset!(236has_popcnt237&& has_avx512f238&& has_fma239&& has_bmi1240&& has_bmi2241&& has_lzcnt242&& has_cmpxchg16b243),244);245settings.add_preset(246"knm",247"Knights Mill microarchitecture.",248preset!(knights_landing),249);250let skylake_avx512 = settings.add_preset(251"skylake-avx512",252"Skylake AVX512 microarchitecture.",253preset!(broadwell && has_avx512f && has_avx512dq && has_avx512vl),254);255settings.add_preset(256"skx",257"Skylake AVX512 microarchitecture.",258preset!(skylake_avx512),259);260let cascadelake = settings.add_preset(261"cascadelake",262"Cascade Lake microarchitecture.",263preset!(skylake_avx512),264);265settings.add_preset(266"cooperlake",267"Cooper Lake microarchitecture.",268preset!(cascadelake),269);270let cannonlake = settings.add_preset(271"cannonlake",272"Canon Lake microarchitecture.",273preset!(skylake && has_avx512f && has_avx512dq && has_avx512vl && has_avx512vbmi),274);275let icelake_client = settings.add_preset(276"icelake-client",277"Ice Lake microarchitecture.",278preset!(cannonlake && has_avx512bitalg),279);280// LLVM doesn't use the name "icelake" but Cranelift did in the past; alias it281settings.add_preset(282"icelake",283"Ice Lake microarchitecture",284preset!(icelake_client),285);286let icelake_server = settings.add_preset(287"icelake-server",288"Ice Lake (server) microarchitecture.",289preset!(icelake_client),290);291settings.add_preset(292"tigerlake",293"Tiger Lake microarchitecture.",294preset!(icelake_client),295);296let sapphire_rapids = settings.add_preset(297"sapphirerapids",298"Sapphire Rapids microarchitecture.",299preset!(icelake_server),300);301settings.add_preset(302"raptorlake",303"Raptor Lake microarchitecture.",304preset!(alderlake),305);306settings.add_preset(307"meteorlake",308"Meteor Lake microarchitecture.",309preset!(alderlake),310);311settings.add_preset(312"graniterapids",313"Granite Rapids microarchitecture.",314preset!(sapphire_rapids),315);316317// AMD CPUs318319settings.add_preset("opteron", "Opteron microarchitecture.", preset!());320settings.add_preset("k8", "K8 Hammer microarchitecture.", preset!());321settings.add_preset("athlon64", "Athlon64 microarchitecture.", preset!());322settings.add_preset("athlon-fx", "Athlon FX microarchitecture.", preset!());323settings.add_preset(324"opteron-sse3",325"Opteron microarchitecture with support for SSE3 instructions.",326preset!(sse3 && has_cmpxchg16b),327);328settings.add_preset(329"k8-sse3",330"K8 Hammer microarchitecture with support for SSE3 instructions.",331preset!(sse3 && has_cmpxchg16b),332);333settings.add_preset(334"athlon64-sse3",335"Athlon 64 microarchitecture with support for SSE3 instructions.",336preset!(sse3 && has_cmpxchg16b),337);338let barcelona = settings.add_preset(339"barcelona",340"Barcelona microarchitecture.",341preset!(has_popcnt && has_lzcnt && has_cmpxchg16b),342);343settings.add_preset(344"amdfam10",345"AMD Family 10h microarchitecture",346preset!(barcelona),347);348349let btver1 = settings.add_preset(350"btver1",351"Bobcat microarchitecture.",352preset!(ssse3 && has_lzcnt && has_popcnt && has_cmpxchg16b),353);354settings.add_preset(355"btver2",356"Jaguar microarchitecture.",357preset!(btver1 && has_avx && has_bmi1),358);359360let bdver1 = settings.add_preset(361"bdver1",362"Bulldozer microarchitecture",363preset!(has_lzcnt && has_popcnt && ssse3 && has_cmpxchg16b),364);365let bdver2 = settings.add_preset(366"bdver2",367"Piledriver microarchitecture.",368preset!(bdver1 && has_bmi1),369);370let bdver3 = settings.add_preset("bdver3", "Steamroller microarchitecture.", preset!(bdver2));371settings.add_preset(372"bdver4",373"Excavator microarchitecture.",374preset!(bdver3 && has_avx2 && has_bmi2),375);376377let znver1 = settings.add_preset(378"znver1",379"Zen (first generation) microarchitecture.",380preset!(381sse42 && has_popcnt && has_bmi1 && has_bmi2 && has_lzcnt && has_fma && has_cmpxchg16b382),383);384let znver2 = settings.add_preset(385"znver2",386"Zen (second generation) microarchitecture.",387preset!(znver1),388);389let znver3 = settings.add_preset(390"znver3",391"Zen (third generation) microarchitecture.",392preset!(znver2),393);394settings.add_preset(395"znver4",396"Zen (fourth generation) microarchitecture.",397preset!(398znver3399&& has_avx512bitalg400&& has_avx512dq401&& has_avx512f402&& has_avx512vbmi403&& has_avx512vl404),405);406407// Generic408409settings.add_preset("x86_64", "Generic x86-64 microarchitecture.", preset!());410let x86_64_v2 = settings.add_preset(411"x86_64_v2",412"Generic x86-64 (V2) microarchitecture.",413preset!(sse42 && has_popcnt && has_cmpxchg16b),414);415let x86_64_v3 = settings.add_preset(416"x86_64_v3",417"Generic x86-64 (V3) microarchitecture.",418preset!(x86_64_v2 && has_bmi1 && has_bmi2 && has_fma && has_lzcnt && has_avx2),419);420settings.add_preset(421"x86_64_v4",422"Generic x86-64 (V4) microarchitecture.",423preset!(x86_64_v3 && has_avx512dq && has_avx512vl),424);425426TargetIsa::new("x86", settings.build())427}428429430