CoCalc -- emit

GitHub Repository: bytecodealliance/wasmtime
Path: blob/main/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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1
use crate::ir::types::*;
2
use crate::ir::{ExternalName, TrapCode};
3
use crate::isa::aarch64::inst::*;
4

5
use alloc::boxed::Box;
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7
#[cfg(test)]
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fn simm9_zero() -> SImm9 {
9
    SImm9::maybe_from_i64(0).unwrap()
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}
11

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#[cfg(test)]
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fn simm7_scaled_zero(scale_ty: Type) -> SImm7Scaled {
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    SImm7Scaled::maybe_from_i64(0, scale_ty).unwrap()
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}
16

17
#[test]
18
fn test_aarch64_binemit() {
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    let mut insns = Vec::<(Inst, &str, &str)>::new();
20

21
    // N.B.: the architecture is little-endian, so when transcribing the 32-bit
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    // hex instructions from e.g. objdump disassembly, one must swap the bytes
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    // seen below. (E.g., a `ret` is normally written as the u32 `D65F03C0`,
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    // but we write it here as C0035FD6.)
25

26
    // Useful helper script to produce the encodings from the text:
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    //
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    //      #!/bin/sh
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    //      tmp=`mktemp /tmp/XXXXXXXX.o`
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    //      aarch64-linux-gnu-as /dev/stdin -o $tmp
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    //      aarch64-linux-gnu-objdump -d $tmp
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    //      rm -f $tmp
33
    //
34
    // Then:
35
    //
36
    //      $ echo "mov x1, x2" | aarch64inst.sh
37
    insns.push((Inst::Ret {}, "C0035FD6", "ret"));
38
    insns.push((
39
        Inst::AuthenticatedRet {
40
            key: APIKey::ASP,
41
            is_hint: true,
42
        },
43
        "BF2303D5C0035FD6",
44
        "autiasp ; ret",
45
    ));
46
    insns.push((
47
        Inst::AuthenticatedRet {
48
            key: APIKey::BSP,
49
            is_hint: false,
50
        },
51
        "FF0F5FD6",
52
        "retabsp",
53
    ));
54
    insns.push((Inst::Paci { key: APIKey::BSP }, "7F2303D5", "pacibsp"));
55
    insns.push((Inst::Xpaclri, "FF2003D5", "xpaclri"));
56
    insns.push((
57
        Inst::Bti {
58
            targets: BranchTargetType::J,
59
        },
60
        "9F2403D5",
61
        "bti j",
62
    ));
63
    insns.push((Inst::Nop0, "", "nop-zero-len"));
64
    insns.push((Inst::Nop4, "1F2003D5", "nop"));
65
    insns.push((Inst::Csdb, "9F2203D5", "csdb"));
66
    insns.push((
67
        Inst::Udf {
68
            trap_code: TrapCode::STACK_OVERFLOW,
69
        },
70
        "1FC10000",
71
        "udf #0xc11f",
72
    ));
73
    insns.push((
74
        Inst::AluRRR {
75
            alu_op: ALUOp::Add,
76
            size: OperandSize::Size32,
77
            rd: writable_xreg(1),
78
            rn: xreg(2),
79
            rm: xreg(3),
80
        },
81
        "4100030B",
82
        "add w1, w2, w3",
83
    ));
84
    insns.push((
85
        Inst::AluRRR {
86
            alu_op: ALUOp::Add,
87
            size: OperandSize::Size64,
88
            rd: writable_xreg(4),
89
            rn: xreg(5),
90
            rm: xreg(6),
91
        },
92
        "A400068B",
93
        "add x4, x5, x6",
94
    ));
95
    insns.push((
96
        Inst::AluRRR {
97
            alu_op: ALUOp::Adc,
98
            size: OperandSize::Size32,
99
            rd: writable_xreg(1),
100
            rn: xreg(2),
101
            rm: xreg(3),
102
        },
103
        "4100031A",
104
        "adc w1, w2, w3",
105
    ));
106
    insns.push((
107
        Inst::AluRRR {
108
            alu_op: ALUOp::Adc,
109
            size: OperandSize::Size64,
110
            rd: writable_xreg(4),
111
            rn: xreg(5),
112
            rm: xreg(6),
113
        },
114
        "A400069A",
115
        "adc x4, x5, x6",
116
    ));
117
    insns.push((
118
        Inst::AluRRR {
119
            alu_op: ALUOp::AdcS,
120
            size: OperandSize::Size32,
121
            rd: writable_xreg(1),
122
            rn: xreg(2),
123
            rm: xreg(3),
124
        },
125
        "4100033A",
126
        "adcs w1, w2, w3",
127
    ));
128
    insns.push((
129
        Inst::AluRRR {
130
            alu_op: ALUOp::AdcS,
131
            size: OperandSize::Size64,
132
            rd: writable_xreg(4),
133
            rn: xreg(5),
134
            rm: xreg(6),
135
        },
136
        "A40006BA",
137
        "adcs x4, x5, x6",
138
    ));
139
    insns.push((
140
        Inst::AluRRR {
141
            alu_op: ALUOp::Sub,
142
            size: OperandSize::Size32,
143
            rd: writable_xreg(1),
144
            rn: xreg(2),
145
            rm: xreg(3),
146
        },
147
        "4100034B",
148
        "sub w1, w2, w3",
149
    ));
150
    insns.push((
151
        Inst::AluRRR {
152
            alu_op: ALUOp::Sub,
153
            size: OperandSize::Size64,
154
            rd: writable_xreg(4),
155
            rn: xreg(5),
156
            rm: xreg(6),
157
        },
158
        "A40006CB",
159
        "sub x4, x5, x6",
160
    ));
161
    insns.push((
162
        Inst::AluRRR {
163
            alu_op: ALUOp::Sbc,
164
            size: OperandSize::Size32,
165
            rd: writable_xreg(1),
166
            rn: xreg(2),
167
            rm: xreg(3),
168
        },
169
        "4100035A",
170
        "sbc w1, w2, w3",
171
    ));
172
    insns.push((
173
        Inst::AluRRR {
174
            alu_op: ALUOp::Sbc,
175
            size: OperandSize::Size64,
176
            rd: writable_xreg(4),
177
            rn: xreg(5),
178
            rm: xreg(6),
179
        },
180
        "A40006DA",
181
        "sbc x4, x5, x6",
182
    ));
183
    insns.push((
184
        Inst::AluRRR {
185
            alu_op: ALUOp::SbcS,
186
            size: OperandSize::Size32,
187
            rd: writable_xreg(1),
188
            rn: xreg(2),
189
            rm: xreg(3),
190
        },
191
        "4100037A",
192
        "sbcs w1, w2, w3",
193
    ));
194
    insns.push((
195
        Inst::AluRRR {
196
            alu_op: ALUOp::SbcS,
197
            size: OperandSize::Size64,
198
            rd: writable_xreg(4),
199
            rn: xreg(5),
200
            rm: xreg(6),
201
        },
202
        "A40006FA",
203
        "sbcs x4, x5, x6",
204
    ));
205

206
    insns.push((
207
        Inst::AluRRR {
208
            alu_op: ALUOp::Orr,
209
            size: OperandSize::Size32,
210
            rd: writable_xreg(1),
211
            rn: xreg(2),
212
            rm: xreg(3),
213
        },
214
        "4100032A",
215
        "orr w1, w2, w3",
216
    ));
217
    insns.push((
218
        Inst::AluRRR {
219
            alu_op: ALUOp::Orr,
220
            size: OperandSize::Size64,
221
            rd: writable_xreg(4),
222
            rn: xreg(5),
223
            rm: xreg(6),
224
        },
225
        "A40006AA",
226
        "orr x4, x5, x6",
227
    ));
228
    insns.push((
229
        Inst::AluRRR {
230
            alu_op: ALUOp::And,
231
            size: OperandSize::Size32,
232
            rd: writable_xreg(1),
233
            rn: xreg(2),
234
            rm: xreg(3),
235
        },
236
        "4100030A",
237
        "and w1, w2, w3",
238
    ));
239
    insns.push((
240
        Inst::AluRRR {
241
            alu_op: ALUOp::And,
242
            size: OperandSize::Size64,
243
            rd: writable_xreg(4),
244
            rn: xreg(5),
245
            rm: xreg(6),
246
        },
247
        "A400068A",
248
        "and x4, x5, x6",
249
    ));
250
    insns.push((
251
        Inst::AluRRR {
252
            alu_op: ALUOp::AndS,
253
            size: OperandSize::Size32,
254
            rd: writable_xreg(1),
255
            rn: xreg(2),
256
            rm: xreg(3),
257
        },
258
        "4100036A",
259
        "ands w1, w2, w3",
260
    ));
261
    insns.push((
262
        Inst::AluRRR {
263
            alu_op: ALUOp::AndS,
264
            size: OperandSize::Size64,
265
            rd: writable_xreg(4),
266
            rn: xreg(5),
267
            rm: xreg(6),
268
        },
269
        "A40006EA",
270
        "ands x4, x5, x6",
271
    ));
272
    insns.push((
273
        Inst::AluRRR {
274
            alu_op: ALUOp::SubS,
275
            size: OperandSize::Size32,
276
            rd: writable_zero_reg(),
277
            rn: xreg(2),
278
            rm: xreg(3),
279
        },
280
        "5F00036B",
281
        // TODO: Display as cmp
282
        "subs wzr, w2, w3",
283
    ));
284
    insns.push((
285
        Inst::AluRRR {
286
            alu_op: ALUOp::SubS,
287
            size: OperandSize::Size32,
288
            rd: writable_xreg(1),
289
            rn: xreg(2),
290
            rm: xreg(3),
291
        },
292
        "4100036B",
293
        "subs w1, w2, w3",
294
    ));
295
    insns.push((
296
        Inst::AluRRR {
297
            alu_op: ALUOp::SubS,
298
            size: OperandSize::Size64,
299
            rd: writable_xreg(4),
300
            rn: xreg(5),
301
            rm: xreg(6),
302
        },
303
        "A40006EB",
304
        "subs x4, x5, x6",
305
    ));
306
    insns.push((
307
        Inst::AluRRR {
308
            alu_op: ALUOp::AddS,
309
            size: OperandSize::Size32,
310
            rd: writable_xreg(1),
311
            rn: xreg(2),
312
            rm: xreg(3),
313
        },
314
        "4100032B",
315
        "adds w1, w2, w3",
316
    ));
317
    insns.push((
318
        Inst::AluRRR {
319
            alu_op: ALUOp::AddS,
320
            size: OperandSize::Size64,
321
            rd: writable_xreg(4),
322
            rn: xreg(5),
323
            rm: xreg(6),
324
        },
325
        "A40006AB",
326
        "adds x4, x5, x6",
327
    ));
328
    insns.push((
329
        Inst::AluRRImm12 {
330
            alu_op: ALUOp::AddS,
331
            size: OperandSize::Size64,
332
            rd: writable_zero_reg(),
333
            rn: xreg(5),
334
            imm12: Imm12::maybe_from_u64(1).unwrap(),
335
        },
336
        "BF0400B1",
337
        // TODO: Display as cmn.
338
        "adds xzr, x5, #1",
339
    ));
340
    insns.push((
341
        Inst::AluRRR {
342
            alu_op: ALUOp::SDiv,
343
            size: OperandSize::Size64,
344
            rd: writable_xreg(4),
345
            rn: xreg(5),
346
            rm: xreg(6),
347
        },
348
        "A40CC69A",
349
        "sdiv x4, x5, x6",
350
    ));
351
    insns.push((
352
        Inst::AluRRR {
353
            alu_op: ALUOp::UDiv,
354
            size: OperandSize::Size64,
355
            rd: writable_xreg(4),
356
            rn: xreg(5),
357
            rm: xreg(6),
358
        },
359
        "A408C69A",
360
        "udiv x4, x5, x6",
361
    ));
362

363
    insns.push((
364
        Inst::AluRRR {
365
            alu_op: ALUOp::Eor,
366
            size: OperandSize::Size32,
367
            rd: writable_xreg(4),
368
            rn: xreg(5),
369
            rm: xreg(6),
370
        },
371
        "A400064A",
372
        "eor w4, w5, w6",
373
    ));
374
    insns.push((
375
        Inst::AluRRR {
376
            alu_op: ALUOp::Eor,
377
            size: OperandSize::Size64,
378
            rd: writable_xreg(4),
379
            rn: xreg(5),
380
            rm: xreg(6),
381
        },
382
        "A40006CA",
383
        "eor x4, x5, x6",
384
    ));
385
    insns.push((
386
        Inst::AluRRR {
387
            alu_op: ALUOp::AndNot,
388
            size: OperandSize::Size32,
389
            rd: writable_xreg(4),
390
            rn: xreg(5),
391
            rm: xreg(6),
392
        },
393
        "A400260A",
394
        "bic w4, w5, w6",
395
    ));
396
    insns.push((
397
        Inst::AluRRR {
398
            alu_op: ALUOp::AndNot,
399
            size: OperandSize::Size64,
400
            rd: writable_xreg(4),
401
            rn: xreg(5),
402
            rm: xreg(6),
403
        },
404
        "A400268A",
405
        "bic x4, x5, x6",
406
    ));
407
    insns.push((
408
        Inst::AluRRR {
409
            alu_op: ALUOp::OrrNot,
410
            size: OperandSize::Size32,
411
            rd: writable_xreg(4),
412
            rn: xreg(5),
413
            rm: xreg(6),
414
        },
415
        "A400262A",
416
        "orn w4, w5, w6",
417
    ));
418
    insns.push((
419
        Inst::AluRRR {
420
            alu_op: ALUOp::OrrNot,
421
            size: OperandSize::Size64,
422
            rd: writable_xreg(4),
423
            rn: xreg(5),
424
            rm: xreg(6),
425
        },
426
        "A40026AA",
427
        "orn x4, x5, x6",
428
    ));
429
    insns.push((
430
        Inst::AluRRR {
431
            alu_op: ALUOp::EorNot,
432
            size: OperandSize::Size32,
433
            rd: writable_xreg(4),
434
            rn: xreg(5),
435
            rm: xreg(6),
436
        },
437
        "A400264A",
438
        "eon w4, w5, w6",
439
    ));
440
    insns.push((
441
        Inst::AluRRR {
442
            alu_op: ALUOp::EorNot,
443
            size: OperandSize::Size64,
444
            rd: writable_xreg(4),
445
            rn: xreg(5),
446
            rm: xreg(6),
447
        },
448
        "A40026CA",
449
        "eon x4, x5, x6",
450
    ));
451

452
    insns.push((
453
        Inst::AluRRR {
454
            alu_op: ALUOp::Extr,
455
            size: OperandSize::Size32,
456
            rd: writable_xreg(4),
457
            rn: xreg(5),
458
            rm: xreg(6),
459
        },
460
        "A42CC61A",
461
        "extr w4, w5, w6",
462
    ));
463
    insns.push((
464
        Inst::AluRRR {
465
            alu_op: ALUOp::Extr,
466
            size: OperandSize::Size64,
467
            rd: writable_xreg(4),
468
            rn: xreg(5),
469
            rm: xreg(6),
470
        },
471
        "A42CC69A",
472
        "extr x4, x5, x6",
473
    ));
474
    insns.push((
475
        Inst::AluRRR {
476
            alu_op: ALUOp::Lsr,
477
            size: OperandSize::Size32,
478
            rd: writable_xreg(4),
479
            rn: xreg(5),
480
            rm: xreg(6),
481
        },
482
        "A424C61A",
483
        "lsr w4, w5, w6",
484
    ));
485
    insns.push((
486
        Inst::AluRRR {
487
            alu_op: ALUOp::Lsr,
488
            size: OperandSize::Size64,
489
            rd: writable_xreg(4),
490
            rn: xreg(5),
491
            rm: xreg(6),
492
        },
493
        "A424C69A",
494
        "lsr x4, x5, x6",
495
    ));
496
    insns.push((
497
        Inst::AluRRR {
498
            alu_op: ALUOp::Asr,
499
            size: OperandSize::Size32,
500
            rd: writable_xreg(4),
501
            rn: xreg(5),
502
            rm: xreg(6),
503
        },
504
        "A428C61A",
505
        "asr w4, w5, w6",
506
    ));
507
    insns.push((
508
        Inst::AluRRR {
509
            alu_op: ALUOp::Asr,
510
            size: OperandSize::Size64,
511
            rd: writable_xreg(4),
512
            rn: xreg(5),
513
            rm: xreg(6),
514
        },
515
        "A428C69A",
516
        "asr x4, x5, x6",
517
    ));
518
    insns.push((
519
        Inst::AluRRR {
520
            alu_op: ALUOp::Lsl,
521
            size: OperandSize::Size32,
522
            rd: writable_xreg(4),
523
            rn: xreg(5),
524
            rm: xreg(6),
525
        },
526
        "A420C61A",
527
        "lsl w4, w5, w6",
528
    ));
529
    insns.push((
530
        Inst::AluRRR {
531
            alu_op: ALUOp::Lsl,
532
            size: OperandSize::Size64,
533
            rd: writable_xreg(4),
534
            rn: xreg(5),
535
            rm: xreg(6),
536
        },
537
        "A420C69A",
538
        "lsl x4, x5, x6",
539
    ));
540

541
    insns.push((
542
        Inst::AluRRImm12 {
543
            alu_op: ALUOp::Add,
544
            size: OperandSize::Size32,
545
            rd: writable_xreg(7),
546
            rn: xreg(8),
547
            imm12: Imm12 {
548
                bits: 0x123,
549
                shift12: false,
550
            },
551
        },
552
        "078D0411",
553
        "add w7, w8, #291",
554
    ));
555
    insns.push((
556
        Inst::AluRRImm12 {
557
            alu_op: ALUOp::Add,
558
            size: OperandSize::Size32,
559
            rd: writable_xreg(7),
560
            rn: xreg(8),
561
            imm12: Imm12 {
562
                bits: 0x123,
563
                shift12: true,
564
            },
565
        },
566
        "078D4411",
567
        "add w7, w8, #1191936",
568
    ));
569
    insns.push((
570
        Inst::AluRRImm12 {
571
            alu_op: ALUOp::Add,
572
            size: OperandSize::Size64,
573
            rd: writable_xreg(7),
574
            rn: xreg(8),
575
            imm12: Imm12 {
576
                bits: 0x123,
577
                shift12: false,
578
            },
579
        },
580
        "078D0491",
581
        "add x7, x8, #291",
582
    ));
583
    insns.push((
584
        Inst::AluRRImm12 {
585
            alu_op: ALUOp::Sub,
586
            size: OperandSize::Size32,
587
            rd: writable_xreg(7),
588
            rn: xreg(8),
589
            imm12: Imm12 {
590
                bits: 0x123,
591
                shift12: false,
592
            },
593
        },
594
        "078D0451",
595
        "sub w7, w8, #291",
596
    ));
597
    insns.push((
598
        Inst::AluRRImm12 {
599
            alu_op: ALUOp::Sub,
600
            size: OperandSize::Size64,
601
            rd: writable_xreg(7),
602
            rn: xreg(8),
603
            imm12: Imm12 {
604
                bits: 0x123,
605
                shift12: false,
606
            },
607
        },
608
        "078D04D1",
609
        "sub x7, x8, #291",
610
    ));
611
    insns.push((
612
        Inst::AluRRImm12 {
613
            alu_op: ALUOp::SubS,
614
            size: OperandSize::Size32,
615
            rd: writable_xreg(7),
616
            rn: xreg(8),
617
            imm12: Imm12 {
618
                bits: 0x123,
619
                shift12: false,
620
            },
621
        },
622
        "078D0471",
623
        "subs w7, w8, #291",
624
    ));
625
    insns.push((
626
        Inst::AluRRImm12 {
627
            alu_op: ALUOp::SubS,
628
            size: OperandSize::Size64,
629
            rd: writable_xreg(7),
630
            rn: xreg(8),
631
            imm12: Imm12 {
632
                bits: 0x123,
633
                shift12: false,
634
            },
635
        },
636
        "078D04F1",
637
        "subs x7, x8, #291",
638
    ));
639

640
    insns.push((
641
        Inst::AluRRRExtend {
642
            alu_op: ALUOp::Add,
643
            size: OperandSize::Size32,
644
            rd: writable_xreg(7),
645
            rn: xreg(8),
646
            rm: xreg(9),
647
            extendop: ExtendOp::SXTB,
648
        },
649
        "0781290B",
650
        "add w7, w8, w9, SXTB",
651
    ));
652

653
    insns.push((
654
        Inst::AluRRRExtend {
655
            alu_op: ALUOp::Add,
656
            size: OperandSize::Size64,
657
            rd: writable_xreg(15),
658
            rn: xreg(16),
659
            rm: xreg(17),
660
            extendop: ExtendOp::UXTB,
661
        },
662
        "0F02318B",
663
        "add x15, x16, x17, UXTB",
664
    ));
665

666
    insns.push((
667
        Inst::AluRRRExtend {
668
            alu_op: ALUOp::Sub,
669
            size: OperandSize::Size32,
670
            rd: writable_xreg(1),
671
            rn: xreg(2),
672
            rm: xreg(3),
673
            extendop: ExtendOp::SXTH,
674
        },
675
        "41A0234B",
676
        "sub w1, w2, w3, SXTH",
677
    ));
678

679
    insns.push((
680
        Inst::AluRRRExtend {
681
            alu_op: ALUOp::Sub,
682
            size: OperandSize::Size64,
683
            rd: writable_xreg(20),
684
            rn: xreg(21),
685
            rm: xreg(22),
686
            extendop: ExtendOp::UXTW,
687
        },
688
        "B44236CB",
689
        "sub x20, x21, x22, UXTW",
690
    ));
691

692
    insns.push((
693
        Inst::AluRRRShift {
694
            alu_op: ALUOp::Add,
695
            size: OperandSize::Size32,
696
            rd: writable_xreg(10),
697
            rn: xreg(11),
698
            rm: xreg(12),
699
            shiftop: ShiftOpAndAmt::new(
700
                ShiftOp::LSL,
701
                ShiftOpShiftImm::maybe_from_shift(20).unwrap(),
702
            ),
703
        },
704
        "6A510C0B",
705
        "add w10, w11, w12, LSL 20",
706
    ));
707
    insns.push((
708
        Inst::AluRRRShift {
709
            alu_op: ALUOp::Add,
710
            size: OperandSize::Size64,
711
            rd: writable_xreg(10),
712
            rn: xreg(11),
713
            rm: xreg(12),
714
            shiftop: ShiftOpAndAmt::new(
715
                ShiftOp::ASR,
716
                ShiftOpShiftImm::maybe_from_shift(42).unwrap(),
717
            ),
718
        },
719
        "6AA98C8B",
720
        "add x10, x11, x12, ASR 42",
721
    ));
722
    insns.push((
723
        Inst::AluRRRShift {
724
            alu_op: ALUOp::Sub,
725
            size: OperandSize::Size32,
726
            rd: writable_xreg(10),
727
            rn: xreg(11),
728
            rm: xreg(12),
729
            shiftop: ShiftOpAndAmt::new(
730
                ShiftOp::LSL,
731
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
732
            ),
733
        },
734
        "6A5D0C4B",
735
        "sub w10, w11, w12, LSL 23",
736
    ));
737
    insns.push((
738
        Inst::AluRRRShift {
739
            alu_op: ALUOp::Sub,
740
            size: OperandSize::Size64,
741
            rd: writable_xreg(10),
742
            rn: xreg(11),
743
            rm: xreg(12),
744
            shiftop: ShiftOpAndAmt::new(
745
                ShiftOp::LSL,
746
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
747
            ),
748
        },
749
        "6A5D0CCB",
750
        "sub x10, x11, x12, LSL 23",
751
    ));
752
    insns.push((
753
        Inst::AluRRRShift {
754
            alu_op: ALUOp::Orr,
755
            size: OperandSize::Size32,
756
            rd: writable_xreg(10),
757
            rn: xreg(11),
758
            rm: xreg(12),
759
            shiftop: ShiftOpAndAmt::new(
760
                ShiftOp::LSL,
761
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
762
            ),
763
        },
764
        "6A5D0C2A",
765
        "orr w10, w11, w12, LSL 23",
766
    ));
767
    insns.push((
768
        Inst::AluRRRShift {
769
            alu_op: ALUOp::Orr,
770
            size: OperandSize::Size64,
771
            rd: writable_xreg(10),
772
            rn: xreg(11),
773
            rm: xreg(12),
774
            shiftop: ShiftOpAndAmt::new(
775
                ShiftOp::LSL,
776
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
777
            ),
778
        },
779
        "6A5D0CAA",
780
        "orr x10, x11, x12, LSL 23",
781
    ));
782
    insns.push((
783
        Inst::AluRRRShift {
784
            alu_op: ALUOp::And,
785
            size: OperandSize::Size32,
786
            rd: writable_xreg(10),
787
            rn: xreg(11),
788
            rm: xreg(12),
789
            shiftop: ShiftOpAndAmt::new(
790
                ShiftOp::LSL,
791
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
792
            ),
793
        },
794
        "6A5D0C0A",
795
        "and w10, w11, w12, LSL 23",
796
    ));
797
    insns.push((
798
        Inst::AluRRRShift {
799
            alu_op: ALUOp::And,
800
            size: OperandSize::Size64,
801
            rd: writable_xreg(10),
802
            rn: xreg(11),
803
            rm: xreg(12),
804
            shiftop: ShiftOpAndAmt::new(
805
                ShiftOp::LSL,
806
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
807
            ),
808
        },
809
        "6A5D0C8A",
810
        "and x10, x11, x12, LSL 23",
811
    ));
812
    insns.push((
813
        Inst::AluRRRShift {
814
            alu_op: ALUOp::AndS,
815
            size: OperandSize::Size32,
816
            rd: writable_xreg(10),
817
            rn: xreg(11),
818
            rm: xreg(12),
819
            shiftop: ShiftOpAndAmt::new(
820
                ShiftOp::LSL,
821
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
822
            ),
823
        },
824
        "6A5D0C6A",
825
        "ands w10, w11, w12, LSL 23",
826
    ));
827
    insns.push((
828
        Inst::AluRRRShift {
829
            alu_op: ALUOp::AndS,
830
            size: OperandSize::Size64,
831
            rd: writable_xreg(10),
832
            rn: xreg(11),
833
            rm: xreg(12),
834
            shiftop: ShiftOpAndAmt::new(
835
                ShiftOp::LSL,
836
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
837
            ),
838
        },
839
        "6A5D0CEA",
840
        "ands x10, x11, x12, LSL 23",
841
    ));
842
    insns.push((
843
        Inst::AluRRRShift {
844
            alu_op: ALUOp::Eor,
845
            size: OperandSize::Size32,
846
            rd: writable_xreg(10),
847
            rn: xreg(11),
848
            rm: xreg(12),
849
            shiftop: ShiftOpAndAmt::new(
850
                ShiftOp::LSL,
851
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
852
            ),
853
        },
854
        "6A5D0C4A",
855
        "eor w10, w11, w12, LSL 23",
856
    ));
857
    insns.push((
858
        Inst::AluRRRShift {
859
            alu_op: ALUOp::Eor,
860
            size: OperandSize::Size64,
861
            rd: writable_xreg(10),
862
            rn: xreg(11),
863
            rm: xreg(12),
864
            shiftop: ShiftOpAndAmt::new(
865
                ShiftOp::LSL,
866
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
867
            ),
868
        },
869
        "6A5D0CCA",
870
        "eor x10, x11, x12, LSL 23",
871
    ));
872
    insns.push((
873
        Inst::AluRRRShift {
874
            alu_op: ALUOp::OrrNot,
875
            size: OperandSize::Size32,
876
            rd: writable_xreg(10),
877
            rn: xreg(11),
878
            rm: xreg(12),
879
            shiftop: ShiftOpAndAmt::new(
880
                ShiftOp::LSL,
881
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
882
            ),
883
        },
884
        "6A5D2C2A",
885
        "orn w10, w11, w12, LSL 23",
886
    ));
887
    insns.push((
888
        Inst::AluRRRShift {
889
            alu_op: ALUOp::OrrNot,
890
            size: OperandSize::Size64,
891
            rd: writable_xreg(10),
892
            rn: xreg(11),
893
            rm: xreg(12),
894
            shiftop: ShiftOpAndAmt::new(
895
                ShiftOp::LSL,
896
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
897
            ),
898
        },
899
        "6A5D2CAA",
900
        "orn x10, x11, x12, LSL 23",
901
    ));
902
    insns.push((
903
        Inst::AluRRRShift {
904
            alu_op: ALUOp::AndNot,
905
            size: OperandSize::Size32,
906
            rd: writable_xreg(10),
907
            rn: xreg(11),
908
            rm: xreg(12),
909
            shiftop: ShiftOpAndAmt::new(
910
                ShiftOp::LSL,
911
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
912
            ),
913
        },
914
        "6A5D2C0A",
915
        "bic w10, w11, w12, LSL 23",
916
    ));
917
    insns.push((
918
        Inst::AluRRRShift {
919
            alu_op: ALUOp::AndNot,
920
            size: OperandSize::Size64,
921
            rd: writable_xreg(10),
922
            rn: xreg(11),
923
            rm: xreg(12),
924
            shiftop: ShiftOpAndAmt::new(
925
                ShiftOp::LSL,
926
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
927
            ),
928
        },
929
        "6A5D2C8A",
930
        "bic x10, x11, x12, LSL 23",
931
    ));
932
    insns.push((
933
        Inst::AluRRRShift {
934
            alu_op: ALUOp::EorNot,
935
            size: OperandSize::Size32,
936
            rd: writable_xreg(10),
937
            rn: xreg(11),
938
            rm: xreg(12),
939
            shiftop: ShiftOpAndAmt::new(
940
                ShiftOp::LSL,
941
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
942
            ),
943
        },
944
        "6A5D2C4A",
945
        "eon w10, w11, w12, LSL 23",
946
    ));
947
    insns.push((
948
        Inst::AluRRRShift {
949
            alu_op: ALUOp::EorNot,
950
            size: OperandSize::Size64,
951
            rd: writable_xreg(10),
952
            rn: xreg(11),
953
            rm: xreg(12),
954
            shiftop: ShiftOpAndAmt::new(
955
                ShiftOp::LSL,
956
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
957
            ),
958
        },
959
        "6A5D2CCA",
960
        "eon x10, x11, x12, LSL 23",
961
    ));
962
    insns.push((
963
        Inst::AluRRRShift {
964
            alu_op: ALUOp::AddS,
965
            size: OperandSize::Size32,
966
            rd: writable_xreg(10),
967
            rn: xreg(11),
968
            rm: xreg(12),
969
            shiftop: ShiftOpAndAmt::new(
970
                ShiftOp::LSL,
971
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
972
            ),
973
        },
974
        "6A5D0C2B",
975
        "adds w10, w11, w12, LSL 23",
976
    ));
977
    insns.push((
978
        Inst::AluRRRShift {
979
            alu_op: ALUOp::AddS,
980
            size: OperandSize::Size64,
981
            rd: writable_xreg(10),
982
            rn: xreg(11),
983
            rm: xreg(12),
984
            shiftop: ShiftOpAndAmt::new(
985
                ShiftOp::LSL,
986
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
987
            ),
988
        },
989
        "6A5D0CAB",
990
        "adds x10, x11, x12, LSL 23",
991
    ));
992
    insns.push((
993
        Inst::AluRRRShift {
994
            alu_op: ALUOp::SubS,
995
            size: OperandSize::Size32,
996
            rd: writable_xreg(10),
997
            rn: xreg(11),
998
            rm: xreg(12),
999
            shiftop: ShiftOpAndAmt::new(
1000
                ShiftOp::LSL,
1001
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
1002
            ),
1003
        },
1004
        "6A5D0C6B",
1005
        "subs w10, w11, w12, LSL 23",
1006
    ));
1007
    insns.push((
1008
        Inst::AluRRRShift {
1009
            alu_op: ALUOp::SubS,
1010
            size: OperandSize::Size64,
1011
            rd: writable_xreg(10),
1012
            rn: xreg(11),
1013
            rm: xreg(12),
1014
            shiftop: ShiftOpAndAmt::new(
1015
                ShiftOp::LSL,
1016
                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
1017
            ),
1018
        },
1019
        "6A5D0CEB",
1020
        "subs x10, x11, x12, LSL 23",
1021
    ));
1022

1023
    insns.push((
1024
        Inst::AluRRRExtend {
1025
            alu_op: ALUOp::SubS,
1026
            size: OperandSize::Size64,
1027
            rd: writable_zero_reg(),
1028
            rn: stack_reg(),
1029
            rm: xreg(12),
1030
            extendop: ExtendOp::UXTX,
1031
        },
1032
        "FF632CEB",
1033
        "subs xzr, sp, x12, UXTX",
1034
    ));
1035

1036
    insns.push((
1037
        Inst::AluRRRR {
1038
            alu_op: ALUOp3::MAdd,
1039
            size: OperandSize::Size32,
1040
            rd: writable_xreg(1),
1041
            rn: xreg(2),
1042
            rm: xreg(3),
1043
            ra: xreg(4),
1044
        },
1045
        "4110031B",
1046
        "madd w1, w2, w3, w4",
1047
    ));
1048
    insns.push((
1049
        Inst::AluRRRR {
1050
            alu_op: ALUOp3::MAdd,
1051
            size: OperandSize::Size64,
1052
            rd: writable_xreg(1),
1053
            rn: xreg(2),
1054
            rm: xreg(3),
1055
            ra: xreg(4),
1056
        },
1057
        "4110039B",
1058
        "madd x1, x2, x3, x4",
1059
    ));
1060
    insns.push((
1061
        Inst::AluRRRR {
1062
            alu_op: ALUOp3::MSub,
1063
            size: OperandSize::Size32,
1064
            rd: writable_xreg(1),
1065
            rn: xreg(2),
1066
            rm: xreg(3),
1067
            ra: xreg(4),
1068
        },
1069
        "4190031B",
1070
        "msub w1, w2, w3, w4",
1071
    ));
1072
    insns.push((
1073
        Inst::AluRRRR {
1074
            alu_op: ALUOp3::MSub,
1075
            size: OperandSize::Size64,
1076
            rd: writable_xreg(1),
1077
            rn: xreg(2),
1078
            rm: xreg(3),
1079
            ra: xreg(4),
1080
        },
1081
        "4190039B",
1082
        "msub x1, x2, x3, x4",
1083
    ));
1084
    insns.push((
1085
        Inst::AluRRRR {
1086
            alu_op: ALUOp3::UMAddL,
1087
            size: OperandSize::Size32,
1088
            rd: writable_xreg(1),
1089
            rn: xreg(2),
1090
            rm: xreg(3),
1091
            ra: xreg(4),
1092
        },
1093
        "4110A39B",
1094
        "umaddl x1, w2, w3, x4",
1095
    ));
1096
    insns.push((
1097
        Inst::AluRRRR {
1098
            alu_op: ALUOp3::SMAddL,
1099
            size: OperandSize::Size32,
1100
            rd: writable_xreg(1),
1101
            rn: xreg(2),
1102
            rm: xreg(3),
1103
            ra: xreg(4),
1104
        },
1105
        "4110239B",
1106
        "smaddl x1, w2, w3, x4",
1107
    ));
1108
    insns.push((
1109
        Inst::AluRRR {
1110
            alu_op: ALUOp::SMulH,
1111
            size: OperandSize::Size64,
1112
            rd: writable_xreg(1),
1113
            rn: xreg(2),
1114
            rm: xreg(3),
1115
        },
1116
        "417C439B",
1117
        "smulh x1, x2, x3",
1118
    ));
1119
    insns.push((
1120
        Inst::AluRRR {
1121
            alu_op: ALUOp::UMulH,
1122
            size: OperandSize::Size64,
1123
            rd: writable_xreg(1),
1124
            rn: xreg(2),
1125
            rm: xreg(3),
1126
        },
1127
        "417CC39B",
1128
        "umulh x1, x2, x3",
1129
    ));
1130

1131
    insns.push((
1132
        Inst::AluRRImmShift {
1133
            alu_op: ALUOp::Extr,
1134
            size: OperandSize::Size32,
1135
            rd: writable_xreg(20),
1136
            rn: xreg(21),
1137
            immshift: ImmShift::maybe_from_u64(19).unwrap(),
1138
        },
1139
        "B44E9513",
1140
        "extr w20, w21, #19",
1141
    ));
1142
    insns.push((
1143
        Inst::AluRRImmShift {
1144
            alu_op: ALUOp::Extr,
1145
            size: OperandSize::Size64,
1146
            rd: writable_xreg(20),
1147
            rn: xreg(21),
1148
            immshift: ImmShift::maybe_from_u64(42).unwrap(),
1149
        },
1150
        "B4AAD593",
1151
        "extr x20, x21, #42",
1152
    ));
1153
    insns.push((
1154
        Inst::AluRRImmShift {
1155
            alu_op: ALUOp::Lsr,
1156
            size: OperandSize::Size32,
1157
            rd: writable_xreg(10),
1158
            rn: xreg(11),
1159
            immshift: ImmShift::maybe_from_u64(13).unwrap(),
1160
        },
1161
        "6A7D0D53",
1162
        "lsr w10, w11, #13",
1163
    ));
1164
    insns.push((
1165
        Inst::AluRRImmShift {
1166
            alu_op: ALUOp::Lsr,
1167
            size: OperandSize::Size64,
1168
            rd: writable_xreg(10),
1169
            rn: xreg(11),
1170
            immshift: ImmShift::maybe_from_u64(57).unwrap(),
1171
        },
1172
        "6AFD79D3",
1173
        "lsr x10, x11, #57",
1174
    ));
1175
    insns.push((
1176
        Inst::AluRRImmShift {
1177
            alu_op: ALUOp::Asr,
1178
            size: OperandSize::Size32,
1179
            rd: writable_xreg(4),
1180
            rn: xreg(5),
1181
            immshift: ImmShift::maybe_from_u64(7).unwrap(),
1182
        },
1183
        "A47C0713",
1184
        "asr w4, w5, #7",
1185
    ));
1186
    insns.push((
1187
        Inst::AluRRImmShift {
1188
            alu_op: ALUOp::Asr,
1189
            size: OperandSize::Size64,
1190
            rd: writable_xreg(4),
1191
            rn: xreg(5),
1192
            immshift: ImmShift::maybe_from_u64(35).unwrap(),
1193
        },
1194
        "A4FC6393",
1195
        "asr x4, x5, #35",
1196
    ));
1197
    insns.push((
1198
        Inst::AluRRImmShift {
1199
            alu_op: ALUOp::Lsl,
1200
            size: OperandSize::Size32,
1201
            rd: writable_xreg(8),
1202
            rn: xreg(9),
1203
            immshift: ImmShift::maybe_from_u64(24).unwrap(),
1204
        },
1205
        "281D0853",
1206
        "lsl w8, w9, #24",
1207
    ));
1208
    insns.push((
1209
        Inst::AluRRImmShift {
1210
            alu_op: ALUOp::Lsl,
1211
            size: OperandSize::Size64,
1212
            rd: writable_xreg(8),
1213
            rn: xreg(9),
1214
            immshift: ImmShift::maybe_from_u64(63).unwrap(),
1215
        },
1216
        "280141D3",
1217
        "lsl x8, x9, #63",
1218
    ));
1219
    insns.push((
1220
        Inst::AluRRImmShift {
1221
            alu_op: ALUOp::Lsl,
1222
            size: OperandSize::Size32,
1223
            rd: writable_xreg(10),
1224
            rn: xreg(11),
1225
            immshift: ImmShift::maybe_from_u64(0).unwrap(),
1226
        },
1227
        "6A7D0053",
1228
        "lsl w10, w11, #0",
1229
    ));
1230
    insns.push((
1231
        Inst::AluRRImmShift {
1232
            alu_op: ALUOp::Lsl,
1233
            size: OperandSize::Size64,
1234
            rd: writable_xreg(10),
1235
            rn: xreg(11),
1236
            immshift: ImmShift::maybe_from_u64(0).unwrap(),
1237
        },
1238
        "6AFD40D3",
1239
        "lsl x10, x11, #0",
1240
    ));
1241

1242
    insns.push((
1243
        Inst::AluRRImmLogic {
1244
            alu_op: ALUOp::And,
1245
            size: OperandSize::Size32,
1246
            rd: writable_xreg(21),
1247
            rn: xreg(27),
1248
            imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
1249
        },
1250
        "753B0112",
1251
        "and w21, w27, #2147500031",
1252
    ));
1253
    insns.push((
1254
        Inst::AluRRImmLogic {
1255
            alu_op: ALUOp::And,
1256
            size: OperandSize::Size64,
1257
            rd: writable_xreg(7),
1258
            rn: xreg(6),
1259
            imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
1260
        },
1261
        "C7381592",
1262
        "and x7, x6, #288221580125796352",
1263
    ));
1264
    insns.push((
1265
        Inst::AluRRImmLogic {
1266
            alu_op: ALUOp::AndS,
1267
            size: OperandSize::Size32,
1268
            rd: writable_xreg(21),
1269
            rn: xreg(27),
1270
            imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
1271
        },
1272
        "753B0172",
1273
        "ands w21, w27, #2147500031",
1274
    ));
1275
    insns.push((
1276
        Inst::AluRRImmLogic {
1277
            alu_op: ALUOp::AndS,
1278
            size: OperandSize::Size64,
1279
            rd: writable_xreg(7),
1280
            rn: xreg(6),
1281
            imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
1282
        },
1283
        "C73815F2",
1284
        "ands x7, x6, #288221580125796352",
1285
    ));
1286
    insns.push((
1287
        Inst::AluRRImmLogic {
1288
            alu_op: ALUOp::Orr,
1289
            size: OperandSize::Size32,
1290
            rd: writable_xreg(1),
1291
            rn: xreg(5),
1292
            imml: ImmLogic::maybe_from_u64(0x100000, I32).unwrap(),
1293
        },
1294
        "A1000C32",
1295
        "orr w1, w5, #1048576",
1296
    ));
1297
    insns.push((
1298
        Inst::AluRRImmLogic {
1299
            alu_op: ALUOp::Orr,
1300
            size: OperandSize::Size64,
1301
            rd: writable_xreg(4),
1302
            rn: xreg(5),
1303
            imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1304
        },
1305
        "A4C401B2",
1306
        "orr x4, x5, #9331882296111890817",
1307
    ));
1308
    insns.push((
1309
        Inst::AluRRImmLogic {
1310
            alu_op: ALUOp::Eor,
1311
            size: OperandSize::Size32,
1312
            rd: writable_xreg(1),
1313
            rn: xreg(5),
1314
            imml: ImmLogic::maybe_from_u64(0x00007fff, I32).unwrap(),
1315
        },
1316
        "A1380052",
1317
        "eor w1, w5, #32767",
1318
    ));
1319
    insns.push((
1320
        Inst::AluRRImmLogic {
1321
            alu_op: ALUOp::Eor,
1322
            size: OperandSize::Size64,
1323
            rd: writable_xreg(10),
1324
            rn: xreg(8),
1325
            imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1326
        },
1327
        "0AC501D2",
1328
        "eor x10, x8, #9331882296111890817",
1329
    ));
1330

1331
    insns.push((
1332
        Inst::BitRR {
1333
            op: BitOp::RBit,
1334
            size: OperandSize::Size32,
1335
            rd: writable_xreg(1),
1336
            rn: xreg(10),
1337
        },
1338
        "4101C05A",
1339
        "rbit w1, w10",
1340
    ));
1341

1342
    insns.push((
1343
        Inst::BitRR {
1344
            op: BitOp::RBit,
1345
            size: OperandSize::Size64,
1346
            rd: writable_xreg(1),
1347
            rn: xreg(10),
1348
        },
1349
        "4101C0DA",
1350
        "rbit x1, x10",
1351
    ));
1352

1353
    insns.push((
1354
        Inst::BitRR {
1355
            op: BitOp::Clz,
1356
            size: OperandSize::Size32,
1357
            rd: writable_xreg(15),
1358
            rn: xreg(3),
1359
        },
1360
        "6F10C05A",
1361
        "clz w15, w3",
1362
    ));
1363

1364
    insns.push((
1365
        Inst::BitRR {
1366
            op: BitOp::Clz,
1367
            size: OperandSize::Size64,
1368
            rd: writable_xreg(15),
1369
            rn: xreg(3),
1370
        },
1371
        "6F10C0DA",
1372
        "clz x15, x3",
1373
    ));
1374

1375
    insns.push((
1376
        Inst::BitRR {
1377
            op: BitOp::Cls,
1378
            size: OperandSize::Size32,
1379
            rd: writable_xreg(21),
1380
            rn: xreg(16),
1381
        },
1382
        "1516C05A",
1383
        "cls w21, w16",
1384
    ));
1385

1386
    insns.push((
1387
        Inst::BitRR {
1388
            op: BitOp::Cls,
1389
            size: OperandSize::Size64,
1390
            rd: writable_xreg(21),
1391
            rn: xreg(16),
1392
        },
1393
        "1516C0DA",
1394
        "cls x21, x16",
1395
    ));
1396

1397
    insns.push((
1398
        Inst::BitRR {
1399
            op: BitOp::Rev16,
1400
            size: OperandSize::Size64,
1401
            rd: writable_xreg(2),
1402
            rn: xreg(11),
1403
        },
1404
        "6205C0DA",
1405
        "rev16 x2, x11",
1406
    ));
1407

1408
    insns.push((
1409
        Inst::BitRR {
1410
            op: BitOp::Rev16,
1411
            size: OperandSize::Size32,
1412
            rd: writable_xreg(3),
1413
            rn: xreg(21),
1414
        },
1415
        "A306C05A",
1416
        "rev16 w3, w21",
1417
    ));
1418

1419
    insns.push((
1420
        Inst::BitRR {
1421
            op: BitOp::Rev32,
1422
            size: OperandSize::Size64,
1423
            rd: writable_xreg(2),
1424
            rn: xreg(11),
1425
        },
1426
        "6209C0DA",
1427
        "rev32 x2, x11",
1428
    ));
1429

1430
    insns.push((
1431
        Inst::BitRR {
1432
            op: BitOp::Rev32,
1433
            size: OperandSize::Size32,
1434
            rd: writable_xreg(3),
1435
            rn: xreg(21),
1436
        },
1437
        "A30AC05A",
1438
        "rev32 w3, w21",
1439
    ));
1440

1441
    insns.push((
1442
        Inst::BitRR {
1443
            op: BitOp::Rev64,
1444
            size: OperandSize::Size64,
1445
            rd: writable_xreg(1),
1446
            rn: xreg(10),
1447
        },
1448
        "410DC0DA",
1449
        "rev64 x1, x10",
1450
    ));
1451

1452
    insns.push((
1453
        Inst::ULoad8 {
1454
            rd: writable_xreg(1),
1455
            mem: AMode::Unscaled {
1456
                rn: xreg(2),
1457
                simm9: simm9_zero(),
1458
            },
1459
            flags: MemFlags::trusted(),
1460
        },
1461
        "41004038",
1462
        "ldurb w1, [x2]",
1463
    ));
1464
    insns.push((
1465
        Inst::ULoad8 {
1466
            rd: writable_xreg(1),
1467
            mem: AMode::UnsignedOffset {
1468
                rn: xreg(2),
1469
                uimm12: UImm12Scaled::zero(I8),
1470
            },
1471
            flags: MemFlags::trusted(),
1472
        },
1473
        "41004039",
1474
        "ldrb w1, [x2]",
1475
    ));
1476
    insns.push((
1477
        Inst::ULoad8 {
1478
            rd: writable_xreg(1),
1479
            mem: AMode::RegReg {
1480
                rn: xreg(2),
1481
                rm: xreg(5),
1482
            },
1483
            flags: MemFlags::trusted(),
1484
        },
1485
        "41686538",
1486
        "ldrb w1, [x2, x5]",
1487
    ));
1488
    insns.push((
1489
        Inst::SLoad8 {
1490
            rd: writable_xreg(1),
1491
            mem: AMode::Unscaled {
1492
                rn: xreg(2),
1493
                simm9: simm9_zero(),
1494
            },
1495
            flags: MemFlags::trusted(),
1496
        },
1497
        "41008038",
1498
        "ldursb x1, [x2]",
1499
    ));
1500
    insns.push((
1501
        Inst::SLoad8 {
1502
            rd: writable_xreg(1),
1503
            mem: AMode::UnsignedOffset {
1504
                rn: xreg(2),
1505
                uimm12: UImm12Scaled::maybe_from_i64(63, I8).unwrap(),
1506
            },
1507
            flags: MemFlags::trusted(),
1508
        },
1509
        "41FC8039",
1510
        "ldrsb x1, [x2, #63]",
1511
    ));
1512
    insns.push((
1513
        Inst::SLoad8 {
1514
            rd: writable_xreg(1),
1515
            mem: AMode::RegReg {
1516
                rn: xreg(2),
1517
                rm: xreg(5),
1518
            },
1519
            flags: MemFlags::trusted(),
1520
        },
1521
        "4168A538",
1522
        "ldrsb x1, [x2, x5]",
1523
    ));
1524
    insns.push((
1525
        Inst::ULoad16 {
1526
            rd: writable_xreg(1),
1527
            mem: AMode::Unscaled {
1528
                rn: xreg(2),
1529
                simm9: SImm9::maybe_from_i64(5).unwrap(),
1530
            },
1531
            flags: MemFlags::trusted(),
1532
        },
1533
        "41504078",
1534
        "ldurh w1, [x2, #5]",
1535
    ));
1536
    insns.push((
1537
        Inst::ULoad16 {
1538
            rd: writable_xreg(1),
1539
            mem: AMode::UnsignedOffset {
1540
                rn: xreg(2),
1541
                uimm12: UImm12Scaled::maybe_from_i64(8, I16).unwrap(),
1542
            },
1543
            flags: MemFlags::trusted(),
1544
        },
1545
        "41104079",
1546
        "ldrh w1, [x2, #8]",
1547
    ));
1548
    insns.push((
1549
        Inst::ULoad16 {
1550
            rd: writable_xreg(1),
1551
            mem: AMode::RegScaled {
1552
                rn: xreg(2),
1553
                rm: xreg(3),
1554
            },
1555
            flags: MemFlags::trusted(),
1556
        },
1557
        "41786378",
1558
        "ldrh w1, [x2, x3, LSL #1]",
1559
    ));
1560
    insns.push((
1561
        Inst::SLoad16 {
1562
            rd: writable_xreg(1),
1563
            mem: AMode::Unscaled {
1564
                rn: xreg(2),
1565
                simm9: simm9_zero(),
1566
            },
1567
            flags: MemFlags::trusted(),
1568
        },
1569
        "41008078",
1570
        "ldursh x1, [x2]",
1571
    ));
1572
    insns.push((
1573
        Inst::SLoad16 {
1574
            rd: writable_xreg(28),
1575
            mem: AMode::UnsignedOffset {
1576
                rn: xreg(20),
1577
                uimm12: UImm12Scaled::maybe_from_i64(24, I16).unwrap(),
1578
            },
1579
            flags: MemFlags::trusted(),
1580
        },
1581
        "9C328079",
1582
        "ldrsh x28, [x20, #24]",
1583
    ));
1584
    insns.push((
1585
        Inst::SLoad16 {
1586
            rd: writable_xreg(28),
1587
            mem: AMode::RegScaled {
1588
                rn: xreg(20),
1589
                rm: xreg(20),
1590
            },
1591
            flags: MemFlags::trusted(),
1592
        },
1593
        "9C7AB478",
1594
        "ldrsh x28, [x20, x20, LSL #1]",
1595
    ));
1596
    insns.push((
1597
        Inst::ULoad32 {
1598
            rd: writable_xreg(1),
1599
            mem: AMode::Unscaled {
1600
                rn: xreg(2),
1601
                simm9: simm9_zero(),
1602
            },
1603
            flags: MemFlags::trusted(),
1604
        },
1605
        "410040B8",
1606
        "ldur w1, [x2]",
1607
    ));
1608
    insns.push((
1609
        Inst::ULoad32 {
1610
            rd: writable_xreg(12),
1611
            mem: AMode::UnsignedOffset {
1612
                rn: xreg(0),
1613
                uimm12: UImm12Scaled::maybe_from_i64(204, I32).unwrap(),
1614
            },
1615
            flags: MemFlags::trusted(),
1616
        },
1617
        "0CCC40B9",
1618
        "ldr w12, [x0, #204]",
1619
    ));
1620
    insns.push((
1621
        Inst::ULoad32 {
1622
            rd: writable_xreg(1),
1623
            mem: AMode::RegScaled {
1624
                rn: xreg(2),
1625
                rm: xreg(12),
1626
            },
1627
            flags: MemFlags::trusted(),
1628
        },
1629
        "41786CB8",
1630
        "ldr w1, [x2, x12, LSL #2]",
1631
    ));
1632
    insns.push((
1633
        Inst::SLoad32 {
1634
            rd: writable_xreg(1),
1635
            mem: AMode::Unscaled {
1636
                rn: xreg(2),
1637
                simm9: simm9_zero(),
1638
            },
1639
            flags: MemFlags::trusted(),
1640
        },
1641
        "410080B8",
1642
        "ldursw x1, [x2]",
1643
    ));
1644
    insns.push((
1645
        Inst::SLoad32 {
1646
            rd: writable_xreg(12),
1647
            mem: AMode::UnsignedOffset {
1648
                rn: xreg(1),
1649
                uimm12: UImm12Scaled::maybe_from_i64(16380, I32).unwrap(),
1650
            },
1651
            flags: MemFlags::trusted(),
1652
        },
1653
        "2CFCBFB9",
1654
        "ldrsw x12, [x1, #16380]",
1655
    ));
1656
    insns.push((
1657
        Inst::SLoad32 {
1658
            rd: writable_xreg(1),
1659
            mem: AMode::RegScaled {
1660
                rn: xreg(5),
1661
                rm: xreg(1),
1662
            },
1663
            flags: MemFlags::trusted(),
1664
        },
1665
        "A178A1B8",
1666
        "ldrsw x1, [x5, x1, LSL #2]",
1667
    ));
1668
    insns.push((
1669
        Inst::ULoad64 {
1670
            rd: writable_xreg(1),
1671
            mem: AMode::Unscaled {
1672
                rn: xreg(2),
1673
                simm9: simm9_zero(),
1674
            },
1675
            flags: MemFlags::trusted(),
1676
        },
1677
        "410040F8",
1678
        "ldur x1, [x2]",
1679
    ));
1680
    insns.push((
1681
        Inst::ULoad64 {
1682
            rd: writable_xreg(1),
1683
            mem: AMode::Unscaled {
1684
                rn: xreg(2),
1685
                simm9: SImm9::maybe_from_i64(-256).unwrap(),
1686
            },
1687
            flags: MemFlags::trusted(),
1688
        },
1689
        "410050F8",
1690
        "ldur x1, [x2, #-256]",
1691
    ));
1692
    insns.push((
1693
        Inst::ULoad64 {
1694
            rd: writable_xreg(1),
1695
            mem: AMode::Unscaled {
1696
                rn: xreg(2),
1697
                simm9: SImm9::maybe_from_i64(255).unwrap(),
1698
            },
1699
            flags: MemFlags::trusted(),
1700
        },
1701
        "41F04FF8",
1702
        "ldur x1, [x2, #255]",
1703
    ));
1704
    insns.push((
1705
        Inst::ULoad64 {
1706
            rd: writable_xreg(1),
1707
            mem: AMode::UnsignedOffset {
1708
                rn: xreg(2),
1709
                uimm12: UImm12Scaled::maybe_from_i64(32760, I64).unwrap(),
1710
            },
1711
            flags: MemFlags::trusted(),
1712
        },
1713
        "41FC7FF9",
1714
        "ldr x1, [x2, #32760]",
1715
    ));
1716
    insns.push((
1717
        Inst::ULoad64 {
1718
            rd: writable_xreg(1),
1719
            mem: AMode::RegReg {
1720
                rn: xreg(2),
1721
                rm: xreg(3),
1722
            },
1723
            flags: MemFlags::trusted(),
1724
        },
1725
        "416863F8",
1726
        "ldr x1, [x2, x3]",
1727
    ));
1728
    insns.push((
1729
        Inst::ULoad64 {
1730
            rd: writable_xreg(1),
1731
            mem: AMode::RegScaled {
1732
                rn: xreg(2),
1733
                rm: xreg(3),
1734
            },
1735
            flags: MemFlags::trusted(),
1736
        },
1737
        "417863F8",
1738
        "ldr x1, [x2, x3, LSL #3]",
1739
    ));
1740
    insns.push((
1741
        Inst::ULoad64 {
1742
            rd: writable_xreg(1),
1743
            mem: AMode::RegScaledExtended {
1744
                rn: xreg(2),
1745
                rm: xreg(3),
1746
                extendop: ExtendOp::SXTW,
1747
            },
1748
            flags: MemFlags::trusted(),
1749
        },
1750
        "41D863F8",
1751
        "ldr x1, [x2, w3, SXTW #3]",
1752
    ));
1753
    insns.push((
1754
        Inst::ULoad64 {
1755
            rd: writable_xreg(1),
1756
            mem: AMode::RegExtended {
1757
                rn: xreg(2),
1758
                rm: xreg(3),
1759
                extendop: ExtendOp::SXTW,
1760
            },
1761
            flags: MemFlags::trusted(),
1762
        },
1763
        "41C863F8",
1764
        "ldr x1, [x2, w3, SXTW]",
1765
    ));
1766
    insns.push((
1767
        Inst::ULoad64 {
1768
            rd: writable_xreg(1),
1769
            mem: AMode::Label {
1770
                label: MemLabel::PCRel(64),
1771
            },
1772
            flags: MemFlags::trusted(),
1773
        },
1774
        "01020058",
1775
        "ldr x1, pc+64",
1776
    ));
1777
    insns.push((
1778
        Inst::ULoad64 {
1779
            rd: writable_xreg(1),
1780
            mem: AMode::SPPreIndexed {
1781
                simm9: SImm9::maybe_from_i64(16).unwrap(),
1782
            },
1783
            flags: MemFlags::trusted(),
1784
        },
1785
        "E10F41F8",
1786
        "ldr x1, [sp, #16]!",
1787
    ));
1788
    insns.push((
1789
        Inst::ULoad64 {
1790
            rd: writable_xreg(1),
1791
            mem: AMode::SPPostIndexed {
1792
                simm9: SImm9::maybe_from_i64(16).unwrap(),
1793
            },
1794
            flags: MemFlags::trusted(),
1795
        },
1796
        "E10741F8",
1797
        "ldr x1, [sp], #16",
1798
    ));
1799
    insns.push((
1800
        Inst::ULoad64 {
1801
            rd: writable_xreg(1),
1802
            mem: AMode::FPOffset { off: 32768 },
1803
            flags: MemFlags::trusted(),
1804
        },
1805
        "100090D2A1EB70F8",
1806
        "movz x16, #32768 ; ldr x1, [fp, x16, SXTX]",
1807
    ));
1808
    insns.push((
1809
        Inst::ULoad64 {
1810
            rd: writable_xreg(1),
1811
            mem: AMode::FPOffset { off: -32768 },
1812
            flags: MemFlags::trusted(),
1813
        },
1814
        "F0FF8F92A1EB70F8",
1815
        "movn x16, #32767 ; ldr x1, [fp, x16, SXTX]",
1816
    ));
1817
    insns.push((
1818
        Inst::ULoad64 {
1819
            rd: writable_xreg(1),
1820
            mem: AMode::FPOffset { off: 1048576 }, // 2^20
1821
            flags: MemFlags::trusted(),
1822
        },
1823
        "1002A0D2A1EB70F8",
1824
        "movz x16, #16, LSL #16 ; ldr x1, [fp, x16, SXTX]",
1825
    ));
1826
    insns.push((
1827
        Inst::ULoad64 {
1828
            rd: writable_xreg(1),
1829
            mem: AMode::FPOffset { off: 1048576 + 1 }, // 2^20 + 1
1830
            flags: MemFlags::trusted(),
1831
        },
1832
        "300080521002A072A1EB70F8",
1833
        "movz w16, #1 ; movk w16, w16, #16, LSL #16 ; ldr x1, [fp, x16, SXTX]",
1834
    ));
1835

1836
    insns.push((
1837
        Inst::ULoad64 {
1838
            rd: writable_xreg(1),
1839
            mem: AMode::RegOffset {
1840
                rn: xreg(7),
1841
                off: 8,
1842
            },
1843
            flags: MemFlags::trusted(),
1844
        },
1845
        "E18040F8",
1846
        "ldr x1, [x7, #8]",
1847
    ));
1848

1849
    insns.push((
1850
        Inst::ULoad64 {
1851
            rd: writable_xreg(1),
1852
            mem: AMode::RegOffset {
1853
                rn: xreg(7),
1854
                off: 1024,
1855
            },
1856
            flags: MemFlags::trusted(),
1857
        },
1858
        "E10042F9",
1859
        "ldr x1, [x7, #1024]",
1860
    ));
1861

1862
    insns.push((
1863
        Inst::ULoad64 {
1864
            rd: writable_xreg(1),
1865
            mem: AMode::RegOffset {
1866
                rn: xreg(7),
1867
                off: 1048576,
1868
            },
1869
            flags: MemFlags::trusted(),
1870
        },
1871
        "1002A0D2E1E870F8",
1872
        "movz x16, #16, LSL #16 ; ldr x1, [x7, x16, SXTX]",
1873
    ));
1874

1875
    insns.push((
1876
        Inst::Store8 {
1877
            rd: xreg(1),
1878
            mem: AMode::Unscaled {
1879
                rn: xreg(2),
1880
                simm9: simm9_zero(),
1881
            },
1882
            flags: MemFlags::trusted(),
1883
        },
1884
        "41000038",
1885
        "sturb w1, [x2]",
1886
    ));
1887
    insns.push((
1888
        Inst::Store8 {
1889
            rd: xreg(1),
1890
            mem: AMode::UnsignedOffset {
1891
                rn: xreg(2),
1892
                uimm12: UImm12Scaled::maybe_from_i64(4095, I8).unwrap(),
1893
            },
1894
            flags: MemFlags::trusted(),
1895
        },
1896
        "41FC3F39",
1897
        "strb w1, [x2, #4095]",
1898
    ));
1899
    insns.push((
1900
        Inst::Store16 {
1901
            rd: xreg(1),
1902
            mem: AMode::Unscaled {
1903
                rn: xreg(2),
1904
                simm9: simm9_zero(),
1905
            },
1906
            flags: MemFlags::trusted(),
1907
        },
1908
        "41000078",
1909
        "sturh w1, [x2]",
1910
    ));
1911
    insns.push((
1912
        Inst::Store16 {
1913
            rd: xreg(1),
1914
            mem: AMode::UnsignedOffset {
1915
                rn: xreg(2),
1916
                uimm12: UImm12Scaled::maybe_from_i64(8190, I16).unwrap(),
1917
            },
1918
            flags: MemFlags::trusted(),
1919
        },
1920
        "41FC3F79",
1921
        "strh w1, [x2, #8190]",
1922
    ));
1923
    insns.push((
1924
        Inst::Store32 {
1925
            rd: xreg(1),
1926
            mem: AMode::Unscaled {
1927
                rn: xreg(2),
1928
                simm9: simm9_zero(),
1929
            },
1930
            flags: MemFlags::trusted(),
1931
        },
1932
        "410000B8",
1933
        "stur w1, [x2]",
1934
    ));
1935
    insns.push((
1936
        Inst::Store32 {
1937
            rd: xreg(1),
1938
            mem: AMode::UnsignedOffset {
1939
                rn: xreg(2),
1940
                uimm12: UImm12Scaled::maybe_from_i64(16380, I32).unwrap(),
1941
            },
1942
            flags: MemFlags::trusted(),
1943
        },
1944
        "41FC3FB9",
1945
        "str w1, [x2, #16380]",
1946
    ));
1947
    insns.push((
1948
        Inst::Store64 {
1949
            rd: xreg(1),
1950
            mem: AMode::Unscaled {
1951
                rn: xreg(2),
1952
                simm9: simm9_zero(),
1953
            },
1954
            flags: MemFlags::trusted(),
1955
        },
1956
        "410000F8",
1957
        "stur x1, [x2]",
1958
    ));
1959
    insns.push((
1960
        Inst::Store64 {
1961
            rd: xreg(1),
1962
            mem: AMode::UnsignedOffset {
1963
                rn: xreg(2),
1964
                uimm12: UImm12Scaled::maybe_from_i64(32760, I64).unwrap(),
1965
            },
1966
            flags: MemFlags::trusted(),
1967
        },
1968
        "41FC3FF9",
1969
        "str x1, [x2, #32760]",
1970
    ));
1971
    insns.push((
1972
        Inst::Store64 {
1973
            rd: xreg(1),
1974
            mem: AMode::RegReg {
1975
                rn: xreg(2),
1976
                rm: xreg(3),
1977
            },
1978
            flags: MemFlags::trusted(),
1979
        },
1980
        "416823F8",
1981
        "str x1, [x2, x3]",
1982
    ));
1983
    insns.push((
1984
        Inst::Store64 {
1985
            rd: xreg(1),
1986
            mem: AMode::RegScaled {
1987
                rn: xreg(2),
1988
                rm: xreg(3),
1989
            },
1990
            flags: MemFlags::trusted(),
1991
        },
1992
        "417823F8",
1993
        "str x1, [x2, x3, LSL #3]",
1994
    ));
1995
    insns.push((
1996
        Inst::Store64 {
1997
            rd: xreg(1),
1998
            mem: AMode::RegScaledExtended {
1999
                rn: xreg(2),
2000
                rm: xreg(3),
2001
                extendop: ExtendOp::UXTW,
2002
            },
2003
            flags: MemFlags::trusted(),
2004
        },
2005
        "415823F8",
2006
        "str x1, [x2, w3, UXTW #3]",
2007
    ));
2008
    insns.push((
2009
        Inst::Store64 {
2010
            rd: xreg(1),
2011
            mem: AMode::RegExtended {
2012
                rn: xreg(2),
2013
                rm: xreg(3),
2014
                extendop: ExtendOp::UXTW,
2015
            },
2016
            flags: MemFlags::trusted(),
2017
        },
2018
        "414823F8",
2019
        "str x1, [x2, w3, UXTW]",
2020
    ));
2021
    insns.push((
2022
        Inst::Store64 {
2023
            rd: xreg(1),
2024
            mem: AMode::SPPreIndexed {
2025
                simm9: SImm9::maybe_from_i64(16).unwrap(),
2026
            },
2027
            flags: MemFlags::trusted(),
2028
        },
2029
        "E10F01F8",
2030
        "str x1, [sp, #16]!",
2031
    ));
2032
    insns.push((
2033
        Inst::Store64 {
2034
            rd: xreg(1),
2035
            mem: AMode::SPPostIndexed {
2036
                simm9: SImm9::maybe_from_i64(16).unwrap(),
2037
            },
2038
            flags: MemFlags::trusted(),
2039
        },
2040
        "E10701F8",
2041
        "str x1, [sp], #16",
2042
    ));
2043

2044
    insns.push((
2045
        Inst::StoreP64 {
2046
            rt: xreg(8),
2047
            rt2: xreg(9),
2048
            mem: PairAMode::SignedOffset {
2049
                reg: xreg(10),
2050
                simm7: simm7_scaled_zero(I64),
2051
            },
2052
            flags: MemFlags::trusted(),
2053
        },
2054
        "482500A9",
2055
        "stp x8, x9, [x10]",
2056
    ));
2057
    insns.push((
2058
        Inst::StoreP64 {
2059
            rt: xreg(8),
2060
            rt2: xreg(9),
2061
            mem: PairAMode::SignedOffset {
2062
                reg: xreg(10),
2063
                simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2064
            },
2065
            flags: MemFlags::trusted(),
2066
        },
2067
        "48A51FA9",
2068
        "stp x8, x9, [x10, #504]",
2069
    ));
2070
    insns.push((
2071
        Inst::StoreP64 {
2072
            rt: xreg(8),
2073
            rt2: xreg(9),
2074
            mem: PairAMode::SignedOffset {
2075
                reg: xreg(10),
2076
                simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2077
            },
2078
            flags: MemFlags::trusted(),
2079
        },
2080
        "48253CA9",
2081
        "stp x8, x9, [x10, #-64]",
2082
    ));
2083
    insns.push((
2084
        Inst::StoreP64 {
2085
            rt: xreg(21),
2086
            rt2: xreg(28),
2087
            mem: PairAMode::SignedOffset {
2088
                reg: xreg(1),
2089
                simm7: SImm7Scaled::maybe_from_i64(-512, I64).unwrap(),
2090
            },
2091
            flags: MemFlags::trusted(),
2092
        },
2093
        "357020A9",
2094
        "stp x21, x28, [x1, #-512]",
2095
    ));
2096
    insns.push((
2097
        Inst::StoreP64 {
2098
            rt: xreg(8),
2099
            rt2: xreg(9),
2100
            mem: PairAMode::SPPreIndexed {
2101
                simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2102
            },
2103
            flags: MemFlags::trusted(),
2104
        },
2105
        "E827BCA9",
2106
        "stp x8, x9, [sp, #-64]!",
2107
    ));
2108
    insns.push((
2109
        Inst::StoreP64 {
2110
            rt: xreg(15),
2111
            rt2: xreg(16),
2112
            mem: PairAMode::SPPostIndexed {
2113
                simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2114
            },
2115
            flags: MemFlags::trusted(),
2116
        },
2117
        "EFC39FA8",
2118
        "stp x15, x16, [sp], #504",
2119
    ));
2120

2121
    insns.push((
2122
        Inst::LoadP64 {
2123
            rt: writable_xreg(8),
2124
            rt2: writable_xreg(9),
2125
            mem: PairAMode::SignedOffset {
2126
                reg: xreg(10),
2127
                simm7: simm7_scaled_zero(I64),
2128
            },
2129
            flags: MemFlags::trusted(),
2130
        },
2131
        "482540A9",
2132
        "ldp x8, x9, [x10]",
2133
    ));
2134
    insns.push((
2135
        Inst::LoadP64 {
2136
            rt: writable_xreg(8),
2137
            rt2: writable_xreg(9),
2138
            mem: PairAMode::SignedOffset {
2139
                reg: xreg(10),
2140
                simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2141
            },
2142
            flags: MemFlags::trusted(),
2143
        },
2144
        "48A55FA9",
2145
        "ldp x8, x9, [x10, #504]",
2146
    ));
2147
    insns.push((
2148
        Inst::LoadP64 {
2149
            rt: writable_xreg(8),
2150
            rt2: writable_xreg(9),
2151
            mem: PairAMode::SignedOffset {
2152
                reg: xreg(10),
2153
                simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2154
            },
2155
            flags: MemFlags::trusted(),
2156
        },
2157
        "48257CA9",
2158
        "ldp x8, x9, [x10, #-64]",
2159
    ));
2160
    insns.push((
2161
        Inst::LoadP64 {
2162
            rt: writable_xreg(8),
2163
            rt2: writable_xreg(9),
2164
            mem: PairAMode::SignedOffset {
2165
                reg: xreg(10),
2166
                simm7: SImm7Scaled::maybe_from_i64(-512, I64).unwrap(),
2167
            },
2168
            flags: MemFlags::trusted(),
2169
        },
2170
        "482560A9",
2171
        "ldp x8, x9, [x10, #-512]",
2172
    ));
2173
    insns.push((
2174
        Inst::LoadP64 {
2175
            rt: writable_xreg(8),
2176
            rt2: writable_xreg(9),
2177
            mem: PairAMode::SPPreIndexed {
2178
                simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2179
            },
2180
            flags: MemFlags::trusted(),
2181
        },
2182
        "E827FCA9",
2183
        "ldp x8, x9, [sp, #-64]!",
2184
    ));
2185
    insns.push((
2186
        Inst::LoadP64 {
2187
            rt: writable_xreg(8),
2188
            rt2: writable_xreg(25),
2189
            mem: PairAMode::SPPostIndexed {
2190
                simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2191
            },
2192
            flags: MemFlags::trusted(),
2193
        },
2194
        "E8E7DFA8",
2195
        "ldp x8, x25, [sp], #504",
2196
    ));
2197

2198
    insns.push((
2199
        Inst::Mov {
2200
            size: OperandSize::Size64,
2201
            rd: writable_xreg(8),
2202
            rm: xreg(9),
2203
        },
2204
        "E80309AA",
2205
        "mov x8, x9",
2206
    ));
2207
    insns.push((
2208
        Inst::Mov {
2209
            size: OperandSize::Size32,
2210
            rd: writable_xreg(8),
2211
            rm: xreg(9),
2212
        },
2213
        "E803092A",
2214
        "mov w8, w9",
2215
    ));
2216

2217
    insns.push((
2218
        Inst::MovWide {
2219
            op: MoveWideOp::MovZ,
2220
            rd: writable_xreg(8),
2221
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2222
            size: OperandSize::Size64,
2223
        },
2224
        "E8FF9FD2",
2225
        "movz x8, #65535",
2226
    ));
2227
    insns.push((
2228
        Inst::MovWide {
2229
            op: MoveWideOp::MovZ,
2230
            rd: writable_xreg(8),
2231
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2232
            size: OperandSize::Size64,
2233
        },
2234
        "E8FFBFD2",
2235
        "movz x8, #65535, LSL #16",
2236
    ));
2237
    insns.push((
2238
        Inst::MovWide {
2239
            op: MoveWideOp::MovZ,
2240
            rd: writable_xreg(8),
2241
            imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
2242
            size: OperandSize::Size64,
2243
        },
2244
        "E8FFDFD2",
2245
        "movz x8, #65535, LSL #32",
2246
    ));
2247
    insns.push((
2248
        Inst::MovWide {
2249
            op: MoveWideOp::MovZ,
2250
            rd: writable_xreg(8),
2251
            imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
2252
            size: OperandSize::Size64,
2253
        },
2254
        "E8FFFFD2",
2255
        "movz x8, #65535, LSL #48",
2256
    ));
2257
    insns.push((
2258
        Inst::MovWide {
2259
            op: MoveWideOp::MovZ,
2260
            rd: writable_xreg(8),
2261
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2262
            size: OperandSize::Size32,
2263
        },
2264
        "E8FFBF52",
2265
        "movz w8, #65535, LSL #16",
2266
    ));
2267

2268
    insns.push((
2269
        Inst::MovWide {
2270
            op: MoveWideOp::MovN,
2271
            rd: writable_xreg(8),
2272
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2273
            size: OperandSize::Size64,
2274
        },
2275
        "E8FF9F92",
2276
        "movn x8, #65535",
2277
    ));
2278
    insns.push((
2279
        Inst::MovWide {
2280
            op: MoveWideOp::MovN,
2281
            rd: writable_xreg(8),
2282
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2283
            size: OperandSize::Size64,
2284
        },
2285
        "E8FFBF92",
2286
        "movn x8, #65535, LSL #16",
2287
    ));
2288
    insns.push((
2289
        Inst::MovWide {
2290
            op: MoveWideOp::MovN,
2291
            rd: writable_xreg(8),
2292
            imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
2293
            size: OperandSize::Size64,
2294
        },
2295
        "E8FFDF92",
2296
        "movn x8, #65535, LSL #32",
2297
    ));
2298
    insns.push((
2299
        Inst::MovWide {
2300
            op: MoveWideOp::MovN,
2301
            rd: writable_xreg(8),
2302
            imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
2303
            size: OperandSize::Size64,
2304
        },
2305
        "E8FFFF92",
2306
        "movn x8, #65535, LSL #48",
2307
    ));
2308
    insns.push((
2309
        Inst::MovWide {
2310
            op: MoveWideOp::MovN,
2311
            rd: writable_xreg(8),
2312
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2313
            size: OperandSize::Size32,
2314
        },
2315
        "E8FF9F12",
2316
        "movn w8, #65535",
2317
    ));
2318

2319
    insns.push((
2320
        Inst::MovK {
2321
            rd: writable_xreg(12),
2322
            rn: xreg(12),
2323
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_0000).unwrap(),
2324
            size: OperandSize::Size64,
2325
        },
2326
        "0C0080F2",
2327
        "movk x12, x12, #0",
2328
    ));
2329
    insns.push((
2330
        Inst::MovK {
2331
            rd: writable_xreg(19),
2332
            rn: xreg(19),
2333
            imm: MoveWideConst::maybe_with_shift(0x0000, 16).unwrap(),
2334
            size: OperandSize::Size64,
2335
        },
2336
        "1300A0F2",
2337
        "movk x19, x19, #0, LSL #16",
2338
    ));
2339
    insns.push((
2340
        Inst::MovK {
2341
            rd: writable_xreg(3),
2342
            rn: xreg(3),
2343
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2344
            size: OperandSize::Size64,
2345
        },
2346
        "E3FF9FF2",
2347
        "movk x3, x3, #65535",
2348
    ));
2349
    insns.push((
2350
        Inst::MovK {
2351
            rd: writable_xreg(8),
2352
            rn: xreg(8),
2353
            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2354
            size: OperandSize::Size64,
2355
        },
2356
        "E8FFBFF2",
2357
        "movk x8, x8, #65535, LSL #16",
2358
    ));
2359
    insns.push((
2360
        Inst::MovK {
2361
            rd: writable_xreg(8),
2362
            rn: xreg(8),
2363
            imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
2364
            size: OperandSize::Size64,
2365
        },
2366
        "E8FFDFF2",
2367
        "movk x8, x8, #65535, LSL #32",
2368
    ));
2369
    insns.push((
2370
        Inst::MovK {
2371
            rd: writable_xreg(8),
2372
            rn: xreg(8),
2373
            imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
2374
            size: OperandSize::Size64,
2375
        },
2376
        "E8FFFFF2",
2377
        "movk x8, x8, #65535, LSL #48",
2378
    ));
2379

2380
    insns.push((
2381
        Inst::CSel {
2382
            rd: writable_xreg(10),
2383
            rn: xreg(12),
2384
            rm: xreg(14),
2385
            cond: Cond::Hs,
2386
        },
2387
        "8A218E9A",
2388
        "csel x10, x12, x14, hs",
2389
    ));
2390
    insns.push((
2391
        Inst::CSNeg {
2392
            rd: writable_xreg(10),
2393
            rn: xreg(12),
2394
            rm: xreg(14),
2395
            cond: Cond::Hs,
2396
        },
2397
        "8A258EDA",
2398
        "csneg x10, x12, x14, hs",
2399
    ));
2400
    insns.push((
2401
        Inst::CSet {
2402
            rd: writable_xreg(15),
2403
            cond: Cond::Ge,
2404
        },
2405
        "EFB79F9A",
2406
        "cset x15, ge",
2407
    ));
2408
    insns.push((
2409
        Inst::CSetm {
2410
            rd: writable_xreg(0),
2411
            cond: Cond::Eq,
2412
        },
2413
        "E0139FDA",
2414
        "csetm x0, eq",
2415
    ));
2416
    insns.push((
2417
        Inst::CSetm {
2418
            rd: writable_xreg(16),
2419
            cond: Cond::Vs,
2420
        },
2421
        "F0739FDA",
2422
        "csetm x16, vs",
2423
    ));
2424
    insns.push((
2425
        Inst::CCmp {
2426
            size: OperandSize::Size64,
2427
            rn: xreg(22),
2428
            rm: xreg(1),
2429
            nzcv: NZCV::new(false, false, true, true),
2430
            cond: Cond::Eq,
2431
        },
2432
        "C30241FA",
2433
        "ccmp x22, x1, #nzCV, eq",
2434
    ));
2435
    insns.push((
2436
        Inst::CCmp {
2437
            size: OperandSize::Size32,
2438
            rn: xreg(3),
2439
            rm: xreg(28),
2440
            nzcv: NZCV::new(true, true, true, true),
2441
            cond: Cond::Gt,
2442
        },
2443
        "6FC05C7A",
2444
        "ccmp w3, w28, #NZCV, gt",
2445
    ));
2446
    insns.push((
2447
        Inst::CCmpImm {
2448
            size: OperandSize::Size64,
2449
            rn: xreg(22),
2450
            imm: UImm5::maybe_from_u8(5).unwrap(),
2451
            nzcv: NZCV::new(false, false, true, true),
2452
            cond: Cond::Eq,
2453
        },
2454
        "C30A45FA",
2455
        "ccmp x22, #5, #nzCV, eq",
2456
    ));
2457
    insns.push((
2458
        Inst::CCmpImm {
2459
            size: OperandSize::Size32,
2460
            rn: xreg(3),
2461
            imm: UImm5::maybe_from_u8(30).unwrap(),
2462
            nzcv: NZCV::new(true, true, true, true),
2463
            cond: Cond::Gt,
2464
        },
2465
        "6FC85E7A",
2466
        "ccmp w3, #30, #NZCV, gt",
2467
    ));
2468
    insns.push((
2469
        Inst::MovToFpu {
2470
            rd: writable_vreg(31),
2471
            rn: xreg(0),
2472
            size: ScalarSize::Size64,
2473
        },
2474
        "1F00679E",
2475
        "fmov d31, x0",
2476
    ));
2477
    insns.push((
2478
        Inst::MovToFpu {
2479
            rd: writable_vreg(1),
2480
            rn: xreg(28),
2481
            size: ScalarSize::Size32,
2482
        },
2483
        "8103271E",
2484
        "fmov s1, w28",
2485
    ));
2486
    insns.push((
2487
        Inst::FpuMoveFPImm {
2488
            rd: writable_vreg(31),
2489
            imm: ASIMDFPModImm::maybe_from_u64(f64::to_bits(1.0), ScalarSize::Size64).unwrap(),
2490
            size: ScalarSize::Size64,
2491
        },
2492
        "1F106E1E",
2493
        "fmov d31, #1",
2494
    ));
2495
    insns.push((
2496
        Inst::FpuMoveFPImm {
2497
            rd: writable_vreg(1),
2498
            imm: ASIMDFPModImm::maybe_from_u64(f32::to_bits(31.0).into(), ScalarSize::Size32)
2499
                .unwrap(),
2500
            size: ScalarSize::Size32,
2501
        },
2502
        "01F0271E",
2503
        "fmov s1, #31",
2504
    ));
2505
    insns.push((
2506
        Inst::MovToVec {
2507
            rd: writable_vreg(0),
2508
            ri: vreg(0),
2509
            rn: xreg(0),
2510
            idx: 7,
2511
            size: VectorSize::Size8x8,
2512
        },
2513
        "001C0F4E",
2514
        "mov v0.b[7], v0.b[7], w0",
2515
    ));
2516
    insns.push((
2517
        Inst::MovToVec {
2518
            rd: writable_vreg(20),
2519
            ri: vreg(20),
2520
            rn: xreg(21),
2521
            idx: 0,
2522
            size: VectorSize::Size64x2,
2523
        },
2524
        "B41E084E",
2525
        "mov v20.d[0], v20.d[0], x21",
2526
    ));
2527
    insns.push((
2528
        Inst::MovFromVec {
2529
            rd: writable_xreg(3),
2530
            rn: vreg(27),
2531
            idx: 14,
2532
            size: ScalarSize::Size8,
2533
        },
2534
        "633F1D0E",
2535
        "umov w3, v27.b[14]",
2536
    ));
2537
    insns.push((
2538
        Inst::MovFromVec {
2539
            rd: writable_xreg(24),
2540
            rn: vreg(5),
2541
            idx: 3,
2542
            size: ScalarSize::Size16,
2543
        },
2544
        "B83C0E0E",
2545
        "umov w24, v5.h[3]",
2546
    ));
2547
    insns.push((
2548
        Inst::MovFromVec {
2549
            rd: writable_xreg(12),
2550
            rn: vreg(17),
2551
            idx: 1,
2552
            size: ScalarSize::Size32,
2553
        },
2554
        "2C3E0C0E",
2555
        "mov w12, v17.s[1]",
2556
    ));
2557
    insns.push((
2558
        Inst::MovFromVec {
2559
            rd: writable_xreg(21),
2560
            rn: vreg(20),
2561
            idx: 0,
2562
            size: ScalarSize::Size64,
2563
        },
2564
        "953E084E",
2565
        "mov x21, v20.d[0]",
2566
    ));
2567
    insns.push((
2568
        Inst::MovFromVecSigned {
2569
            rd: writable_xreg(0),
2570
            rn: vreg(0),
2571
            idx: 15,
2572
            size: VectorSize::Size8x16,
2573
            scalar_size: OperandSize::Size32,
2574
        },
2575
        "002C1F0E",
2576
        "smov w0, v0.b[15]",
2577
    ));
2578
    insns.push((
2579
        Inst::MovFromVecSigned {
2580
            rd: writable_xreg(12),
2581
            rn: vreg(13),
2582
            idx: 7,
2583
            size: VectorSize::Size8x8,
2584
            scalar_size: OperandSize::Size64,
2585
        },
2586
        "AC2D0F4E",
2587
        "smov x12, v13.b[7]",
2588
    ));
2589
    insns.push((
2590
        Inst::MovFromVecSigned {
2591
            rd: writable_xreg(23),
2592
            rn: vreg(31),
2593
            idx: 7,
2594
            size: VectorSize::Size16x8,
2595
            scalar_size: OperandSize::Size32,
2596
        },
2597
        "F72F1E0E",
2598
        "smov w23, v31.h[7]",
2599
    ));
2600
    insns.push((
2601
        Inst::MovFromVecSigned {
2602
            rd: writable_xreg(24),
2603
            rn: vreg(5),
2604
            idx: 1,
2605
            size: VectorSize::Size32x2,
2606
            scalar_size: OperandSize::Size64,
2607
        },
2608
        "B82C0C4E",
2609
        "smov x24, v5.s[1]",
2610
    ));
2611
    insns.push((
2612
        Inst::MovToNZCV { rn: xreg(13) },
2613
        "0D421BD5",
2614
        "msr nzcv, x13",
2615
    ));
2616
    insns.push((
2617
        Inst::MovFromNZCV {
2618
            rd: writable_xreg(27),
2619
        },
2620
        "1B423BD5",
2621
        "mrs x27, nzcv",
2622
    ));
2623
    insns.push((
2624
        Inst::VecDup {
2625
            rd: writable_vreg(24),
2626
            rn: xreg(8),
2627
            size: VectorSize::Size8x8,
2628
        },
2629
        "180D010E",
2630
        "dup v24.8b, w8",
2631
    ));
2632
    insns.push((
2633
        Inst::VecDup {
2634
            rd: writable_vreg(25),
2635
            rn: xreg(7),
2636
            size: VectorSize::Size8x8,
2637
        },
2638
        "F90C010E",
2639
        "dup v25.8b, w7",
2640
    ));
2641
    insns.push((
2642
        Inst::VecDup {
2643
            rd: writable_vreg(1),
2644
            rn: xreg(22),
2645
            size: VectorSize::Size16x4,
2646
        },
2647
        "C10E020E",
2648
        "dup v1.4h, w22",
2649
    ));
2650
    insns.push((
2651
        Inst::VecDup {
2652
            rd: writable_vreg(2),
2653
            rn: xreg(23),
2654
            size: VectorSize::Size16x8,
2655
        },
2656
        "E20E024E",
2657
        "dup v2.8h, w23",
2658
    ));
2659
    insns.push((
2660
        Inst::VecDup {
2661
            rd: writable_vreg(30),
2662
            rn: xreg(28),
2663
            size: VectorSize::Size32x2,
2664
        },
2665
        "9E0F040E",
2666
        "dup v30.2s, w28",
2667
    ));
2668
    insns.push((
2669
        Inst::VecDup {
2670
            rd: writable_vreg(0),
2671
            rn: xreg(28),
2672
            size: VectorSize::Size32x2,
2673
        },
2674
        "800F040E",
2675
        "dup v0.2s, w28",
2676
    ));
2677
    insns.push((
2678
        Inst::VecDup {
2679
            rd: writable_vreg(31),
2680
            rn: xreg(5),
2681
            size: VectorSize::Size64x2,
2682
        },
2683
        "BF0C084E",
2684
        "dup v31.2d, x5",
2685
    ));
2686
    insns.push((
2687
        Inst::VecDupFromFpu {
2688
            rd: writable_vreg(14),
2689
            rn: vreg(19),
2690
            size: VectorSize::Size32x4,
2691
            lane: 0,
2692
        },
2693
        "6E06044E",
2694
        "dup v14.4s, v19.s[0]",
2695
    ));
2696
    insns.push((
2697
        Inst::VecDupFromFpu {
2698
            rd: writable_vreg(18),
2699
            rn: vreg(10),
2700
            size: VectorSize::Size64x2,
2701
            lane: 0,
2702
        },
2703
        "5205084E",
2704
        "dup v18.2d, v10.d[0]",
2705
    ));
2706
    insns.push((
2707
        Inst::VecDupFPImm {
2708
            rd: writable_vreg(31),
2709
            imm: ASIMDFPModImm::maybe_from_u64(1_f32.to_bits() as u64, ScalarSize::Size32).unwrap(),
2710
            size: VectorSize::Size32x2,
2711
        },
2712
        "1FF6030F",
2713
        "fmov v31.2s, #1",
2714
    ));
2715
    insns.push((
2716
        Inst::VecDupFPImm {
2717
            rd: writable_vreg(0),
2718
            imm: ASIMDFPModImm::maybe_from_u64(2_f64.to_bits(), ScalarSize::Size64).unwrap(),
2719
            size: VectorSize::Size64x2,
2720
        },
2721
        "00F4006F",
2722
        "fmov v0.2d, #2",
2723
    ));
2724
    insns.push((
2725
        Inst::VecDupImm {
2726
            rd: writable_vreg(31),
2727
            imm: ASIMDMovModImm::maybe_from_u64(255, ScalarSize::Size8).unwrap(),
2728
            invert: false,
2729
            size: VectorSize::Size8x16,
2730
        },
2731
        "FFE7074F",
2732
        "movi v31.16b, #255",
2733
    ));
2734
    insns.push((
2735
        Inst::VecDupImm {
2736
            rd: writable_vreg(30),
2737
            imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size16).unwrap(),
2738
            invert: false,
2739
            size: VectorSize::Size16x8,
2740
        },
2741
        "1E84004F",
2742
        "movi v30.8h, #0",
2743
    ));
2744
    insns.push((
2745
        Inst::VecDupImm {
2746
            rd: writable_vreg(0),
2747
            imm: ASIMDMovModImm::zero(ScalarSize::Size16),
2748
            invert: true,
2749
            size: VectorSize::Size16x4,
2750
        },
2751
        "0084002F",
2752
        "mvni v0.4h, #0",
2753
    ));
2754
    insns.push((
2755
        Inst::VecDupImm {
2756
            rd: writable_vreg(0),
2757
            imm: ASIMDMovModImm::maybe_from_u64(256, ScalarSize::Size16).unwrap(),
2758
            invert: false,
2759
            size: VectorSize::Size16x8,
2760
        },
2761
        "20A4004F",
2762
        "movi v0.8h, #1, LSL #8",
2763
    ));
2764
    insns.push((
2765
        Inst::VecDupImm {
2766
            rd: writable_vreg(8),
2767
            imm: ASIMDMovModImm::maybe_from_u64(2228223, ScalarSize::Size32).unwrap(),
2768
            invert: false,
2769
            size: VectorSize::Size32x4,
2770
        },
2771
        "28D4014F",
2772
        "movi v8.4s, #33, MSL #16",
2773
    ));
2774
    insns.push((
2775
        Inst::VecDupImm {
2776
            rd: writable_vreg(16),
2777
            imm: ASIMDMovModImm::maybe_from_u64(35071, ScalarSize::Size32).unwrap(),
2778
            invert: true,
2779
            size: VectorSize::Size32x2,
2780
        },
2781
        "10C5042F",
2782
        "mvni v16.2s, #136, MSL #8",
2783
    ));
2784
    insns.push((
2785
        Inst::VecDupImm {
2786
            rd: writable_vreg(1),
2787
            imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size32).unwrap(),
2788
            invert: false,
2789
            size: VectorSize::Size32x2,
2790
        },
2791
        "0104000F",
2792
        "movi v1.2s, #0",
2793
    ));
2794
    insns.push((
2795
        Inst::VecDupImm {
2796
            rd: writable_vreg(24),
2797
            imm: ASIMDMovModImm::maybe_from_u64(1107296256, ScalarSize::Size32).unwrap(),
2798
            invert: false,
2799
            size: VectorSize::Size32x4,
2800
        },
2801
        "5864024F",
2802
        "movi v24.4s, #66, LSL #24",
2803
    ));
2804
    insns.push((
2805
        Inst::VecDupImm {
2806
            rd: writable_vreg(8),
2807
            imm: ASIMDMovModImm::zero(ScalarSize::Size64),
2808
            invert: false,
2809
            size: VectorSize::Size64x2,
2810
        },
2811
        "08E4006F",
2812
        "movi v8.2d, #0",
2813
    ));
2814
    insns.push((
2815
        Inst::VecDupImm {
2816
            rd: writable_vreg(7),
2817
            imm: ASIMDMovModImm::maybe_from_u64(18374687574904995840, ScalarSize::Size64).unwrap(),
2818
            invert: false,
2819
            size: VectorSize::Size64x2,
2820
        },
2821
        "87E6046F",
2822
        "movi v7.2d, #18374687574904995840",
2823
    ));
2824
    insns.push((
2825
        Inst::VecExtend {
2826
            t: VecExtendOp::Sxtl,
2827
            rd: writable_vreg(4),
2828
            rn: vreg(27),
2829
            high_half: false,
2830
            lane_size: ScalarSize::Size16,
2831
        },
2832
        "64A7080F",
2833
        "sxtl v4.8h, v27.8b",
2834
    ));
2835
    insns.push((
2836
        Inst::VecExtend {
2837
            t: VecExtendOp::Sxtl,
2838
            rd: writable_vreg(17),
2839
            rn: vreg(19),
2840
            high_half: true,
2841
            lane_size: ScalarSize::Size32,
2842
        },
2843
        "71A6104F",
2844
        "sxtl2 v17.4s, v19.8h",
2845
    ));
2846
    insns.push((
2847
        Inst::VecExtend {
2848
            t: VecExtendOp::Sxtl,
2849
            rd: writable_vreg(30),
2850
            rn: vreg(6),
2851
            high_half: false,
2852
            lane_size: ScalarSize::Size64,
2853
        },
2854
        "DEA4200F",
2855
        "sxtl v30.2d, v6.2s",
2856
    ));
2857
    insns.push((
2858
        Inst::VecExtend {
2859
            t: VecExtendOp::Uxtl,
2860
            rd: writable_vreg(3),
2861
            rn: vreg(29),
2862
            high_half: true,
2863
            lane_size: ScalarSize::Size16,
2864
        },
2865
        "A3A7086F",
2866
        "uxtl2 v3.8h, v29.16b",
2867
    ));
2868
    insns.push((
2869
        Inst::VecExtend {
2870
            t: VecExtendOp::Uxtl,
2871
            rd: writable_vreg(15),
2872
            rn: vreg(12),
2873
            high_half: false,
2874
            lane_size: ScalarSize::Size32,
2875
        },
2876
        "8FA5102F",
2877
        "uxtl v15.4s, v12.4h",
2878
    ));
2879
    insns.push((
2880
        Inst::VecExtend {
2881
            t: VecExtendOp::Uxtl,
2882
            rd: writable_vreg(28),
2883
            rn: vreg(2),
2884
            high_half: true,
2885
            lane_size: ScalarSize::Size64,
2886
        },
2887
        "5CA4206F",
2888
        "uxtl2 v28.2d, v2.4s",
2889
    ));
2890

2891
    insns.push((
2892
        Inst::VecMovElement {
2893
            rd: writable_vreg(0),
2894
            ri: vreg(0),
2895
            rn: vreg(31),
2896
            dest_idx: 7,
2897
            src_idx: 7,
2898
            size: VectorSize::Size16x8,
2899
        },
2900
        "E0771E6E",
2901
        "mov v0.h[7], v0.h[7], v31.h[7]",
2902
    ));
2903

2904
    insns.push((
2905
        Inst::VecMovElement {
2906
            rd: writable_vreg(31),
2907
            ri: vreg(31),
2908
            rn: vreg(16),
2909
            dest_idx: 1,
2910
            src_idx: 0,
2911
            size: VectorSize::Size32x2,
2912
        },
2913
        "1F060C6E",
2914
        "mov v31.s[1], v31.s[1], v16.s[0]",
2915
    ));
2916

2917
    insns.push((
2918
        Inst::VecRRLong {
2919
            op: VecRRLongOp::Fcvtl16,
2920
            rd: writable_vreg(0),
2921
            rn: vreg(30),
2922
            high_half: false,
2923
        },
2924
        "C07B210E",
2925
        "fcvtl v0.4s, v30.4h",
2926
    ));
2927

2928
    insns.push((
2929
        Inst::VecRRLong {
2930
            op: VecRRLongOp::Fcvtl32,
2931
            rd: writable_vreg(16),
2932
            rn: vreg(1),
2933
            high_half: true,
2934
        },
2935
        "3078614E",
2936
        "fcvtl2 v16.2d, v1.4s",
2937
    ));
2938

2939
    insns.push((
2940
        Inst::VecRRLong {
2941
            op: VecRRLongOp::Shll8,
2942
            rd: writable_vreg(12),
2943
            rn: vreg(5),
2944
            high_half: false,
2945
        },
2946
        "AC38212E",
2947
        "shll v12.8h, v5.8b, #8",
2948
    ));
2949

2950
    insns.push((
2951
        Inst::VecRRLong {
2952
            op: VecRRLongOp::Shll16,
2953
            rd: writable_vreg(9),
2954
            rn: vreg(1),
2955
            high_half: true,
2956
        },
2957
        "2938616E",
2958
        "shll2 v9.4s, v1.8h, #16",
2959
    ));
2960

2961
    insns.push((
2962
        Inst::VecRRLong {
2963
            op: VecRRLongOp::Shll32,
2964
            rd: writable_vreg(1),
2965
            rn: vreg(10),
2966
            high_half: false,
2967
        },
2968
        "4139A12E",
2969
        "shll v1.2d, v10.2s, #32",
2970
    ));
2971

2972
    insns.push((
2973
        Inst::VecRRNarrowLow {
2974
            op: VecRRNarrowOp::Xtn,
2975
            rd: writable_vreg(25),
2976
            rn: vreg(17),
2977
            lane_size: ScalarSize::Size8,
2978
        },
2979
        "392A210E",
2980
        "xtn v25.8b, v17.8h",
2981
    ));
2982

2983
    insns.push((
2984
        Inst::VecRRNarrowHigh {
2985
            op: VecRRNarrowOp::Xtn,
2986
            rd: writable_vreg(3),
2987
            ri: vreg(3),
2988
            rn: vreg(10),
2989
            lane_size: ScalarSize::Size16,
2990
        },
2991
        "4329614E",
2992
        "xtn2 v3.8h, v3.8h, v10.4s",
2993
    ));
2994

2995
    insns.push((
2996
        Inst::VecRRNarrowLow {
2997
            op: VecRRNarrowOp::Xtn,
2998
            rd: writable_vreg(22),
2999
            rn: vreg(8),
3000
            lane_size: ScalarSize::Size32,
3001
        },
3002
        "1629A10E",
3003
        "xtn v22.2s, v8.2d",
3004
    ));
3005

3006
    insns.push((
3007
        Inst::VecRRNarrowHigh {
3008
            op: VecRRNarrowOp::Sqxtn,
3009
            rd: writable_vreg(7),
3010
            ri: vreg(7),
3011
            rn: vreg(22),
3012
            lane_size: ScalarSize::Size8,
3013
        },
3014
        "C74A214E",
3015
        "sqxtn2 v7.16b, v7.16b, v22.8h",
3016
    ));
3017

3018
    insns.push((
3019
        Inst::VecRRNarrowHigh {
3020
            op: VecRRNarrowOp::Sqxtn,
3021
            rd: writable_vreg(31),
3022
            ri: vreg(31),
3023
            rn: vreg(0),
3024
            lane_size: ScalarSize::Size16,
3025
        },
3026
        "1F48614E",
3027
        "sqxtn2 v31.8h, v31.8h, v0.4s",
3028
    ));
3029

3030
    insns.push((
3031
        Inst::VecRRNarrowLow {
3032
            op: VecRRNarrowOp::Sqxtn,
3033
            rd: writable_vreg(14),
3034
            rn: vreg(20),
3035
            lane_size: ScalarSize::Size32,
3036
        },
3037
        "8E4AA10E",
3038
        "sqxtn v14.2s, v20.2d",
3039
    ));
3040

3041
    insns.push((
3042
        Inst::VecRRNarrowLow {
3043
            op: VecRRNarrowOp::Sqxtun,
3044
            rd: writable_vreg(16),
3045
            rn: vreg(23),
3046
            lane_size: ScalarSize::Size8,
3047
        },
3048
        "F02A212E",
3049
        "sqxtun v16.8b, v23.8h",
3050
    ));
3051

3052
    insns.push((
3053
        Inst::VecRRNarrowHigh {
3054
            op: VecRRNarrowOp::Sqxtun,
3055
            rd: writable_vreg(28),
3056
            ri: vreg(28),
3057
            rn: vreg(9),
3058
            lane_size: ScalarSize::Size16,
3059
        },
3060
        "3C29616E",
3061
        "sqxtun2 v28.8h, v28.8h, v9.4s",
3062
    ));
3063

3064
    insns.push((
3065
        Inst::VecRRNarrowLow {
3066
            op: VecRRNarrowOp::Sqxtun,
3067
            rd: writable_vreg(15),
3068
            rn: vreg(15),
3069
            lane_size: ScalarSize::Size32,
3070
        },
3071
        "EF29A12E",
3072
        "sqxtun v15.2s, v15.2d",
3073
    ));
3074

3075
    insns.push((
3076
        Inst::VecRRNarrowHigh {
3077
            op: VecRRNarrowOp::Uqxtn,
3078
            rd: writable_vreg(21),
3079
            ri: vreg(21),
3080
            rn: vreg(4),
3081
            lane_size: ScalarSize::Size8,
3082
        },
3083
        "9548216E",
3084
        "uqxtn2 v21.16b, v21.16b, v4.8h",
3085
    ));
3086

3087
    insns.push((
3088
        Inst::VecRRNarrowLow {
3089
            op: VecRRNarrowOp::Uqxtn,
3090
            rd: writable_vreg(31),
3091
            rn: vreg(31),
3092
            lane_size: ScalarSize::Size16,
3093
        },
3094
        "FF4B612E",
3095
        "uqxtn v31.4h, v31.4s",
3096
    ));
3097

3098
    insns.push((
3099
        Inst::VecRRNarrowHigh {
3100
            op: VecRRNarrowOp::Uqxtn,
3101
            rd: writable_vreg(11),
3102
            ri: vreg(11),
3103
            rn: vreg(12),
3104
            lane_size: ScalarSize::Size32,
3105
        },
3106
        "8B49A16E",
3107
        "uqxtn2 v11.4s, v11.4s, v12.2d",
3108
    ));
3109

3110
    insns.push((
3111
        Inst::VecRRNarrowLow {
3112
            op: VecRRNarrowOp::Fcvtn,
3113
            rd: writable_vreg(0),
3114
            rn: vreg(0),
3115
            lane_size: ScalarSize::Size16,
3116
        },
3117
        "0068210E",
3118
        "fcvtn v0.4h, v0.4s",
3119
    ));
3120

3121
    insns.push((
3122
        Inst::VecRRNarrowLow {
3123
            op: VecRRNarrowOp::Fcvtn,
3124
            rd: writable_vreg(2),
3125
            rn: vreg(7),
3126
            lane_size: ScalarSize::Size32,
3127
        },
3128
        "E268610E",
3129
        "fcvtn v2.2s, v7.2d",
3130
    ));
3131

3132
    insns.push((
3133
        Inst::VecRRNarrowHigh {
3134
            op: VecRRNarrowOp::Fcvtn,
3135
            rd: writable_vreg(31),
3136
            ri: vreg(31),
3137
            rn: vreg(30),
3138
            lane_size: ScalarSize::Size32,
3139
        },
3140
        "DF6B614E",
3141
        "fcvtn2 v31.4s, v31.4s, v30.2d",
3142
    ));
3143

3144
    insns.push((
3145
        Inst::VecRRPair {
3146
            op: VecPairOp::Addp,
3147
            rd: writable_vreg(0),
3148
            rn: vreg(30),
3149
        },
3150
        "C0BBF15E",
3151
        "addp d0, v30.2d",
3152
    ));
3153

3154
    insns.push((
3155
        Inst::VecRRPairLong {
3156
            op: VecRRPairLongOp::Uaddlp8,
3157
            rd: writable_vreg(0),
3158
            rn: vreg(1),
3159
        },
3160
        "2028206E",
3161
        "uaddlp v0.8h, v1.16b",
3162
    ));
3163

3164
    insns.push((
3165
        Inst::VecRRPairLong {
3166
            op: VecRRPairLongOp::Saddlp8,
3167
            rd: writable_vreg(3),
3168
            rn: vreg(11),
3169
        },
3170
        "6329204E",
3171
        "saddlp v3.8h, v11.16b",
3172
    ));
3173

3174
    insns.push((
3175
        Inst::VecRRPairLong {
3176
            op: VecRRPairLongOp::Uaddlp16,
3177
            rd: writable_vreg(14),
3178
            rn: vreg(23),
3179
        },
3180
        "EE2A606E",
3181
        "uaddlp v14.4s, v23.8h",
3182
    ));
3183

3184
    insns.push((
3185
        Inst::VecRRPairLong {
3186
            op: VecRRPairLongOp::Saddlp16,
3187
            rd: writable_vreg(29),
3188
            rn: vreg(0),
3189
        },
3190
        "1D28604E",
3191
        "saddlp v29.4s, v0.8h",
3192
    ));
3193

3194
    insns.push((
3195
        Inst::VecRRR {
3196
            alu_op: VecALUOp::Sqadd,
3197
            rd: writable_vreg(1),
3198
            rn: vreg(2),
3199
            rm: vreg(8),
3200
            size: VectorSize::Size8x16,
3201
        },
3202
        "410C284E",
3203
        "sqadd v1.16b, v2.16b, v8.16b",
3204
    ));
3205

3206
    insns.push((
3207
        Inst::VecRRR {
3208
            alu_op: VecALUOp::Sqadd,
3209
            rd: writable_vreg(1),
3210
            rn: vreg(12),
3211
            rm: vreg(28),
3212
            size: VectorSize::Size16x8,
3213
        },
3214
        "810D7C4E",
3215
        "sqadd v1.8h, v12.8h, v28.8h",
3216
    ));
3217

3218
    insns.push((
3219
        Inst::VecRRR {
3220
            alu_op: VecALUOp::Sqadd,
3221
            rd: writable_vreg(12),
3222
            rn: vreg(2),
3223
            rm: vreg(6),
3224
            size: VectorSize::Size32x4,
3225
        },
3226
        "4C0CA64E",
3227
        "sqadd v12.4s, v2.4s, v6.4s",
3228
    ));
3229

3230
    insns.push((
3231
        Inst::VecRRR {
3232
            alu_op: VecALUOp::Sqadd,
3233
            rd: writable_vreg(20),
3234
            rn: vreg(7),
3235
            rm: vreg(13),
3236
            size: VectorSize::Size64x2,
3237
        },
3238
        "F40CED4E",
3239
        "sqadd v20.2d, v7.2d, v13.2d",
3240
    ));
3241

3242
    insns.push((
3243
        Inst::VecRRR {
3244
            alu_op: VecALUOp::Sqsub,
3245
            rd: writable_vreg(1),
3246
            rn: vreg(2),
3247
            rm: vreg(8),
3248
            size: VectorSize::Size8x16,
3249
        },
3250
        "412C284E",
3251
        "sqsub v1.16b, v2.16b, v8.16b",
3252
    ));
3253

3254
    insns.push((
3255
        Inst::VecRRR {
3256
            alu_op: VecALUOp::Sqsub,
3257
            rd: writable_vreg(1),
3258
            rn: vreg(12),
3259
            rm: vreg(28),
3260
            size: VectorSize::Size16x8,
3261
        },
3262
        "812D7C4E",
3263
        "sqsub v1.8h, v12.8h, v28.8h",
3264
    ));
3265

3266
    insns.push((
3267
        Inst::VecRRR {
3268
            alu_op: VecALUOp::Sqsub,
3269
            rd: writable_vreg(12),
3270
            rn: vreg(2),
3271
            rm: vreg(6),
3272
            size: VectorSize::Size32x4,
3273
        },
3274
        "4C2CA64E",
3275
        "sqsub v12.4s, v2.4s, v6.4s",
3276
    ));
3277

3278
    insns.push((
3279
        Inst::VecRRR {
3280
            alu_op: VecALUOp::Sqsub,
3281
            rd: writable_vreg(20),
3282
            rn: vreg(7),
3283
            rm: vreg(13),
3284
            size: VectorSize::Size64x2,
3285
        },
3286
        "F42CED4E",
3287
        "sqsub v20.2d, v7.2d, v13.2d",
3288
    ));
3289

3290
    insns.push((
3291
        Inst::VecRRR {
3292
            alu_op: VecALUOp::Uqadd,
3293
            rd: writable_vreg(1),
3294
            rn: vreg(2),
3295
            rm: vreg(8),
3296
            size: VectorSize::Size8x16,
3297
        },
3298
        "410C286E",
3299
        "uqadd v1.16b, v2.16b, v8.16b",
3300
    ));
3301

3302
    insns.push((
3303
        Inst::VecRRR {
3304
            alu_op: VecALUOp::Uqadd,
3305
            rd: writable_vreg(1),
3306
            rn: vreg(12),
3307
            rm: vreg(28),
3308
            size: VectorSize::Size16x8,
3309
        },
3310
        "810D7C6E",
3311
        "uqadd v1.8h, v12.8h, v28.8h",
3312
    ));
3313

3314
    insns.push((
3315
        Inst::VecRRR {
3316
            alu_op: VecALUOp::Uqadd,
3317
            rd: writable_vreg(12),
3318
            rn: vreg(2),
3319
            rm: vreg(6),
3320
            size: VectorSize::Size32x4,
3321
        },
3322
        "4C0CA66E",
3323
        "uqadd v12.4s, v2.4s, v6.4s",
3324
    ));
3325

3326
    insns.push((
3327
        Inst::VecRRR {
3328
            alu_op: VecALUOp::Uqadd,
3329
            rd: writable_vreg(20),
3330
            rn: vreg(7),
3331
            rm: vreg(13),
3332
            size: VectorSize::Size64x2,
3333
        },
3334
        "F40CED6E",
3335
        "uqadd v20.2d, v7.2d, v13.2d",
3336
    ));
3337

3338
    insns.push((
3339
        Inst::VecRRR {
3340
            alu_op: VecALUOp::Uqsub,
3341
            rd: writable_vreg(1),
3342
            rn: vreg(2),
3343
            rm: vreg(8),
3344
            size: VectorSize::Size8x16,
3345
        },
3346
        "412C286E",
3347
        "uqsub v1.16b, v2.16b, v8.16b",
3348
    ));
3349

3350
    insns.push((
3351
        Inst::VecRRR {
3352
            alu_op: VecALUOp::Uqsub,
3353
            rd: writable_vreg(1),
3354
            rn: vreg(12),
3355
            rm: vreg(28),
3356
            size: VectorSize::Size16x8,
3357
        },
3358
        "812D7C6E",
3359
        "uqsub v1.8h, v12.8h, v28.8h",
3360
    ));
3361

3362
    insns.push((
3363
        Inst::VecRRR {
3364
            alu_op: VecALUOp::Uqsub,
3365
            rd: writable_vreg(12),
3366
            rn: vreg(2),
3367
            rm: vreg(6),
3368
            size: VectorSize::Size32x4,
3369
        },
3370
        "4C2CA66E",
3371
        "uqsub v12.4s, v2.4s, v6.4s",
3372
    ));
3373

3374
    insns.push((
3375
        Inst::VecRRR {
3376
            alu_op: VecALUOp::Uqsub,
3377
            rd: writable_vreg(20),
3378
            rn: vreg(7),
3379
            rm: vreg(13),
3380
            size: VectorSize::Size64x2,
3381
        },
3382
        "F42CED6E",
3383
        "uqsub v20.2d, v7.2d, v13.2d",
3384
    ));
3385

3386
    insns.push((
3387
        Inst::VecRRR {
3388
            alu_op: VecALUOp::Cmeq,
3389
            rd: writable_vreg(3),
3390
            rn: vreg(23),
3391
            rm: vreg(24),
3392
            size: VectorSize::Size8x16,
3393
        },
3394
        "E38E386E",
3395
        "cmeq v3.16b, v23.16b, v24.16b",
3396
    ));
3397

3398
    insns.push((
3399
        Inst::VecRRR {
3400
            alu_op: VecALUOp::Cmgt,
3401
            rd: writable_vreg(3),
3402
            rn: vreg(23),
3403
            rm: vreg(24),
3404
            size: VectorSize::Size8x16,
3405
        },
3406
        "E336384E",
3407
        "cmgt v3.16b, v23.16b, v24.16b",
3408
    ));
3409

3410
    insns.push((
3411
        Inst::VecRRR {
3412
            alu_op: VecALUOp::Cmge,
3413
            rd: writable_vreg(23),
3414
            rn: vreg(9),
3415
            rm: vreg(12),
3416
            size: VectorSize::Size8x16,
3417
        },
3418
        "373D2C4E",
3419
        "cmge v23.16b, v9.16b, v12.16b",
3420
    ));
3421

3422
    insns.push((
3423
        Inst::VecRRR {
3424
            alu_op: VecALUOp::Cmhi,
3425
            rd: writable_vreg(5),
3426
            rn: vreg(1),
3427
            rm: vreg(1),
3428
            size: VectorSize::Size8x16,
3429
        },
3430
        "2534216E",
3431
        "cmhi v5.16b, v1.16b, v1.16b",
3432
    ));
3433

3434
    insns.push((
3435
        Inst::VecRRR {
3436
            alu_op: VecALUOp::Cmhs,
3437
            rd: writable_vreg(8),
3438
            rn: vreg(2),
3439
            rm: vreg(15),
3440
            size: VectorSize::Size8x16,
3441
        },
3442
        "483C2F6E",
3443
        "cmhs v8.16b, v2.16b, v15.16b",
3444
    ));
3445

3446
    insns.push((
3447
        Inst::VecRRR {
3448
            alu_op: VecALUOp::Cmeq,
3449
            rd: writable_vreg(3),
3450
            rn: vreg(23),
3451
            rm: vreg(24),
3452
            size: VectorSize::Size16x8,
3453
        },
3454
        "E38E786E",
3455
        "cmeq v3.8h, v23.8h, v24.8h",
3456
    ));
3457

3458
    insns.push((
3459
        Inst::VecRRR {
3460
            alu_op: VecALUOp::Cmgt,
3461
            rd: writable_vreg(3),
3462
            rn: vreg(23),
3463
            rm: vreg(24),
3464
            size: VectorSize::Size16x8,
3465
        },
3466
        "E336784E",
3467
        "cmgt v3.8h, v23.8h, v24.8h",
3468
    ));
3469

3470
    insns.push((
3471
        Inst::VecRRR {
3472
            alu_op: VecALUOp::Cmge,
3473
            rd: writable_vreg(23),
3474
            rn: vreg(9),
3475
            rm: vreg(12),
3476
            size: VectorSize::Size16x8,
3477
        },
3478
        "373D6C4E",
3479
        "cmge v23.8h, v9.8h, v12.8h",
3480
    ));
3481

3482
    insns.push((
3483
        Inst::VecRRR {
3484
            alu_op: VecALUOp::Cmhi,
3485
            rd: writable_vreg(5),
3486
            rn: vreg(1),
3487
            rm: vreg(1),
3488
            size: VectorSize::Size16x8,
3489
        },
3490
        "2534616E",
3491
        "cmhi v5.8h, v1.8h, v1.8h",
3492
    ));
3493

3494
    insns.push((
3495
        Inst::VecRRR {
3496
            alu_op: VecALUOp::Cmhs,
3497
            rd: writable_vreg(8),
3498
            rn: vreg(2),
3499
            rm: vreg(15),
3500
            size: VectorSize::Size16x8,
3501
        },
3502
        "483C6F6E",
3503
        "cmhs v8.8h, v2.8h, v15.8h",
3504
    ));
3505

3506
    insns.push((
3507
        Inst::VecRRR {
3508
            alu_op: VecALUOp::Cmeq,
3509
            rd: writable_vreg(3),
3510
            rn: vreg(23),
3511
            rm: vreg(24),
3512
            size: VectorSize::Size32x4,
3513
        },
3514
        "E38EB86E",
3515
        "cmeq v3.4s, v23.4s, v24.4s",
3516
    ));
3517

3518
    insns.push((
3519
        Inst::VecRRR {
3520
            alu_op: VecALUOp::Cmgt,
3521
            rd: writable_vreg(3),
3522
            rn: vreg(23),
3523
            rm: vreg(24),
3524
            size: VectorSize::Size32x4,
3525
        },
3526
        "E336B84E",
3527
        "cmgt v3.4s, v23.4s, v24.4s",
3528
    ));
3529

3530
    insns.push((
3531
        Inst::VecRRR {
3532
            alu_op: VecALUOp::Cmge,
3533
            rd: writable_vreg(23),
3534
            rn: vreg(9),
3535
            rm: vreg(12),
3536
            size: VectorSize::Size32x4,
3537
        },
3538
        "373DAC4E",
3539
        "cmge v23.4s, v9.4s, v12.4s",
3540
    ));
3541

3542
    insns.push((
3543
        Inst::VecRRR {
3544
            alu_op: VecALUOp::Cmhi,
3545
            rd: writable_vreg(5),
3546
            rn: vreg(1),
3547
            rm: vreg(1),
3548
            size: VectorSize::Size32x4,
3549
        },
3550
        "2534A16E",
3551
        "cmhi v5.4s, v1.4s, v1.4s",
3552
    ));
3553

3554
    insns.push((
3555
        Inst::VecRRR {
3556
            alu_op: VecALUOp::Cmhs,
3557
            rd: writable_vreg(8),
3558
            rn: vreg(2),
3559
            rm: vreg(15),
3560
            size: VectorSize::Size32x4,
3561
        },
3562
        "483CAF6E",
3563
        "cmhs v8.4s, v2.4s, v15.4s",
3564
    ));
3565

3566
    insns.push((
3567
        Inst::VecRRR {
3568
            alu_op: VecALUOp::Fcmeq,
3569
            rd: writable_vreg(28),
3570
            rn: vreg(12),
3571
            rm: vreg(4),
3572
            size: VectorSize::Size32x2,
3573
        },
3574
        "9CE5240E",
3575
        "fcmeq v28.2s, v12.2s, v4.2s",
3576
    ));
3577

3578
    insns.push((
3579
        Inst::VecRRR {
3580
            alu_op: VecALUOp::Fcmgt,
3581
            rd: writable_vreg(3),
3582
            rn: vreg(16),
3583
            rm: vreg(31),
3584
            size: VectorSize::Size64x2,
3585
        },
3586
        "03E6FF6E",
3587
        "fcmgt v3.2d, v16.2d, v31.2d",
3588
    ));
3589

3590
    insns.push((
3591
        Inst::VecRRR {
3592
            alu_op: VecALUOp::Fcmge,
3593
            rd: writable_vreg(18),
3594
            rn: vreg(23),
3595
            rm: vreg(0),
3596
            size: VectorSize::Size64x2,
3597
        },
3598
        "F2E6606E",
3599
        "fcmge v18.2d, v23.2d, v0.2d",
3600
    ));
3601

3602
    insns.push((
3603
        Inst::VecRRR {
3604
            alu_op: VecALUOp::And,
3605
            rd: writable_vreg(20),
3606
            rn: vreg(19),
3607
            rm: vreg(18),
3608
            size: VectorSize::Size32x4,
3609
        },
3610
        "741E324E",
3611
        "and v20.16b, v19.16b, v18.16b",
3612
    ));
3613

3614
    insns.push((
3615
        Inst::VecRRR {
3616
            alu_op: VecALUOp::Bic,
3617
            rd: writable_vreg(8),
3618
            rn: vreg(11),
3619
            rm: vreg(1),
3620
            size: VectorSize::Size8x16,
3621
        },
3622
        "681D614E",
3623
        "bic v8.16b, v11.16b, v1.16b",
3624
    ));
3625

3626
    insns.push((
3627
        Inst::VecRRR {
3628
            alu_op: VecALUOp::Orr,
3629
            rd: writable_vreg(15),
3630
            rn: vreg(2),
3631
            rm: vreg(12),
3632
            size: VectorSize::Size16x8,
3633
        },
3634
        "4F1CAC4E",
3635
        "orr v15.16b, v2.16b, v12.16b",
3636
    ));
3637

3638
    insns.push((
3639
        Inst::VecRRR {
3640
            alu_op: VecALUOp::Eor,
3641
            rd: writable_vreg(18),
3642
            rn: vreg(3),
3643
            rm: vreg(22),
3644
            size: VectorSize::Size8x16,
3645
        },
3646
        "721C366E",
3647
        "eor v18.16b, v3.16b, v22.16b",
3648
    ));
3649

3650
    insns.push((
3651
        Inst::VecRRRMod {
3652
            alu_op: VecALUModOp::Bsl,
3653
            rd: writable_vreg(8),
3654
            ri: vreg(8),
3655
            rn: vreg(9),
3656
            rm: vreg(1),
3657
            size: VectorSize::Size8x16,
3658
        },
3659
        "281D616E",
3660
        "bsl v8.16b, v8.16b, v9.16b, v1.16b",
3661
    ));
3662

3663
    insns.push((
3664
        Inst::VecRRR {
3665
            alu_op: VecALUOp::Umaxp,
3666
            rd: writable_vreg(8),
3667
            rn: vreg(12),
3668
            rm: vreg(1),
3669
            size: VectorSize::Size8x16,
3670
        },
3671
        "88A5216E",
3672
        "umaxp v8.16b, v12.16b, v1.16b",
3673
    ));
3674

3675
    insns.push((
3676
        Inst::VecRRR {
3677
            alu_op: VecALUOp::Umaxp,
3678
            rd: writable_vreg(1),
3679
            rn: vreg(6),
3680
            rm: vreg(1),
3681
            size: VectorSize::Size16x8,
3682
        },
3683
        "C1A4616E",
3684
        "umaxp v1.8h, v6.8h, v1.8h",
3685
    ));
3686

3687
    insns.push((
3688
        Inst::VecRRR {
3689
            alu_op: VecALUOp::Umaxp,
3690
            rd: writable_vreg(1),
3691
            rn: vreg(20),
3692
            rm: vreg(16),
3693
            size: VectorSize::Size32x4,
3694
        },
3695
        "81A6B06E",
3696
        "umaxp v1.4s, v20.4s, v16.4s",
3697
    ));
3698

3699
    insns.push((
3700
        Inst::VecRRR {
3701
            alu_op: VecALUOp::Add,
3702
            rd: writable_vreg(5),
3703
            rn: vreg(1),
3704
            rm: vreg(1),
3705
            size: VectorSize::Size8x16,
3706
        },
3707
        "2584214E",
3708
        "add v5.16b, v1.16b, v1.16b",
3709
    ));
3710

3711
    insns.push((
3712
        Inst::VecRRR {
3713
            alu_op: VecALUOp::Add,
3714
            rd: writable_vreg(7),
3715
            rn: vreg(13),
3716
            rm: vreg(2),
3717
            size: VectorSize::Size16x8,
3718
        },
3719
        "A785624E",
3720
        "add v7.8h, v13.8h, v2.8h",
3721
    ));
3722

3723
    insns.push((
3724
        Inst::VecRRR {
3725
            alu_op: VecALUOp::Add,
3726
            rd: writable_vreg(18),
3727
            rn: vreg(9),
3728
            rm: vreg(6),
3729
            size: VectorSize::Size32x4,
3730
        },
3731
        "3285A64E",
3732
        "add v18.4s, v9.4s, v6.4s",
3733
    ));
3734

3735
    insns.push((
3736
        Inst::VecRRR {
3737
            alu_op: VecALUOp::Add,
3738
            rd: writable_vreg(1),
3739
            rn: vreg(3),
3740
            rm: vreg(2),
3741
            size: VectorSize::Size64x2,
3742
        },
3743
        "6184E24E",
3744
        "add v1.2d, v3.2d, v2.2d",
3745
    ));
3746

3747
    insns.push((
3748
        Inst::VecRRR {
3749
            alu_op: VecALUOp::Sub,
3750
            rd: writable_vreg(5),
3751
            rn: vreg(1),
3752
            rm: vreg(1),
3753
            size: VectorSize::Size8x16,
3754
        },
3755
        "2584216E",
3756
        "sub v5.16b, v1.16b, v1.16b",
3757
    ));
3758

3759
    insns.push((
3760
        Inst::VecRRR {
3761
            alu_op: VecALUOp::Sub,
3762
            rd: writable_vreg(7),
3763
            rn: vreg(13),
3764
            rm: vreg(2),
3765
            size: VectorSize::Size16x8,
3766
        },
3767
        "A785626E",
3768
        "sub v7.8h, v13.8h, v2.8h",
3769
    ));
3770

3771
    insns.push((
3772
        Inst::VecRRR {
3773
            alu_op: VecALUOp::Sub,
3774
            rd: writable_vreg(18),
3775
            rn: vreg(9),
3776
            rm: vreg(6),
3777
            size: VectorSize::Size32x4,
3778
        },
3779
        "3285A66E",
3780
        "sub v18.4s, v9.4s, v6.4s",
3781
    ));
3782

3783
    insns.push((
3784
        Inst::VecRRR {
3785
            alu_op: VecALUOp::Sub,
3786
            rd: writable_vreg(18),
3787
            rn: vreg(0),
3788
            rm: vreg(8),
3789
            size: VectorSize::Size64x2,
3790
        },
3791
        "1284E86E",
3792
        "sub v18.2d, v0.2d, v8.2d",
3793
    ));
3794

3795
    insns.push((
3796
        Inst::VecRRR {
3797
            alu_op: VecALUOp::Mul,
3798
            rd: writable_vreg(25),
3799
            rn: vreg(9),
3800
            rm: vreg(8),
3801
            size: VectorSize::Size8x16,
3802
        },
3803
        "399D284E",
3804
        "mul v25.16b, v9.16b, v8.16b",
3805
    ));
3806

3807
    insns.push((
3808
        Inst::VecRRR {
3809
            alu_op: VecALUOp::Mul,
3810
            rd: writable_vreg(30),
3811
            rn: vreg(30),
3812
            rm: vreg(12),
3813
            size: VectorSize::Size16x8,
3814
        },
3815
        "DE9F6C4E",
3816
        "mul v30.8h, v30.8h, v12.8h",
3817
    ));
3818

3819
    insns.push((
3820
        Inst::VecRRR {
3821
            alu_op: VecALUOp::Mul,
3822
            rd: writable_vreg(18),
3823
            rn: vreg(18),
3824
            rm: vreg(18),
3825
            size: VectorSize::Size32x4,
3826
        },
3827
        "529EB24E",
3828
        "mul v18.4s, v18.4s, v18.4s",
3829
    ));
3830

3831
    insns.push((
3832
        Inst::VecRRR {
3833
            alu_op: VecALUOp::Ushl,
3834
            rd: writable_vreg(18),
3835
            rn: vreg(18),
3836
            rm: vreg(18),
3837
            size: VectorSize::Size8x16,
3838
        },
3839
        "5246326E",
3840
        "ushl v18.16b, v18.16b, v18.16b",
3841
    ));
3842

3843
    insns.push((
3844
        Inst::VecRRR {
3845
            alu_op: VecALUOp::Ushl,
3846
            rd: writable_vreg(18),
3847
            rn: vreg(18),
3848
            rm: vreg(18),
3849
            size: VectorSize::Size16x8,
3850
        },
3851
        "5246726E",
3852
        "ushl v18.8h, v18.8h, v18.8h",
3853
    ));
3854

3855
    insns.push((
3856
        Inst::VecRRR {
3857
            alu_op: VecALUOp::Ushl,
3858
            rd: writable_vreg(18),
3859
            rn: vreg(1),
3860
            rm: vreg(21),
3861
            size: VectorSize::Size32x4,
3862
        },
3863
        "3244B56E",
3864
        "ushl v18.4s, v1.4s, v21.4s",
3865
    ));
3866

3867
    insns.push((
3868
        Inst::VecRRR {
3869
            alu_op: VecALUOp::Ushl,
3870
            rd: writable_vreg(5),
3871
            rn: vreg(7),
3872
            rm: vreg(19),
3873
            size: VectorSize::Size64x2,
3874
        },
3875
        "E544F36E",
3876
        "ushl v5.2d, v7.2d, v19.2d",
3877
    ));
3878

3879
    insns.push((
3880
        Inst::VecRRR {
3881
            alu_op: VecALUOp::Sshl,
3882
            rd: writable_vreg(18),
3883
            rn: vreg(18),
3884
            rm: vreg(18),
3885
            size: VectorSize::Size8x16,
3886
        },
3887
        "5246324E",
3888
        "sshl v18.16b, v18.16b, v18.16b",
3889
    ));
3890

3891
    insns.push((
3892
        Inst::VecRRR {
3893
            alu_op: VecALUOp::Sshl,
3894
            rd: writable_vreg(30),
3895
            rn: vreg(1),
3896
            rm: vreg(29),
3897
            size: VectorSize::Size16x8,
3898
        },
3899
        "3E447D4E",
3900
        "sshl v30.8h, v1.8h, v29.8h",
3901
    ));
3902

3903
    insns.push((
3904
        Inst::VecRRR {
3905
            alu_op: VecALUOp::Sshl,
3906
            rd: writable_vreg(8),
3907
            rn: vreg(22),
3908
            rm: vreg(21),
3909
            size: VectorSize::Size32x4,
3910
        },
3911
        "C846B54E",
3912
        "sshl v8.4s, v22.4s, v21.4s",
3913
    ));
3914

3915
    insns.push((
3916
        Inst::VecRRR {
3917
            alu_op: VecALUOp::Sshl,
3918
            rd: writable_vreg(8),
3919
            rn: vreg(22),
3920
            rm: vreg(2),
3921
            size: VectorSize::Size64x2,
3922
        },
3923
        "C846E24E",
3924
        "sshl v8.2d, v22.2d, v2.2d",
3925
    ));
3926

3927
    insns.push((
3928
        Inst::VecRRR {
3929
            alu_op: VecALUOp::Umin,
3930
            rd: writable_vreg(0),
3931
            rn: vreg(11),
3932
            rm: vreg(2),
3933
            size: VectorSize::Size8x8,
3934
        },
3935
        "606D222E",
3936
        "umin v0.8b, v11.8b, v2.8b",
3937
    ));
3938

3939
    insns.push((
3940
        Inst::VecRRR {
3941
            alu_op: VecALUOp::Umin,
3942
            rd: writable_vreg(1),
3943
            rn: vreg(12),
3944
            rm: vreg(3),
3945
            size: VectorSize::Size8x16,
3946
        },
3947
        "816D236E",
3948
        "umin v1.16b, v12.16b, v3.16b",
3949
    ));
3950

3951
    insns.push((
3952
        Inst::VecRRR {
3953
            alu_op: VecALUOp::Umin,
3954
            rd: writable_vreg(29),
3955
            rn: vreg(19),
3956
            rm: vreg(9),
3957
            size: VectorSize::Size16x4,
3958
        },
3959
        "7D6E692E",
3960
        "umin v29.4h, v19.4h, v9.4h",
3961
    ));
3962

3963
    insns.push((
3964
        Inst::VecRRR {
3965
            alu_op: VecALUOp::Umin,
3966
            rd: writable_vreg(30),
3967
            rn: vreg(20),
3968
            rm: vreg(10),
3969
            size: VectorSize::Size16x8,
3970
        },
3971
        "9E6E6A6E",
3972
        "umin v30.8h, v20.8h, v10.8h",
3973
    ));
3974

3975
    insns.push((
3976
        Inst::VecRRR {
3977
            alu_op: VecALUOp::Umin,
3978
            rd: writable_vreg(7),
3979
            rn: vreg(21),
3980
            rm: vreg(20),
3981
            size: VectorSize::Size32x2,
3982
        },
3983
        "A76EB42E",
3984
        "umin v7.2s, v21.2s, v20.2s",
3985
    ));
3986

3987
    insns.push((
3988
        Inst::VecRRR {
3989
            alu_op: VecALUOp::Umin,
3990
            rd: writable_vreg(8),
3991
            rn: vreg(22),
3992
            rm: vreg(21),
3993
            size: VectorSize::Size32x4,
3994
        },
3995
        "C86EB56E",
3996
        "umin v8.4s, v22.4s, v21.4s",
3997
    ));
3998

3999
    insns.push((
4000
        Inst::VecRRR {
4001
            alu_op: VecALUOp::Smin,
4002
            rd: writable_vreg(2),
4003
            rn: vreg(13),
4004
            rm: vreg(4),
4005
            size: VectorSize::Size8x8,
4006
        },
4007
        "A26D240E",
4008
        "smin v2.8b, v13.8b, v4.8b",
4009
    ));
4010

4011
    insns.push((
4012
        Inst::VecRRR {
4013
            alu_op: VecALUOp::Smin,
4014
            rd: writable_vreg(1),
4015
            rn: vreg(12),
4016
            rm: vreg(3),
4017
            size: VectorSize::Size8x16,
4018
        },
4019
        "816D234E",
4020
        "smin v1.16b, v12.16b, v3.16b",
4021
    ));
4022

4023
    insns.push((
4024
        Inst::VecRRR {
4025
            alu_op: VecALUOp::Smin,
4026
            rd: writable_vreg(3),
4027
            rn: vreg(2),
4028
            rm: vreg(1),
4029
            size: VectorSize::Size16x4,
4030
        },
4031
        "436C610E",
4032
        "smin v3.4h, v2.4h, v1.4h",
4033
    ));
4034

4035
    insns.push((
4036
        Inst::VecRRR {
4037
            alu_op: VecALUOp::Smin,
4038
            rd: writable_vreg(30),
4039
            rn: vreg(20),
4040
            rm: vreg(10),
4041
            size: VectorSize::Size16x8,
4042
        },
4043
        "9E6E6A4E",
4044
        "smin v30.8h, v20.8h, v10.8h",
4045
    ));
4046

4047
    insns.push((
4048
        Inst::VecRRR {
4049
            alu_op: VecALUOp::Smin,
4050
            rd: writable_vreg(9),
4051
            rn: vreg(22),
4052
            rm: vreg(20),
4053
            size: VectorSize::Size32x2,
4054
        },
4055
        "C96EB40E",
4056
        "smin v9.2s, v22.2s, v20.2s",
4057
    ));
4058

4059
    insns.push((
4060
        Inst::VecRRR {
4061
            alu_op: VecALUOp::Smin,
4062
            rd: writable_vreg(8),
4063
            rn: vreg(22),
4064
            rm: vreg(21),
4065
            size: VectorSize::Size32x4,
4066
        },
4067
        "C86EB54E",
4068
        "smin v8.4s, v22.4s, v21.4s",
4069
    ));
4070

4071
    insns.push((
4072
        Inst::VecRRR {
4073
            alu_op: VecALUOp::Umax,
4074
            rd: writable_vreg(6),
4075
            rn: vreg(9),
4076
            rm: vreg(8),
4077
            size: VectorSize::Size8x8,
4078
        },
4079
        "2665282E",
4080
        "umax v6.8b, v9.8b, v8.8b",
4081
    ));
4082

4083
    insns.push((
4084
        Inst::VecRRR {
4085
            alu_op: VecALUOp::Umax,
4086
            rd: writable_vreg(5),
4087
            rn: vreg(15),
4088
            rm: vreg(8),
4089
            size: VectorSize::Size8x16,
4090
        },
4091
        "E565286E",
4092
        "umax v5.16b, v15.16b, v8.16b",
4093
    ));
4094

4095
    insns.push((
4096
        Inst::VecRRR {
4097
            alu_op: VecALUOp::Umax,
4098
            rd: writable_vreg(12),
4099
            rn: vreg(14),
4100
            rm: vreg(3),
4101
            size: VectorSize::Size16x4,
4102
        },
4103
        "CC65632E",
4104
        "umax v12.4h, v14.4h, v3.4h",
4105
    ));
4106

4107
    insns.push((
4108
        Inst::VecRRR {
4109
            alu_op: VecALUOp::Umax,
4110
            rd: writable_vreg(11),
4111
            rn: vreg(13),
4112
            rm: vreg(2),
4113
            size: VectorSize::Size16x8,
4114
        },
4115
        "AB65626E",
4116
        "umax v11.8h, v13.8h, v2.8h",
4117
    ));
4118

4119
    insns.push((
4120
        Inst::VecRRR {
4121
            alu_op: VecALUOp::Umax,
4122
            rd: writable_vreg(9),
4123
            rn: vreg(13),
4124
            rm: vreg(15),
4125
            size: VectorSize::Size32x2,
4126
        },
4127
        "A965AF2E",
4128
        "umax v9.2s, v13.2s, v15.2s",
4129
    ));
4130

4131
    insns.push((
4132
        Inst::VecRRR {
4133
            alu_op: VecALUOp::Umax,
4134
            rd: writable_vreg(8),
4135
            rn: vreg(12),
4136
            rm: vreg(14),
4137
            size: VectorSize::Size32x4,
4138
        },
4139
        "8865AE6E",
4140
        "umax v8.4s, v12.4s, v14.4s",
4141
    ));
4142

4143
    insns.push((
4144
        Inst::VecRRR {
4145
            alu_op: VecALUOp::Smax,
4146
            rd: writable_vreg(7),
4147
            rn: vreg(8),
4148
            rm: vreg(9),
4149
            size: VectorSize::Size8x8,
4150
        },
4151
        "0765290E",
4152
        "smax v7.8b, v8.8b, v9.8b",
4153
    ));
4154

4155
    insns.push((
4156
        Inst::VecRRR {
4157
            alu_op: VecALUOp::Smax,
4158
            rd: writable_vreg(6),
4159
            rn: vreg(9),
4160
            rm: vreg(8),
4161
            size: VectorSize::Size8x16,
4162
        },
4163
        "2665284E",
4164
        "smax v6.16b, v9.16b, v8.16b",
4165
    ));
4166

4167
    insns.push((
4168
        Inst::VecRRR {
4169
            alu_op: VecALUOp::Smax,
4170
            rd: writable_vreg(11),
4171
            rn: vreg(12),
4172
            rm: vreg(13),
4173
            size: VectorSize::Size16x4,
4174
        },
4175
        "8B656D0E",
4176
        "smax v11.4h, v12.4h, v13.4h",
4177
    ));
4178

4179
    insns.push((
4180
        Inst::VecRRR {
4181
            alu_op: VecALUOp::Smax,
4182
            rd: writable_vreg(11),
4183
            rn: vreg(13),
4184
            rm: vreg(2),
4185
            size: VectorSize::Size16x8,
4186
        },
4187
        "AB65624E",
4188
        "smax v11.8h, v13.8h, v2.8h",
4189
    ));
4190

4191
    insns.push((
4192
        Inst::VecRRR {
4193
            alu_op: VecALUOp::Smax,
4194
            rd: writable_vreg(14),
4195
            rn: vreg(16),
4196
            rm: vreg(18),
4197
            size: VectorSize::Size32x2,
4198
        },
4199
        "0E66B20E",
4200
        "smax v14.2s, v16.2s, v18.2s",
4201
    ));
4202

4203
    insns.push((
4204
        Inst::VecRRR {
4205
            alu_op: VecALUOp::Smax,
4206
            rd: writable_vreg(8),
4207
            rn: vreg(12),
4208
            rm: vreg(14),
4209
            size: VectorSize::Size32x4,
4210
        },
4211
        "8865AE4E",
4212
        "smax v8.4s, v12.4s, v14.4s",
4213
    ));
4214

4215
    insns.push((
4216
        Inst::VecRRR {
4217
            alu_op: VecALUOp::Urhadd,
4218
            rd: writable_vreg(8),
4219
            rn: vreg(1),
4220
            rm: vreg(3),
4221
            size: VectorSize::Size8x8,
4222
        },
4223
        "2814232E",
4224
        "urhadd v8.8b, v1.8b, v3.8b",
4225
    ));
4226

4227
    insns.push((
4228
        Inst::VecRRR {
4229
            alu_op: VecALUOp::Urhadd,
4230
            rd: writable_vreg(8),
4231
            rn: vreg(1),
4232
            rm: vreg(3),
4233
            size: VectorSize::Size8x16,
4234
        },
4235
        "2814236E",
4236
        "urhadd v8.16b, v1.16b, v3.16b",
4237
    ));
4238

4239
    insns.push((
4240
        Inst::VecRRR {
4241
            alu_op: VecALUOp::Urhadd,
4242
            rd: writable_vreg(2),
4243
            rn: vreg(13),
4244
            rm: vreg(6),
4245
            size: VectorSize::Size16x4,
4246
        },
4247
        "A215662E",
4248
        "urhadd v2.4h, v13.4h, v6.4h",
4249
    ));
4250

4251
    insns.push((
4252
        Inst::VecRRR {
4253
            alu_op: VecALUOp::Urhadd,
4254
            rd: writable_vreg(2),
4255
            rn: vreg(13),
4256
            rm: vreg(6),
4257
            size: VectorSize::Size16x8,
4258
        },
4259
        "A215666E",
4260
        "urhadd v2.8h, v13.8h, v6.8h",
4261
    ));
4262

4263
    insns.push((
4264
        Inst::VecRRR {
4265
            alu_op: VecALUOp::Urhadd,
4266
            rd: writable_vreg(8),
4267
            rn: vreg(12),
4268
            rm: vreg(14),
4269
            size: VectorSize::Size32x2,
4270
        },
4271
        "8815AE2E",
4272
        "urhadd v8.2s, v12.2s, v14.2s",
4273
    ));
4274

4275
    insns.push((
4276
        Inst::VecRRR {
4277
            alu_op: VecALUOp::Urhadd,
4278
            rd: writable_vreg(8),
4279
            rn: vreg(12),
4280
            rm: vreg(14),
4281
            size: VectorSize::Size32x4,
4282
        },
4283
        "8815AE6E",
4284
        "urhadd v8.4s, v12.4s, v14.4s",
4285
    ));
4286

4287
    insns.push((
4288
        Inst::VecRRR {
4289
            alu_op: VecALUOp::Fadd,
4290
            rd: writable_vreg(31),
4291
            rn: vreg(0),
4292
            rm: vreg(16),
4293
            size: VectorSize::Size32x4,
4294
        },
4295
        "1FD4304E",
4296
        "fadd v31.4s, v0.4s, v16.4s",
4297
    ));
4298

4299
    insns.push((
4300
        Inst::VecRRR {
4301
            alu_op: VecALUOp::Fsub,
4302
            rd: writable_vreg(8),
4303
            rn: vreg(7),
4304
            rm: vreg(15),
4305
            size: VectorSize::Size64x2,
4306
        },
4307
        "E8D4EF4E",
4308
        "fsub v8.2d, v7.2d, v15.2d",
4309
    ));
4310

4311
    insns.push((
4312
        Inst::VecRRR {
4313
            alu_op: VecALUOp::Fdiv,
4314
            rd: writable_vreg(1),
4315
            rn: vreg(3),
4316
            rm: vreg(4),
4317
            size: VectorSize::Size32x4,
4318
        },
4319
        "61FC246E",
4320
        "fdiv v1.4s, v3.4s, v4.4s",
4321
    ));
4322

4323
    insns.push((
4324
        Inst::VecRRR {
4325
            alu_op: VecALUOp::Fmax,
4326
            rd: writable_vreg(31),
4327
            rn: vreg(16),
4328
            rm: vreg(0),
4329
            size: VectorSize::Size64x2,
4330
        },
4331
        "1FF6604E",
4332
        "fmax v31.2d, v16.2d, v0.2d",
4333
    ));
4334

4335
    insns.push((
4336
        Inst::VecRRR {
4337
            alu_op: VecALUOp::Fmin,
4338
            rd: writable_vreg(5),
4339
            rn: vreg(19),
4340
            rm: vreg(26),
4341
            size: VectorSize::Size32x4,
4342
        },
4343
        "65F6BA4E",
4344
        "fmin v5.4s, v19.4s, v26.4s",
4345
    ));
4346

4347
    insns.push((
4348
        Inst::VecRRR {
4349
            alu_op: VecALUOp::Fmul,
4350
            rd: writable_vreg(2),
4351
            rn: vreg(0),
4352
            rm: vreg(5),
4353
            size: VectorSize::Size64x2,
4354
        },
4355
        "02DC656E",
4356
        "fmul v2.2d, v0.2d, v5.2d",
4357
    ));
4358

4359
    insns.push((
4360
        Inst::VecRRRMod {
4361
            alu_op: VecALUModOp::Fmla,
4362
            rd: writable_vreg(2),
4363
            ri: vreg(2),
4364
            rn: vreg(0),
4365
            rm: vreg(5),
4366
            size: VectorSize::Size32x2,
4367
        },
4368
        "02CC250E",
4369
        "fmla v2.2s, v2.2s, v0.2s, v5.2s",
4370
    ));
4371

4372
    insns.push((
4373
        Inst::VecRRRMod {
4374
            alu_op: VecALUModOp::Fmla,
4375
            rd: writable_vreg(2),
4376
            ri: vreg(2),
4377
            rn: vreg(0),
4378
            rm: vreg(5),
4379
            size: VectorSize::Size32x4,
4380
        },
4381
        "02CC254E",
4382
        "fmla v2.4s, v2.4s, v0.4s, v5.4s",
4383
    ));
4384

4385
    insns.push((
4386
        Inst::VecRRRMod {
4387
            alu_op: VecALUModOp::Fmla,
4388
            rd: writable_vreg(2),
4389
            ri: vreg(2),
4390
            rn: vreg(0),
4391
            rm: vreg(5),
4392
            size: VectorSize::Size64x2,
4393
        },
4394
        "02CC654E",
4395
        "fmla v2.2d, v2.2d, v0.2d, v5.2d",
4396
    ));
4397

4398
    insns.push((
4399
        Inst::VecRRR {
4400
            alu_op: VecALUOp::Addp,
4401
            rd: writable_vreg(16),
4402
            rn: vreg(12),
4403
            rm: vreg(1),
4404
            size: VectorSize::Size8x8,
4405
        },
4406
        "90BD210E",
4407
        "addp v16.8b, v12.8b, v1.8b",
4408
    ));
4409

4410
    insns.push((
4411
        Inst::VecRRR {
4412
            alu_op: VecALUOp::Addp,
4413
            rd: writable_vreg(16),
4414
            rn: vreg(12),
4415
            rm: vreg(1),
4416
            size: VectorSize::Size8x16,
4417
        },
4418
        "90BD214E",
4419
        "addp v16.16b, v12.16b, v1.16b",
4420
    ));
4421

4422
    insns.push((
4423
        Inst::VecRRR {
4424
            alu_op: VecALUOp::Addp,
4425
            rd: writable_vreg(8),
4426
            rn: vreg(12),
4427
            rm: vreg(14),
4428
            size: VectorSize::Size32x4,
4429
        },
4430
        "88BDAE4E",
4431
        "addp v8.4s, v12.4s, v14.4s",
4432
    ));
4433

4434
    insns.push((
4435
        Inst::VecRRR {
4436
            alu_op: VecALUOp::Addp,
4437
            rd: writable_vreg(8),
4438
            rn: vreg(12),
4439
            rm: vreg(14),
4440
            size: VectorSize::Size32x2,
4441
        },
4442
        "88BDAE0E",
4443
        "addp v8.2s, v12.2s, v14.2s",
4444
    ));
4445

4446
    insns.push((
4447
        Inst::VecRRR {
4448
            alu_op: VecALUOp::Zip1,
4449
            rd: writable_vreg(16),
4450
            rn: vreg(12),
4451
            rm: vreg(1),
4452
            size: VectorSize::Size8x16,
4453
        },
4454
        "9039014E",
4455
        "zip1 v16.16b, v12.16b, v1.16b",
4456
    ));
4457

4458
    insns.push((
4459
        Inst::VecRRR {
4460
            alu_op: VecALUOp::Zip1,
4461
            rd: writable_vreg(2),
4462
            rn: vreg(13),
4463
            rm: vreg(6),
4464
            size: VectorSize::Size16x8,
4465
        },
4466
        "A239464E",
4467
        "zip1 v2.8h, v13.8h, v6.8h",
4468
    ));
4469

4470
    insns.push((
4471
        Inst::VecRRR {
4472
            alu_op: VecALUOp::Zip1,
4473
            rd: writable_vreg(8),
4474
            rn: vreg(12),
4475
            rm: vreg(14),
4476
            size: VectorSize::Size32x4,
4477
        },
4478
        "88398E4E",
4479
        "zip1 v8.4s, v12.4s, v14.4s",
4480
    ));
4481

4482
    insns.push((
4483
        Inst::VecRRR {
4484
            alu_op: VecALUOp::Zip1,
4485
            rd: writable_vreg(9),
4486
            rn: vreg(20),
4487
            rm: vreg(17),
4488
            size: VectorSize::Size64x2,
4489
        },
4490
        "893AD14E",
4491
        "zip1 v9.2d, v20.2d, v17.2d",
4492
    ));
4493

4494
    insns.push((
4495
        Inst::VecRRRLong {
4496
            alu_op: VecRRRLongOp::Smull8,
4497
            rd: writable_vreg(16),
4498
            rn: vreg(12),
4499
            rm: vreg(1),
4500
            high_half: false,
4501
        },
4502
        "90C1210E",
4503
        "smull v16.8h, v12.8b, v1.8b",
4504
    ));
4505

4506
    insns.push((
4507
        Inst::VecRRRLong {
4508
            alu_op: VecRRRLongOp::Umull8,
4509
            rd: writable_vreg(15),
4510
            rn: vreg(11),
4511
            rm: vreg(2),
4512
            high_half: false,
4513
        },
4514
        "6FC1222E",
4515
        "umull v15.8h, v11.8b, v2.8b",
4516
    ));
4517

4518
    insns.push((
4519
        Inst::VecRRRLongMod {
4520
            alu_op: VecRRRLongModOp::Umlal8,
4521
            rd: writable_vreg(4),
4522
            ri: vreg(4),
4523
            rn: vreg(8),
4524
            rm: vreg(16),
4525
            high_half: false,
4526
        },
4527
        "0481302E",
4528
        "umlal v4.8h, v4.8h, v8.8b, v16.8b",
4529
    ));
4530

4531
    insns.push((
4532
        Inst::VecRRRLong {
4533
            alu_op: VecRRRLongOp::Smull16,
4534
            rd: writable_vreg(2),
4535
            rn: vreg(13),
4536
            rm: vreg(6),
4537
            high_half: false,
4538
        },
4539
        "A2C1660E",
4540
        "smull v2.4s, v13.4h, v6.4h",
4541
    ));
4542

4543
    insns.push((
4544
        Inst::VecRRRLong {
4545
            alu_op: VecRRRLongOp::Umull16,
4546
            rd: writable_vreg(3),
4547
            rn: vreg(14),
4548
            rm: vreg(7),
4549
            high_half: false,
4550
        },
4551
        "C3C1672E",
4552
        "umull v3.4s, v14.4h, v7.4h",
4553
    ));
4554

4555
    insns.push((
4556
        Inst::VecRRRLongMod {
4557
            alu_op: VecRRRLongModOp::Umlal16,
4558
            rd: writable_vreg(7),
4559
            ri: vreg(7),
4560
            rn: vreg(14),
4561
            rm: vreg(21),
4562
            high_half: false,
4563
        },
4564
        "C781752E",
4565
        "umlal v7.4s, v7.4s, v14.4h, v21.4h",
4566
    ));
4567

4568
    insns.push((
4569
        Inst::VecRRRLong {
4570
            alu_op: VecRRRLongOp::Smull32,
4571
            rd: writable_vreg(8),
4572
            rn: vreg(12),
4573
            rm: vreg(14),
4574
            high_half: false,
4575
        },
4576
        "88C1AE0E",
4577
        "smull v8.2d, v12.2s, v14.2s",
4578
    ));
4579

4580
    insns.push((
4581
        Inst::VecRRRLong {
4582
            alu_op: VecRRRLongOp::Umull32,
4583
            rd: writable_vreg(9),
4584
            rn: vreg(5),
4585
            rm: vreg(6),
4586
            high_half: false,
4587
        },
4588
        "A9C0A62E",
4589
        "umull v9.2d, v5.2s, v6.2s",
4590
    ));
4591

4592
    insns.push((
4593
        Inst::VecRRRLongMod {
4594
            alu_op: VecRRRLongModOp::Umlal32,
4595
            rd: writable_vreg(9),
4596
            ri: vreg(9),
4597
            rn: vreg(20),
4598
            rm: vreg(17),
4599
            high_half: false,
4600
        },
4601
        "8982B12E",
4602
        "umlal v9.2d, v9.2d, v20.2s, v17.2s",
4603
    ));
4604

4605
    insns.push((
4606
        Inst::VecRRRLong {
4607
            alu_op: VecRRRLongOp::Smull8,
4608
            rd: writable_vreg(16),
4609
            rn: vreg(12),
4610
            rm: vreg(1),
4611
            high_half: true,
4612
        },
4613
        "90C1214E",
4614
        "smull2 v16.8h, v12.16b, v1.16b",
4615
    ));
4616

4617
    insns.push((
4618
        Inst::VecRRRLong {
4619
            alu_op: VecRRRLongOp::Umull8,
4620
            rd: writable_vreg(29),
4621
            rn: vreg(22),
4622
            rm: vreg(10),
4623
            high_half: true,
4624
        },
4625
        "DDC22A6E",
4626
        "umull2 v29.8h, v22.16b, v10.16b",
4627
    ));
4628

4629
    insns.push((
4630
        Inst::VecRRRLongMod {
4631
            alu_op: VecRRRLongModOp::Umlal8,
4632
            rd: writable_vreg(1),
4633
            ri: vreg(1),
4634
            rn: vreg(5),
4635
            rm: vreg(15),
4636
            high_half: true,
4637
        },
4638
        "A1802F6E",
4639
        "umlal2 v1.8h, v1.8h, v5.16b, v15.16b",
4640
    ));
4641

4642
    insns.push((
4643
        Inst::VecRRRLong {
4644
            alu_op: VecRRRLongOp::Smull16,
4645
            rd: writable_vreg(2),
4646
            rn: vreg(13),
4647
            rm: vreg(6),
4648
            high_half: true,
4649
        },
4650
        "A2C1664E",
4651
        "smull2 v2.4s, v13.8h, v6.8h",
4652
    ));
4653

4654
    insns.push((
4655
        Inst::VecRRRLong {
4656
            alu_op: VecRRRLongOp::Umull16,
4657
            rd: writable_vreg(19),
4658
            rn: vreg(18),
4659
            rm: vreg(17),
4660
            high_half: true,
4661
        },
4662
        "53C2716E",
4663
        "umull2 v19.4s, v18.8h, v17.8h",
4664
    ));
4665

4666
    insns.push((
4667
        Inst::VecRRRLongMod {
4668
            alu_op: VecRRRLongModOp::Umlal16,
4669
            rd: writable_vreg(11),
4670
            ri: vreg(11),
4671
            rn: vreg(10),
4672
            rm: vreg(12),
4673
            high_half: true,
4674
        },
4675
        "4B816C6E",
4676
        "umlal2 v11.4s, v11.4s, v10.8h, v12.8h",
4677
    ));
4678

4679
    insns.push((
4680
        Inst::VecRRRLong {
4681
            alu_op: VecRRRLongOp::Smull32,
4682
            rd: writable_vreg(8),
4683
            rn: vreg(12),
4684
            rm: vreg(14),
4685
            high_half: true,
4686
        },
4687
        "88C1AE4E",
4688
        "smull2 v8.2d, v12.4s, v14.4s",
4689
    ));
4690

4691
    insns.push((
4692
        Inst::VecRRRLong {
4693
            alu_op: VecRRRLongOp::Umull32,
4694
            rd: writable_vreg(4),
4695
            rn: vreg(12),
4696
            rm: vreg(16),
4697
            high_half: true,
4698
        },
4699
        "84C1B06E",
4700
        "umull2 v4.2d, v12.4s, v16.4s",
4701
    ));
4702

4703
    insns.push((
4704
        Inst::VecRRRLongMod {
4705
            alu_op: VecRRRLongModOp::Umlal32,
4706
            rd: writable_vreg(10),
4707
            ri: vreg(10),
4708
            rn: vreg(29),
4709
            rm: vreg(2),
4710
            high_half: true,
4711
        },
4712
        "AA83A26E",
4713
        "umlal2 v10.2d, v10.2d, v29.4s, v2.4s",
4714
    ));
4715

4716
    insns.push((
4717
        Inst::VecRRR {
4718
            alu_op: VecALUOp::Sqrdmulh,
4719
            rd: writable_vreg(31),
4720
            rn: vreg(0),
4721
            rm: vreg(31),
4722
            size: VectorSize::Size16x8,
4723
        },
4724
        "1FB47F6E",
4725
        "sqrdmulh v31.8h, v0.8h, v31.8h",
4726
    ));
4727

4728
    insns.push((
4729
        Inst::VecRRR {
4730
            alu_op: VecALUOp::Sqrdmulh,
4731
            rd: writable_vreg(7),
4732
            rn: vreg(7),
4733
            rm: vreg(23),
4734
            size: VectorSize::Size32x2,
4735
        },
4736
        "E7B4B72E",
4737
        "sqrdmulh v7.2s, v7.2s, v23.2s",
4738
    ));
4739

4740
    insns.push((
4741
        Inst::VecMisc {
4742
            op: VecMisc2::Not,
4743
            rd: writable_vreg(20),
4744
            rn: vreg(17),
4745
            size: VectorSize::Size8x8,
4746
        },
4747
        "345A202E",
4748
        "mvn v20.8b, v17.8b",
4749
    ));
4750

4751
    insns.push((
4752
        Inst::VecMisc {
4753
            op: VecMisc2::Not,
4754
            rd: writable_vreg(2),
4755
            rn: vreg(1),
4756
            size: VectorSize::Size32x4,
4757
        },
4758
        "2258206E",
4759
        "mvn v2.16b, v1.16b",
4760
    ));
4761

4762
    insns.push((
4763
        Inst::VecMisc {
4764
            op: VecMisc2::Neg,
4765
            rd: writable_vreg(3),
4766
            rn: vreg(7),
4767
            size: VectorSize::Size8x8,
4768
        },
4769
        "E3B8202E",
4770
        "neg v3.8b, v7.8b",
4771
    ));
4772

4773
    insns.push((
4774
        Inst::VecMisc {
4775
            op: VecMisc2::Neg,
4776
            rd: writable_vreg(8),
4777
            rn: vreg(12),
4778
            size: VectorSize::Size8x16,
4779
        },
4780
        "88B9206E",
4781
        "neg v8.16b, v12.16b",
4782
    ));
4783

4784
    insns.push((
4785
        Inst::VecMisc {
4786
            op: VecMisc2::Neg,
4787
            rd: writable_vreg(0),
4788
            rn: vreg(31),
4789
            size: VectorSize::Size16x8,
4790
        },
4791
        "E0BB606E",
4792
        "neg v0.8h, v31.8h",
4793
    ));
4794

4795
    insns.push((
4796
        Inst::VecMisc {
4797
            op: VecMisc2::Neg,
4798
            rd: writable_vreg(2),
4799
            rn: vreg(3),
4800
            size: VectorSize::Size32x4,
4801
        },
4802
        "62B8A06E",
4803
        "neg v2.4s, v3.4s",
4804
    ));
4805

4806
    insns.push((
4807
        Inst::VecMisc {
4808
            op: VecMisc2::Neg,
4809
            rd: writable_vreg(10),
4810
            rn: vreg(8),
4811
            size: VectorSize::Size64x2,
4812
        },
4813
        "0AB9E06E",
4814
        "neg v10.2d, v8.2d",
4815
    ));
4816

4817
    insns.push((
4818
        Inst::VecMisc {
4819
            op: VecMisc2::Abs,
4820
            rd: writable_vreg(3),
4821
            rn: vreg(1),
4822
            size: VectorSize::Size8x8,
4823
        },
4824
        "23B8200E",
4825
        "abs v3.8b, v1.8b",
4826
    ));
4827

4828
    insns.push((
4829
        Inst::VecMisc {
4830
            op: VecMisc2::Abs,
4831
            rd: writable_vreg(1),
4832
            rn: vreg(1),
4833
            size: VectorSize::Size8x16,
4834
        },
4835
        "21B8204E",
4836
        "abs v1.16b, v1.16b",
4837
    ));
4838

4839
    insns.push((
4840
        Inst::VecMisc {
4841
            op: VecMisc2::Abs,
4842
            rd: writable_vreg(29),
4843
            rn: vreg(28),
4844
            size: VectorSize::Size16x8,
4845
        },
4846
        "9DBB604E",
4847
        "abs v29.8h, v28.8h",
4848
    ));
4849

4850
    insns.push((
4851
        Inst::VecMisc {
4852
            op: VecMisc2::Abs,
4853
            rd: writable_vreg(7),
4854
            rn: vreg(8),
4855
            size: VectorSize::Size32x4,
4856
        },
4857
        "07B9A04E",
4858
        "abs v7.4s, v8.4s",
4859
    ));
4860

4861
    insns.push((
4862
        Inst::VecMisc {
4863
            op: VecMisc2::Abs,
4864
            rd: writable_vreg(1),
4865
            rn: vreg(10),
4866
            size: VectorSize::Size64x2,
4867
        },
4868
        "41B9E04E",
4869
        "abs v1.2d, v10.2d",
4870
    ));
4871

4872
    insns.push((
4873
        Inst::VecMisc {
4874
            op: VecMisc2::Fabs,
4875
            rd: writable_vreg(15),
4876
            rn: vreg(16),
4877
            size: VectorSize::Size32x2,
4878
        },
4879
        "0FFAA00E",
4880
        "fabs v15.2s, v16.2s",
4881
    ));
4882

4883
    insns.push((
4884
        Inst::VecMisc {
4885
            op: VecMisc2::Fabs,
4886
            rd: writable_vreg(15),
4887
            rn: vreg(16),
4888
            size: VectorSize::Size32x4,
4889
        },
4890
        "0FFAA04E",
4891
        "fabs v15.4s, v16.4s",
4892
    ));
4893

4894
    insns.push((
4895
        Inst::VecMisc {
4896
            op: VecMisc2::Fabs,
4897
            rd: writable_vreg(3),
4898
            rn: vreg(22),
4899
            size: VectorSize::Size64x2,
4900
        },
4901
        "C3FAE04E",
4902
        "fabs v3.2d, v22.2d",
4903
    ));
4904

4905
    insns.push((
4906
        Inst::VecMisc {
4907
            op: VecMisc2::Fneg,
4908
            rd: writable_vreg(31),
4909
            rn: vreg(0),
4910
            size: VectorSize::Size32x2,
4911
        },
4912
        "1FF8A02E",
4913
        "fneg v31.2s, v0.2s",
4914
    ));
4915

4916
    insns.push((
4917
        Inst::VecMisc {
4918
            op: VecMisc2::Fneg,
4919
            rd: writable_vreg(31),
4920
            rn: vreg(0),
4921
            size: VectorSize::Size32x4,
4922
        },
4923
        "1FF8A06E",
4924
        "fneg v31.4s, v0.4s",
4925
    ));
4926

4927
    insns.push((
4928
        Inst::VecMisc {
4929
            op: VecMisc2::Fneg,
4930
            rd: writable_vreg(11),
4931
            rn: vreg(6),
4932
            size: VectorSize::Size64x2,
4933
        },
4934
        "CBF8E06E",
4935
        "fneg v11.2d, v6.2d",
4936
    ));
4937

4938
    insns.push((
4939
        Inst::VecMisc {
4940
            op: VecMisc2::Fsqrt,
4941
            rd: writable_vreg(18),
4942
            rn: vreg(25),
4943
            size: VectorSize::Size32x2,
4944
        },
4945
        "32FBA12E",
4946
        "fsqrt v18.2s, v25.2s",
4947
    ));
4948

4949
    insns.push((
4950
        Inst::VecMisc {
4951
            op: VecMisc2::Fsqrt,
4952
            rd: writable_vreg(18),
4953
            rn: vreg(25),
4954
            size: VectorSize::Size32x4,
4955
        },
4956
        "32FBA16E",
4957
        "fsqrt v18.4s, v25.4s",
4958
    ));
4959

4960
    insns.push((
4961
        Inst::VecMisc {
4962
            op: VecMisc2::Fsqrt,
4963
            rd: writable_vreg(7),
4964
            rn: vreg(18),
4965
            size: VectorSize::Size64x2,
4966
        },
4967
        "47FAE16E",
4968
        "fsqrt v7.2d, v18.2d",
4969
    ));
4970

4971
    insns.push((
4972
        Inst::VecMisc {
4973
            op: VecMisc2::Rev64,
4974
            rd: writable_vreg(1),
4975
            rn: vreg(10),
4976
            size: VectorSize::Size32x4,
4977
        },
4978
        "4109A04E",
4979
        "rev64 v1.4s, v10.4s",
4980
    ));
4981

4982
    insns.push((
4983
        Inst::VecMisc {
4984
            op: VecMisc2::Fcvtzs,
4985
            rd: writable_vreg(4),
4986
            rn: vreg(22),
4987
            size: VectorSize::Size32x4,
4988
        },
4989
        "C4BAA14E",
4990
        "fcvtzs v4.4s, v22.4s",
4991
    ));
4992

4993
    insns.push((
4994
        Inst::VecMisc {
4995
            op: VecMisc2::Fcvtzs,
4996
            rd: writable_vreg(0),
4997
            rn: vreg(31),
4998
            size: VectorSize::Size64x2,
4999
        },
5000
        "E0BBE14E",
5001
        "fcvtzs v0.2d, v31.2d",
5002
    ));
5003

5004
    insns.push((
5005
        Inst::VecMisc {
5006
            op: VecMisc2::Fcvtzu,
5007
            rd: writable_vreg(4),
5008
            rn: vreg(26),
5009
            size: VectorSize::Size32x2,
5010
        },
5011
        "44BBA12E",
5012
        "fcvtzu v4.2s, v26.2s",
5013
    ));
5014

5015
    insns.push((
5016
        Inst::VecMisc {
5017
            op: VecMisc2::Fcvtzu,
5018
            rd: writable_vreg(29),
5019
            rn: vreg(15),
5020
            size: VectorSize::Size64x2,
5021
        },
5022
        "FDB9E16E",
5023
        "fcvtzu v29.2d, v15.2d",
5024
    ));
5025

5026
    insns.push((
5027
        Inst::VecMisc {
5028
            op: VecMisc2::Scvtf,
5029
            rd: writable_vreg(20),
5030
            rn: vreg(8),
5031
            size: VectorSize::Size32x4,
5032
        },
5033
        "14D9214E",
5034
        "scvtf v20.4s, v8.4s",
5035
    ));
5036

5037
    insns.push((
5038
        Inst::VecMisc {
5039
            op: VecMisc2::Ucvtf,
5040
            rd: writable_vreg(10),
5041
            rn: vreg(19),
5042
            size: VectorSize::Size64x2,
5043
        },
5044
        "6ADA616E",
5045
        "ucvtf v10.2d, v19.2d",
5046
    ));
5047

5048
    insns.push((
5049
        Inst::VecMisc {
5050
            op: VecMisc2::Frintn,
5051
            rd: writable_vreg(20),
5052
            rn: vreg(7),
5053
            size: VectorSize::Size32x2,
5054
        },
5055
        "F488210E",
5056
        "frintn v20.2s, v7.2s",
5057
    ));
5058

5059
    insns.push((
5060
        Inst::VecMisc {
5061
            op: VecMisc2::Frintn,
5062
            rd: writable_vreg(11),
5063
            rn: vreg(18),
5064
            size: VectorSize::Size32x4,
5065
        },
5066
        "4B8A214E",
5067
        "frintn v11.4s, v18.4s",
5068
    ));
5069

5070
    insns.push((
5071
        Inst::VecMisc {
5072
            op: VecMisc2::Frintn,
5073
            rd: writable_vreg(12),
5074
            rn: vreg(17),
5075
            size: VectorSize::Size64x2,
5076
        },
5077
        "2C8A614E",
5078
        "frintn v12.2d, v17.2d",
5079
    ));
5080

5081
    insns.push((
5082
        Inst::VecMisc {
5083
            op: VecMisc2::Frintz,
5084
            rd: writable_vreg(1),
5085
            rn: vreg(30),
5086
            size: VectorSize::Size32x2,
5087
        },
5088
        "C19BA10E",
5089
        "frintz v1.2s, v30.2s",
5090
    ));
5091

5092
    insns.push((
5093
        Inst::VecMisc {
5094
            op: VecMisc2::Frintz,
5095
            rd: writable_vreg(11),
5096
            rn: vreg(18),
5097
            size: VectorSize::Size32x4,
5098
        },
5099
        "4B9AA14E",
5100
        "frintz v11.4s, v18.4s",
5101
    ));
5102

5103
    insns.push((
5104
        Inst::VecMisc {
5105
            op: VecMisc2::Frintz,
5106
            rd: writable_vreg(12),
5107
            rn: vreg(17),
5108
            size: VectorSize::Size64x2,
5109
        },
5110
        "2C9AE14E",
5111
        "frintz v12.2d, v17.2d",
5112
    ));
5113

5114
    insns.push((
5115
        Inst::VecMisc {
5116
            op: VecMisc2::Frintm,
5117
            rd: writable_vreg(15),
5118
            rn: vreg(7),
5119
            size: VectorSize::Size32x2,
5120
        },
5121
        "EF98210E",
5122
        "frintm v15.2s, v7.2s",
5123
    ));
5124

5125
    insns.push((
5126
        Inst::VecMisc {
5127
            op: VecMisc2::Frintm,
5128
            rd: writable_vreg(11),
5129
            rn: vreg(18),
5130
            size: VectorSize::Size32x4,
5131
        },
5132
        "4B9A214E",
5133
        "frintm v11.4s, v18.4s",
5134
    ));
5135

5136
    insns.push((
5137
        Inst::VecMisc {
5138
            op: VecMisc2::Frintm,
5139
            rd: writable_vreg(12),
5140
            rn: vreg(17),
5141
            size: VectorSize::Size64x2,
5142
        },
5143
        "2C9A614E",
5144
        "frintm v12.2d, v17.2d",
5145
    ));
5146

5147
    insns.push((
5148
        Inst::VecMisc {
5149
            op: VecMisc2::Frintp,
5150
            rd: writable_vreg(3),
5151
            rn: vreg(4),
5152
            size: VectorSize::Size32x2,
5153
        },
5154
        "8388A10E",
5155
        "frintp v3.2s, v4.2s",
5156
    ));
5157

5158
    insns.push((
5159
        Inst::VecMisc {
5160
            op: VecMisc2::Frintp,
5161
            rd: writable_vreg(11),
5162
            rn: vreg(18),
5163
            size: VectorSize::Size32x4,
5164
        },
5165
        "4B8AA14E",
5166
        "frintp v11.4s, v18.4s",
5167
    ));
5168

5169
    insns.push((
5170
        Inst::VecMisc {
5171
            op: VecMisc2::Frintp,
5172
            rd: writable_vreg(12),
5173
            rn: vreg(17),
5174
            size: VectorSize::Size64x2,
5175
        },
5176
        "2C8AE14E",
5177
        "frintp v12.2d, v17.2d",
5178
    ));
5179

5180
    insns.push((
5181
        Inst::VecMisc {
5182
            op: VecMisc2::Cnt,
5183
            rd: writable_vreg(23),
5184
            rn: vreg(5),
5185
            size: VectorSize::Size8x8,
5186
        },
5187
        "B758200E",
5188
        "cnt v23.8b, v5.8b",
5189
    ));
5190

5191
    insns.push((
5192
        Inst::VecMisc {
5193
            op: VecMisc2::Fcmeq0,
5194
            rd: writable_vreg(5),
5195
            rn: vreg(2),
5196
            size: VectorSize::Size32x4,
5197
        },
5198
        "45D8A04E",
5199
        "fcmeq v5.4s, v2.4s, #0.0",
5200
    ));
5201

5202
    insns.push((
5203
        Inst::VecMisc {
5204
            op: VecMisc2::Fcmge0,
5205
            rd: writable_vreg(3),
5206
            rn: vreg(1),
5207
            size: VectorSize::Size64x2,
5208
        },
5209
        "23C8E06E",
5210
        "fcmge v3.2d, v1.2d, #0.0",
5211
    ));
5212

5213
    insns.push((
5214
        Inst::VecMisc {
5215
            op: VecMisc2::Fcmgt0,
5216
            rd: writable_vreg(5),
5217
            rn: vreg(7),
5218
            size: VectorSize::Size32x4,
5219
        },
5220
        "E5C8A04E",
5221
        "fcmgt v5.4s, v7.4s, #0.0",
5222
    ));
5223

5224
    insns.push((
5225
        Inst::VecMisc {
5226
            op: VecMisc2::Fcmle0,
5227
            rd: writable_vreg(10),
5228
            rn: vreg(2),
5229
            size: VectorSize::Size32x4,
5230
        },
5231
        "4AD8A06E",
5232
        "fcmle v10.4s, v2.4s, #0.0",
5233
    ));
5234

5235
    insns.push((
5236
        Inst::VecMisc {
5237
            op: VecMisc2::Fcmlt0,
5238
            rd: writable_vreg(12),
5239
            rn: vreg(12),
5240
            size: VectorSize::Size64x2,
5241
        },
5242
        "8CE9E04E",
5243
        "fcmlt v12.2d, v12.2d, #0.0",
5244
    ));
5245

5246
    insns.push((
5247
        Inst::VecMisc {
5248
            op: VecMisc2::Cmeq0,
5249
            rd: writable_vreg(22),
5250
            rn: vreg(27),
5251
            size: VectorSize::Size16x8,
5252
        },
5253
        "769B604E",
5254
        "cmeq v22.8h, v27.8h, #0",
5255
    ));
5256

5257
    insns.push((
5258
        Inst::VecMisc {
5259
            op: VecMisc2::Cmge0,
5260
            rd: writable_vreg(12),
5261
            rn: vreg(27),
5262
            size: VectorSize::Size16x8,
5263
        },
5264
        "6C8B606E",
5265
        "cmge v12.8h, v27.8h, #0",
5266
    ));
5267

5268
    insns.push((
5269
        Inst::VecMisc {
5270
            op: VecMisc2::Cmgt0,
5271
            rd: writable_vreg(12),
5272
            rn: vreg(27),
5273
            size: VectorSize::Size8x16,
5274
        },
5275
        "6C8B204E",
5276
        "cmgt v12.16b, v27.16b, #0",
5277
    ));
5278

5279
    insns.push((
5280
        Inst::VecMisc {
5281
            op: VecMisc2::Cmle0,
5282
            rd: writable_vreg(1),
5283
            rn: vreg(27),
5284
            size: VectorSize::Size32x4,
5285
        },
5286
        "619BA06E",
5287
        "cmle v1.4s, v27.4s, #0",
5288
    ));
5289

5290
    insns.push((
5291
        Inst::VecMisc {
5292
            op: VecMisc2::Cmlt0,
5293
            rd: writable_vreg(0),
5294
            rn: vreg(7),
5295
            size: VectorSize::Size64x2,
5296
        },
5297
        "E0A8E04E",
5298
        "cmlt v0.2d, v7.2d, #0",
5299
    ));
5300

5301
    insns.push((
5302
        Inst::VecLanes {
5303
            op: VecLanesOp::Uminv,
5304
            rd: writable_vreg(0),
5305
            rn: vreg(31),
5306
            size: VectorSize::Size8x8,
5307
        },
5308
        "E0AB312E",
5309
        "uminv b0, v31.8b",
5310
    ));
5311

5312
    insns.push((
5313
        Inst::VecLanes {
5314
            op: VecLanesOp::Uminv,
5315
            rd: writable_vreg(2),
5316
            rn: vreg(1),
5317
            size: VectorSize::Size8x16,
5318
        },
5319
        "22A8316E",
5320
        "uminv b2, v1.16b",
5321
    ));
5322

5323
    insns.push((
5324
        Inst::VecLanes {
5325
            op: VecLanesOp::Uminv,
5326
            rd: writable_vreg(3),
5327
            rn: vreg(11),
5328
            size: VectorSize::Size16x8,
5329
        },
5330
        "63A9716E",
5331
        "uminv h3, v11.8h",
5332
    ));
5333

5334
    insns.push((
5335
        Inst::VecLanes {
5336
            op: VecLanesOp::Uminv,
5337
            rd: writable_vreg(18),
5338
            rn: vreg(4),
5339
            size: VectorSize::Size32x4,
5340
        },
5341
        "92A8B16E",
5342
        "uminv s18, v4.4s",
5343
    ));
5344

5345
    insns.push((
5346
        Inst::VecLanes {
5347
            op: VecLanesOp::Addv,
5348
            rd: writable_vreg(2),
5349
            rn: vreg(29),
5350
            size: VectorSize::Size8x16,
5351
        },
5352
        "A2BB314E",
5353
        "addv b2, v29.16b",
5354
    ));
5355

5356
    insns.push((
5357
        Inst::VecLanes {
5358
            op: VecLanesOp::Addv,
5359
            rd: writable_vreg(15),
5360
            rn: vreg(7),
5361
            size: VectorSize::Size16x4,
5362
        },
5363
        "EFB8710E",
5364
        "addv h15, v7.4h",
5365
    ));
5366

5367
    insns.push((
5368
        Inst::VecLanes {
5369
            op: VecLanesOp::Addv,
5370
            rd: writable_vreg(3),
5371
            rn: vreg(21),
5372
            size: VectorSize::Size16x8,
5373
        },
5374
        "A3BA714E",
5375
        "addv h3, v21.8h",
5376
    ));
5377

5378
    insns.push((
5379
        Inst::VecLanes {
5380
            op: VecLanesOp::Addv,
5381
            rd: writable_vreg(18),
5382
            rn: vreg(5),
5383
            size: VectorSize::Size32x4,
5384
        },
5385
        "B2B8B14E",
5386
        "addv s18, v5.4s",
5387
    ));
5388

5389
    insns.push((
5390
        Inst::VecShiftImm {
5391
            op: VecShiftImmOp::Shl,
5392
            rd: writable_vreg(27),
5393
            rn: vreg(5),
5394
            imm: 7,
5395
            size: VectorSize::Size8x16,
5396
        },
5397
        "BB540F4F",
5398
        "shl v27.16b, v5.16b, #7",
5399
    ));
5400

5401
    insns.push((
5402
        Inst::VecShiftImm {
5403
            op: VecShiftImmOp::Shl,
5404
            rd: writable_vreg(1),
5405
            rn: vreg(30),
5406
            imm: 0,
5407
            size: VectorSize::Size8x16,
5408
        },
5409
        "C157084F",
5410
        "shl v1.16b, v30.16b, #0",
5411
    ));
5412

5413
    insns.push((
5414
        Inst::VecShiftImm {
5415
            op: VecShiftImmOp::Sshr,
5416
            rd: writable_vreg(26),
5417
            rn: vreg(6),
5418
            imm: 16,
5419
            size: VectorSize::Size16x8,
5420
        },
5421
        "DA04104F",
5422
        "sshr v26.8h, v6.8h, #16",
5423
    ));
5424

5425
    insns.push((
5426
        Inst::VecShiftImm {
5427
            op: VecShiftImmOp::Sshr,
5428
            rd: writable_vreg(3),
5429
            rn: vreg(19),
5430
            imm: 1,
5431
            size: VectorSize::Size16x8,
5432
        },
5433
        "63061F4F",
5434
        "sshr v3.8h, v19.8h, #1",
5435
    ));
5436

5437
    insns.push((
5438
        Inst::VecShiftImm {
5439
            op: VecShiftImmOp::Ushr,
5440
            rd: writable_vreg(25),
5441
            rn: vreg(6),
5442
            imm: 8,
5443
            size: VectorSize::Size8x8,
5444
        },
5445
        "D904082F",
5446
        "ushr v25.8b, v6.8b, #8",
5447
    ));
5448

5449
    insns.push((
5450
        Inst::VecShiftImm {
5451
            op: VecShiftImmOp::Ushr,
5452
            rd: writable_vreg(5),
5453
            rn: vreg(21),
5454
            imm: 1,
5455
            size: VectorSize::Size8x8,
5456
        },
5457
        "A5060F2F",
5458
        "ushr v5.8b, v21.8b, #1",
5459
    ));
5460

5461
    insns.push((
5462
        Inst::VecShiftImm {
5463
            op: VecShiftImmOp::Ushr,
5464
            rd: writable_vreg(25),
5465
            rn: vreg(6),
5466
            imm: 8,
5467
            size: VectorSize::Size8x16,
5468
        },
5469
        "D904086F",
5470
        "ushr v25.16b, v6.16b, #8",
5471
    ));
5472

5473
    insns.push((
5474
        Inst::VecShiftImm {
5475
            op: VecShiftImmOp::Ushr,
5476
            rd: writable_vreg(5),
5477
            rn: vreg(21),
5478
            imm: 1,
5479
            size: VectorSize::Size8x16,
5480
        },
5481
        "A5060F6F",
5482
        "ushr v5.16b, v21.16b, #1",
5483
    ));
5484

5485
    insns.push((
5486
        Inst::VecShiftImm {
5487
            op: VecShiftImmOp::Ushr,
5488
            rd: writable_vreg(25),
5489
            rn: vreg(6),
5490
            imm: 16,
5491
            size: VectorSize::Size16x4,
5492
        },
5493
        "D904102F",
5494
        "ushr v25.4h, v6.4h, #16",
5495
    ));
5496

5497
    insns.push((
5498
        Inst::VecShiftImm {
5499
            op: VecShiftImmOp::Ushr,
5500
            rd: writable_vreg(5),
5501
            rn: vreg(21),
5502
            imm: 1,
5503
            size: VectorSize::Size16x4,
5504
        },
5505
        "A5061F2F",
5506
        "ushr v5.4h, v21.4h, #1",
5507
    ));
5508

5509
    insns.push((
5510
        Inst::VecShiftImm {
5511
            op: VecShiftImmOp::Ushr,
5512
            rd: writable_vreg(25),
5513
            rn: vreg(6),
5514
            imm: 16,
5515
            size: VectorSize::Size16x8,
5516
        },
5517
        "D904106F",
5518
        "ushr v25.8h, v6.8h, #16",
5519
    ));
5520

5521
    insns.push((
5522
        Inst::VecShiftImm {
5523
            op: VecShiftImmOp::Ushr,
5524
            rd: writable_vreg(5),
5525
            rn: vreg(21),
5526
            imm: 1,
5527
            size: VectorSize::Size16x8,
5528
        },
5529
        "A5061F6F",
5530
        "ushr v5.8h, v21.8h, #1",
5531
    ));
5532

5533
    insns.push((
5534
        Inst::VecShiftImm {
5535
            op: VecShiftImmOp::Ushr,
5536
            rd: writable_vreg(25),
5537
            rn: vreg(6),
5538
            imm: 32,
5539
            size: VectorSize::Size32x2,
5540
        },
5541
        "D904202F",
5542
        "ushr v25.2s, v6.2s, #32",
5543
    ));
5544

5545
    insns.push((
5546
        Inst::VecShiftImm {
5547
            op: VecShiftImmOp::Ushr,
5548
            rd: writable_vreg(5),
5549
            rn: vreg(21),
5550
            imm: 1,
5551
            size: VectorSize::Size32x2,
5552
        },
5553
        "A5063F2F",
5554
        "ushr v5.2s, v21.2s, #1",
5555
    ));
5556

5557
    insns.push((
5558
        Inst::VecShiftImm {
5559
            op: VecShiftImmOp::Ushr,
5560
            rd: writable_vreg(25),
5561
            rn: vreg(6),
5562
            imm: 32,
5563
            size: VectorSize::Size32x4,
5564
        },
5565
        "D904206F",
5566
        "ushr v25.4s, v6.4s, #32",
5567
    ));
5568

5569
    insns.push((
5570
        Inst::VecShiftImm {
5571
            op: VecShiftImmOp::Ushr,
5572
            rd: writable_vreg(5),
5573
            rn: vreg(21),
5574
            imm: 1,
5575
            size: VectorSize::Size32x4,
5576
        },
5577
        "A5063F6F",
5578
        "ushr v5.4s, v21.4s, #1",
5579
    ));
5580

5581
    insns.push((
5582
        Inst::VecShiftImm {
5583
            op: VecShiftImmOp::Ushr,
5584
            rd: writable_vreg(25),
5585
            rn: vreg(6),
5586
            imm: 64,
5587
            size: VectorSize::Size64x2,
5588
        },
5589
        "D904406F",
5590
        "ushr v25.2d, v6.2d, #64",
5591
    ));
5592

5593
    insns.push((
5594
        Inst::VecShiftImm {
5595
            op: VecShiftImmOp::Ushr,
5596
            rd: writable_vreg(5),
5597
            rn: vreg(21),
5598
            imm: 1,
5599
            size: VectorSize::Size64x2,
5600
        },
5601
        "A5067F6F",
5602
        "ushr v5.2d, v21.2d, #1",
5603
    ));
5604

5605
    insns.push((
5606
        Inst::VecShiftImm {
5607
            op: VecShiftImmOp::Shl,
5608
            rd: writable_vreg(22),
5609
            rn: vreg(13),
5610
            imm: 63,
5611
            size: VectorSize::Size64x2,
5612
        },
5613
        "B6557F4F",
5614
        "shl v22.2d, v13.2d, #63",
5615
    ));
5616

5617
    insns.push((
5618
        Inst::VecShiftImm {
5619
            op: VecShiftImmOp::Shl,
5620
            rd: writable_vreg(23),
5621
            rn: vreg(9),
5622
            imm: 0,
5623
            size: VectorSize::Size64x2,
5624
        },
5625
        "3755404F",
5626
        "shl v23.2d, v9.2d, #0",
5627
    ));
5628

5629
    insns.push((
5630
        Inst::VecExtract {
5631
            rd: writable_vreg(1),
5632
            rn: vreg(30),
5633
            rm: vreg(17),
5634
            imm4: 0,
5635
        },
5636
        "C103116E",
5637
        "ext v1.16b, v30.16b, v17.16b, #0",
5638
    ));
5639

5640
    insns.push((
5641
        Inst::VecExtract {
5642
            rd: writable_vreg(1),
5643
            rn: vreg(30),
5644
            rm: vreg(17),
5645
            imm4: 8,
5646
        },
5647
        "C143116E",
5648
        "ext v1.16b, v30.16b, v17.16b, #8",
5649
    ));
5650

5651
    insns.push((
5652
        Inst::VecExtract {
5653
            rd: writable_vreg(1),
5654
            rn: vreg(30),
5655
            rm: vreg(17),
5656
            imm4: 15,
5657
        },
5658
        "C17B116E",
5659
        "ext v1.16b, v30.16b, v17.16b, #15",
5660
    ));
5661

5662
    insns.push((
5663
        Inst::VecTbl {
5664
            rd: writable_vreg(0),
5665
            rn: vreg(31),
5666
            rm: vreg(16),
5667
        },
5668
        "E003104E",
5669
        "tbl v0.16b, { v31.16b }, v16.16b",
5670
    ));
5671

5672
    insns.push((
5673
        Inst::VecTblExt {
5674
            rd: writable_vreg(4),
5675
            ri: vreg(4),
5676
            rn: vreg(12),
5677
            rm: vreg(23),
5678
        },
5679
        "8411174E",
5680
        "tbx v4.16b, v4.16b, { v12.16b }, v23.16b",
5681
    ));
5682

5683
    insns.push((
5684
        Inst::VecTbl2 {
5685
            rd: writable_vreg(16),
5686
            rn: vreg(31),
5687
            rn2: vreg(0),
5688
            rm: vreg(26),
5689
        },
5690
        "F0231A4E",
5691
        "tbl v16.16b, { v31.16b, v0.16b }, v26.16b",
5692
    ));
5693

5694
    insns.push((
5695
        Inst::VecTbl2Ext {
5696
            rd: writable_vreg(3),
5697
            ri: vreg(3),
5698
            rn: vreg(11),
5699
            rn2: vreg(12),
5700
            rm: vreg(19),
5701
        },
5702
        "6331134E",
5703
        "tbx v3.16b, v3.16b, { v11.16b, v12.16b }, v19.16b",
5704
    ));
5705

5706
    insns.push((
5707
        Inst::VecLoadReplicate {
5708
            rd: writable_vreg(31),
5709
            rn: xreg(0),
5710
            size: VectorSize::Size64x2,
5711
            flags: MemFlags::trusted(),
5712
        },
5713
        "1FCC404D",
5714
        "ld1r { v31.2d }, [x0]",
5715
    ));
5716

5717
    insns.push((
5718
        Inst::VecLoadReplicate {
5719
            rd: writable_vreg(0),
5720
            rn: xreg(25),
5721
            size: VectorSize::Size8x8,
5722
            flags: MemFlags::trusted(),
5723
        },
5724
        "20C3400D",
5725
        "ld1r { v0.8b }, [x25]",
5726
    ));
5727

5728
    insns.push((
5729
        Inst::VecCSel {
5730
            rd: writable_vreg(5),
5731
            rn: vreg(10),
5732
            rm: vreg(19),
5733
            cond: Cond::Gt,
5734
        },
5735
        "6C000054651EB34E02000014451DAA4E",
5736
        "vcsel v5.16b, v10.16b, v19.16b, gt (if-then-else diamond)",
5737
    ));
5738

5739
    insns.push((
5740
        Inst::Extend {
5741
            rd: writable_xreg(3),
5742
            rn: xreg(5),
5743
            signed: false,
5744
            from_bits: 1,
5745
            to_bits: 32,
5746
        },
5747
        "A3000012",
5748
        "and w3, w5, #1",
5749
    ));
5750
    insns.push((
5751
        Inst::Extend {
5752
            rd: writable_xreg(3),
5753
            rn: xreg(5),
5754
            signed: false,
5755
            from_bits: 1,
5756
            to_bits: 64,
5757
        },
5758
        "A3000012",
5759
        "and w3, w5, #1",
5760
    ));
5761
    insns.push((
5762
        Inst::Extend {
5763
            rd: writable_xreg(10),
5764
            rn: xreg(21),
5765
            signed: true,
5766
            from_bits: 1,
5767
            to_bits: 32,
5768
        },
5769
        "AA020013",
5770
        "sbfx w10, w21, #0, #1",
5771
    ));
5772
    insns.push((
5773
        Inst::Extend {
5774
            rd: writable_xreg(1),
5775
            rn: xreg(2),
5776
            signed: true,
5777
            from_bits: 1,
5778
            to_bits: 64,
5779
        },
5780
        "41004093",
5781
        "sbfx x1, x2, #0, #1",
5782
    ));
5783
    insns.push((
5784
        Inst::Extend {
5785
            rd: writable_xreg(1),
5786
            rn: xreg(2),
5787
            signed: false,
5788
            from_bits: 8,
5789
            to_bits: 32,
5790
        },
5791
        "411C0053",
5792
        "uxtb w1, w2",
5793
    ));
5794
    insns.push((
5795
        Inst::Extend {
5796
            rd: writable_xreg(1),
5797
            rn: xreg(2),
5798
            signed: true,
5799
            from_bits: 8,
5800
            to_bits: 32,
5801
        },
5802
        "411C0013",
5803
        "sxtb w1, w2",
5804
    ));
5805
    insns.push((
5806
        Inst::Extend {
5807
            rd: writable_xreg(1),
5808
            rn: xreg(2),
5809
            signed: false,
5810
            from_bits: 16,
5811
            to_bits: 32,
5812
        },
5813
        "413C0053",
5814
        "uxth w1, w2",
5815
    ));
5816
    insns.push((
5817
        Inst::Extend {
5818
            rd: writable_xreg(1),
5819
            rn: xreg(2),
5820
            signed: true,
5821
            from_bits: 16,
5822
            to_bits: 32,
5823
        },
5824
        "413C0013",
5825
        "sxth w1, w2",
5826
    ));
5827
    insns.push((
5828
        Inst::Extend {
5829
            rd: writable_xreg(1),
5830
            rn: xreg(2),
5831
            signed: false,
5832
            from_bits: 8,
5833
            to_bits: 64,
5834
        },
5835
        "411C0053",
5836
        "uxtb w1, w2",
5837
    ));
5838
    insns.push((
5839
        Inst::Extend {
5840
            rd: writable_xreg(1),
5841
            rn: xreg(2),
5842
            signed: true,
5843
            from_bits: 8,
5844
            to_bits: 64,
5845
        },
5846
        "411C4093",
5847
        "sxtb x1, w2",
5848
    ));
5849
    insns.push((
5850
        Inst::Extend {
5851
            rd: writable_xreg(1),
5852
            rn: xreg(2),
5853
            signed: false,
5854
            from_bits: 16,
5855
            to_bits: 64,
5856
        },
5857
        "413C0053",
5858
        "uxth w1, w2",
5859
    ));
5860
    insns.push((
5861
        Inst::Extend {
5862
            rd: writable_xreg(1),
5863
            rn: xreg(2),
5864
            signed: true,
5865
            from_bits: 16,
5866
            to_bits: 64,
5867
        },
5868
        "413C4093",
5869
        "sxth x1, w2",
5870
    ));
5871
    insns.push((
5872
        Inst::Extend {
5873
            rd: writable_xreg(1),
5874
            rn: xreg(2),
5875
            signed: false,
5876
            from_bits: 32,
5877
            to_bits: 64,
5878
        },
5879
        "E103022A",
5880
        "mov w1, w2",
5881
    ));
5882
    insns.push((
5883
        Inst::Extend {
5884
            rd: writable_xreg(1),
5885
            rn: xreg(2),
5886
            signed: true,
5887
            from_bits: 32,
5888
            to_bits: 64,
5889
        },
5890
        "417C4093",
5891
        "sxtw x1, w2",
5892
    ));
5893

5894
    insns.push((
5895
        Inst::Jump {
5896
            dest: BranchTarget::ResolvedOffset(64),
5897
        },
5898
        "10000014",
5899
        "b 64",
5900
    ));
5901

5902
    insns.push((
5903
        Inst::TrapIf {
5904
            trap_code: TrapCode::STACK_OVERFLOW,
5905
            kind: CondBrKind::NotZero(xreg(8), OperandSize::Size64),
5906
        },
5907
        "280000B51FC10000",
5908
        "cbnz x8, #trap=stk_ovf",
5909
    ));
5910
    insns.push((
5911
        Inst::TrapIf {
5912
            trap_code: TrapCode::STACK_OVERFLOW,
5913
            kind: CondBrKind::Zero(xreg(8), OperandSize::Size64),
5914
        },
5915
        "280000B41FC10000",
5916
        "cbz x8, #trap=stk_ovf",
5917
    ));
5918
    insns.push((
5919
        Inst::TrapIf {
5920
            trap_code: TrapCode::STACK_OVERFLOW,
5921
            kind: CondBrKind::Cond(Cond::Ne),
5922
        },
5923
        "210000541FC10000",
5924
        "b.ne #trap=stk_ovf",
5925
    ));
5926
    insns.push((
5927
        Inst::TrapIf {
5928
            trap_code: TrapCode::STACK_OVERFLOW,
5929
            kind: CondBrKind::Cond(Cond::Eq),
5930
        },
5931
        "200000541FC10000",
5932
        "b.eq #trap=stk_ovf",
5933
    ));
5934
    insns.push((
5935
        Inst::TrapIf {
5936
            trap_code: TrapCode::STACK_OVERFLOW,
5937
            kind: CondBrKind::Cond(Cond::Lo),
5938
        },
5939
        "230000541FC10000",
5940
        "b.lo #trap=stk_ovf",
5941
    ));
5942
    insns.push((
5943
        Inst::TrapIf {
5944
            trap_code: TrapCode::STACK_OVERFLOW,
5945
            kind: CondBrKind::Cond(Cond::Hs),
5946
        },
5947
        "220000541FC10000",
5948
        "b.hs #trap=stk_ovf",
5949
    ));
5950
    insns.push((
5951
        Inst::TrapIf {
5952
            trap_code: TrapCode::STACK_OVERFLOW,
5953
            kind: CondBrKind::Cond(Cond::Pl),
5954
        },
5955
        "250000541FC10000",
5956
        "b.pl #trap=stk_ovf",
5957
    ));
5958
    insns.push((
5959
        Inst::TrapIf {
5960
            trap_code: TrapCode::STACK_OVERFLOW,
5961
            kind: CondBrKind::Cond(Cond::Mi),
5962
        },
5963
        "240000541FC10000",
5964
        "b.mi #trap=stk_ovf",
5965
    ));
5966
    insns.push((
5967
        Inst::TrapIf {
5968
            trap_code: TrapCode::STACK_OVERFLOW,
5969
            kind: CondBrKind::Cond(Cond::Vc),
5970
        },
5971
        "270000541FC10000",
5972
        "b.vc #trap=stk_ovf",
5973
    ));
5974
    insns.push((
5975
        Inst::TrapIf {
5976
            trap_code: TrapCode::STACK_OVERFLOW,
5977
            kind: CondBrKind::Cond(Cond::Vs),
5978
        },
5979
        "260000541FC10000",
5980
        "b.vs #trap=stk_ovf",
5981
    ));
5982
    insns.push((
5983
        Inst::TrapIf {
5984
            trap_code: TrapCode::STACK_OVERFLOW,
5985
            kind: CondBrKind::Cond(Cond::Ls),
5986
        },
5987
        "290000541FC10000",
5988
        "b.ls #trap=stk_ovf",
5989
    ));
5990
    insns.push((
5991
        Inst::TrapIf {
5992
            trap_code: TrapCode::STACK_OVERFLOW,
5993
            kind: CondBrKind::Cond(Cond::Hi),
5994
        },
5995
        "280000541FC10000",
5996
        "b.hi #trap=stk_ovf",
5997
    ));
5998
    insns.push((
5999
        Inst::TrapIf {
6000
            trap_code: TrapCode::STACK_OVERFLOW,
6001
            kind: CondBrKind::Cond(Cond::Lt),
6002
        },
6003
        "2B0000541FC10000",
6004
        "b.lt #trap=stk_ovf",
6005
    ));
6006
    insns.push((
6007
        Inst::TrapIf {
6008
            trap_code: TrapCode::STACK_OVERFLOW,
6009
            kind: CondBrKind::Cond(Cond::Ge),
6010
        },
6011
        "2A0000541FC10000",
6012
        "b.ge #trap=stk_ovf",
6013
    ));
6014
    insns.push((
6015
        Inst::TrapIf {
6016
            trap_code: TrapCode::STACK_OVERFLOW,
6017
            kind: CondBrKind::Cond(Cond::Le),
6018
        },
6019
        "2D0000541FC10000",
6020
        "b.le #trap=stk_ovf",
6021
    ));
6022
    insns.push((
6023
        Inst::TrapIf {
6024
            trap_code: TrapCode::STACK_OVERFLOW,
6025
            kind: CondBrKind::Cond(Cond::Gt),
6026
        },
6027
        "2C0000541FC10000",
6028
        "b.gt #trap=stk_ovf",
6029
    ));
6030
    insns.push((
6031
        Inst::TrapIf {
6032
            trap_code: TrapCode::STACK_OVERFLOW,
6033
            kind: CondBrKind::Cond(Cond::Nv),
6034
        },
6035
        "2F0000541FC10000",
6036
        "b.nv #trap=stk_ovf",
6037
    ));
6038
    insns.push((
6039
        Inst::TrapIf {
6040
            trap_code: TrapCode::STACK_OVERFLOW,
6041
            kind: CondBrKind::Cond(Cond::Al),
6042
        },
6043
        "2E0000541FC10000",
6044
        "b.al #trap=stk_ovf",
6045
    ));
6046

6047
    insns.push((
6048
        Inst::CondBr {
6049
            taken: BranchTarget::ResolvedOffset(64),
6050
            not_taken: BranchTarget::ResolvedOffset(128),
6051
            kind: CondBrKind::Cond(Cond::Le),
6052
        },
6053
        "0D02005420000014",
6054
        "b.le 64 ; b 128",
6055
    ));
6056

6057
    insns.push((
6058
        Inst::Call {
6059
            info: Box::new(CallInfo::empty(
6060
                ExternalName::testcase("test0"),
6061
                CallConv::SystemV,
6062
            )),
6063
        },
6064
        "00000094",
6065
        "bl 0",
6066
    ));
6067

6068
    insns.push((
6069
        Inst::CallInd {
6070
            info: Box::new(CallInfo::empty(xreg(10), CallConv::SystemV)),
6071
        },
6072
        "40013FD6",
6073
        "blr x10",
6074
    ));
6075

6076
    insns.push((
6077
        Inst::IndirectBr {
6078
            rn: xreg(3),
6079
            targets: vec![],
6080
        },
6081
        "60001FD6",
6082
        "br x3",
6083
    ));
6084

6085
    insns.push((Inst::Brk, "00003ED4", "brk #0xf000"));
6086

6087
    insns.push((
6088
        Inst::Adr {
6089
            rd: writable_xreg(15),
6090
            off: (1 << 20) - 4,
6091
        },
6092
        "EFFF7F10",
6093
        "adr x15, pc+1048572",
6094
    ));
6095

6096
    insns.push((
6097
        Inst::Adrp {
6098
            rd: writable_xreg(8),
6099
            off: 0,
6100
        },
6101
        "08000090",
6102
        "adrp x8, pc+0",
6103
    ));
6104

6105
    insns.push((
6106
        Inst::Adrp {
6107
            rd: writable_xreg(3),
6108
            off: 16,
6109
        },
6110
        "83000090",
6111
        "adrp x3, pc+65536",
6112
    ));
6113

6114
    insns.push((
6115
        Inst::FpuMove64 {
6116
            rd: writable_vreg(8),
6117
            rn: vreg(4),
6118
        },
6119
        "8840601E",
6120
        "fmov d8, d4",
6121
    ));
6122

6123
    insns.push((
6124
        Inst::FpuMove32 {
6125
            rd: writable_vreg(8),
6126
            rn: vreg(4),
6127
        },
6128
        "8840201E",
6129
        "fmov s8, s4",
6130
    ));
6131

6132
    insns.push((
6133
        Inst::FpuMove128 {
6134
            rd: writable_vreg(17),
6135
            rn: vreg(26),
6136
        },
6137
        "511FBA4E",
6138
        "mov v17.16b, v26.16b",
6139
    ));
6140

6141
    insns.push((
6142
        Inst::FpuMoveFromVec {
6143
            rd: writable_vreg(1),
6144
            rn: vreg(30),
6145
            idx: 2,
6146
            size: VectorSize::Size32x4,
6147
        },
6148
        "C107145E",
6149
        "mov s1, v30.s[2]",
6150
    ));
6151

6152
    insns.push((
6153
        Inst::FpuMoveFromVec {
6154
            rd: writable_vreg(23),
6155
            rn: vreg(11),
6156
            idx: 0,
6157
            size: VectorSize::Size64x2,
6158
        },
6159
        "7705085E",
6160
        "mov d23, v11.d[0]",
6161
    ));
6162

6163
    insns.push((
6164
        Inst::FpuExtend {
6165
            rd: writable_vreg(31),
6166
            rn: vreg(0),
6167
            size: ScalarSize::Size32,
6168
        },
6169
        "1F40201E",
6170
        "fmov s31, s0",
6171
    ));
6172

6173
    insns.push((
6174
        Inst::FpuExtend {
6175
            rd: writable_vreg(31),
6176
            rn: vreg(0),
6177
            size: ScalarSize::Size64,
6178
        },
6179
        "1F40601E",
6180
        "fmov d31, d0",
6181
    ));
6182

6183
    insns.push((
6184
        Inst::FpuRR {
6185
            fpu_op: FPUOp1::Abs,
6186
            size: ScalarSize::Size32,
6187
            rd: writable_vreg(15),
6188
            rn: vreg(30),
6189
        },
6190
        "CFC3201E",
6191
        "fabs s15, s30",
6192
    ));
6193

6194
    insns.push((
6195
        Inst::FpuRR {
6196
            fpu_op: FPUOp1::Abs,
6197
            size: ScalarSize::Size64,
6198
            rd: writable_vreg(15),
6199
            rn: vreg(30),
6200
        },
6201
        "CFC3601E",
6202
        "fabs d15, d30",
6203
    ));
6204

6205
    insns.push((
6206
        Inst::FpuRR {
6207
            fpu_op: FPUOp1::Neg,
6208
            size: ScalarSize::Size32,
6209
            rd: writable_vreg(15),
6210
            rn: vreg(30),
6211
        },
6212
        "CF43211E",
6213
        "fneg s15, s30",
6214
    ));
6215

6216
    insns.push((
6217
        Inst::FpuRR {
6218
            fpu_op: FPUOp1::Neg,
6219
            size: ScalarSize::Size64,
6220
            rd: writable_vreg(15),
6221
            rn: vreg(30),
6222
        },
6223
        "CF43611E",
6224
        "fneg d15, d30",
6225
    ));
6226

6227
    insns.push((
6228
        Inst::FpuRR {
6229
            fpu_op: FPUOp1::Sqrt,
6230
            size: ScalarSize::Size32,
6231
            rd: writable_vreg(15),
6232
            rn: vreg(30),
6233
        },
6234
        "CFC3211E",
6235
        "fsqrt s15, s30",
6236
    ));
6237

6238
    insns.push((
6239
        Inst::FpuRR {
6240
            fpu_op: FPUOp1::Sqrt,
6241
            size: ScalarSize::Size64,
6242
            rd: writable_vreg(15),
6243
            rn: vreg(30),
6244
        },
6245
        "CFC3611E",
6246
        "fsqrt d15, d30",
6247
    ));
6248

6249
    insns.push((
6250
        Inst::FpuRR {
6251
            fpu_op: FPUOp1::Cvt32To64,
6252
            size: ScalarSize::Size32,
6253
            rd: writable_vreg(15),
6254
            rn: vreg(30),
6255
        },
6256
        "CFC3221E",
6257
        "fcvt d15, s30",
6258
    ));
6259

6260
    insns.push((
6261
        Inst::FpuRR {
6262
            fpu_op: FPUOp1::Cvt64To32,
6263
            size: ScalarSize::Size64,
6264
            rd: writable_vreg(15),
6265
            rn: vreg(30),
6266
        },
6267
        "CF43621E",
6268
        "fcvt s15, d30",
6269
    ));
6270

6271
    insns.push((
6272
        Inst::FpuRRR {
6273
            fpu_op: FPUOp2::Add,
6274
            size: ScalarSize::Size32,
6275
            rd: writable_vreg(15),
6276
            rn: vreg(30),
6277
            rm: vreg(31),
6278
        },
6279
        "CF2B3F1E",
6280
        "fadd s15, s30, s31",
6281
    ));
6282

6283
    insns.push((
6284
        Inst::FpuRRR {
6285
            fpu_op: FPUOp2::Add,
6286
            size: ScalarSize::Size64,
6287
            rd: writable_vreg(15),
6288
            rn: vreg(30),
6289
            rm: vreg(31),
6290
        },
6291
        "CF2B7F1E",
6292
        "fadd d15, d30, d31",
6293
    ));
6294

6295
    insns.push((
6296
        Inst::FpuRRR {
6297
            fpu_op: FPUOp2::Sub,
6298
            size: ScalarSize::Size32,
6299
            rd: writable_vreg(15),
6300
            rn: vreg(30),
6301
            rm: vreg(31),
6302
        },
6303
        "CF3B3F1E",
6304
        "fsub s15, s30, s31",
6305
    ));
6306

6307
    insns.push((
6308
        Inst::FpuRRR {
6309
            fpu_op: FPUOp2::Sub,
6310
            size: ScalarSize::Size64,
6311
            rd: writable_vreg(15),
6312
            rn: vreg(30),
6313
            rm: vreg(31),
6314
        },
6315
        "CF3B7F1E",
6316
        "fsub d15, d30, d31",
6317
    ));
6318

6319
    insns.push((
6320
        Inst::FpuRRR {
6321
            fpu_op: FPUOp2::Mul,
6322
            size: ScalarSize::Size32,
6323
            rd: writable_vreg(15),
6324
            rn: vreg(30),
6325
            rm: vreg(31),
6326
        },
6327
        "CF0B3F1E",
6328
        "fmul s15, s30, s31",
6329
    ));
6330

6331
    insns.push((
6332
        Inst::FpuRRR {
6333
            fpu_op: FPUOp2::Mul,
6334
            size: ScalarSize::Size64,
6335
            rd: writable_vreg(15),
6336
            rn: vreg(30),
6337
            rm: vreg(31),
6338
        },
6339
        "CF0B7F1E",
6340
        "fmul d15, d30, d31",
6341
    ));
6342

6343
    insns.push((
6344
        Inst::FpuRRR {
6345
            fpu_op: FPUOp2::Div,
6346
            size: ScalarSize::Size32,
6347
            rd: writable_vreg(15),
6348
            rn: vreg(30),
6349
            rm: vreg(31),
6350
        },
6351
        "CF1B3F1E",
6352
        "fdiv s15, s30, s31",
6353
    ));
6354

6355
    insns.push((
6356
        Inst::FpuRRR {
6357
            fpu_op: FPUOp2::Div,
6358
            size: ScalarSize::Size64,
6359
            rd: writable_vreg(15),
6360
            rn: vreg(30),
6361
            rm: vreg(31),
6362
        },
6363
        "CF1B7F1E",
6364
        "fdiv d15, d30, d31",
6365
    ));
6366

6367
    insns.push((
6368
        Inst::FpuRRR {
6369
            fpu_op: FPUOp2::Max,
6370
            size: ScalarSize::Size32,
6371
            rd: writable_vreg(15),
6372
            rn: vreg(30),
6373
            rm: vreg(31),
6374
        },
6375
        "CF4B3F1E",
6376
        "fmax s15, s30, s31",
6377
    ));
6378

6379
    insns.push((
6380
        Inst::FpuRRR {
6381
            fpu_op: FPUOp2::Max,
6382
            size: ScalarSize::Size64,
6383
            rd: writable_vreg(15),
6384
            rn: vreg(30),
6385
            rm: vreg(31),
6386
        },
6387
        "CF4B7F1E",
6388
        "fmax d15, d30, d31",
6389
    ));
6390

6391
    insns.push((
6392
        Inst::FpuRRR {
6393
            fpu_op: FPUOp2::Min,
6394
            size: ScalarSize::Size32,
6395
            rd: writable_vreg(15),
6396
            rn: vreg(30),
6397
            rm: vreg(31),
6398
        },
6399
        "CF5B3F1E",
6400
        "fmin s15, s30, s31",
6401
    ));
6402

6403
    insns.push((
6404
        Inst::FpuRRR {
6405
            fpu_op: FPUOp2::Min,
6406
            size: ScalarSize::Size64,
6407
            rd: writable_vreg(15),
6408
            rn: vreg(30),
6409
            rm: vreg(31),
6410
        },
6411
        "CF5B7F1E",
6412
        "fmin d15, d30, d31",
6413
    ));
6414

6415
    insns.push((
6416
        Inst::FpuRRRR {
6417
            fpu_op: FPUOp3::MAdd,
6418
            size: ScalarSize::Size32,
6419
            rd: writable_vreg(15),
6420
            rn: vreg(30),
6421
            rm: vreg(31),
6422
            ra: vreg(1),
6423
        },
6424
        "CF071F1F",
6425
        "fmadd s15, s30, s31, s1",
6426
    ));
6427

6428
    insns.push((
6429
        Inst::FpuRRRR {
6430
            fpu_op: FPUOp3::MSub,
6431
            size: ScalarSize::Size32,
6432
            rd: writable_vreg(15),
6433
            rn: vreg(30),
6434
            rm: vreg(31),
6435
            ra: vreg(1),
6436
        },
6437
        "CF871F1F",
6438
        "fmsub s15, s30, s31, s1",
6439
    ));
6440

6441
    insns.push((
6442
        Inst::FpuRRRR {
6443
            fpu_op: FPUOp3::MAdd,
6444
            size: ScalarSize::Size64,
6445
            rd: writable_vreg(15),
6446
            rn: vreg(30),
6447
            rm: vreg(31),
6448
            ra: vreg(1),
6449
        },
6450
        "CF075F1F",
6451
        "fmadd d15, d30, d31, d1",
6452
    ));
6453

6454
    insns.push((
6455
        Inst::FpuRRRR {
6456
            fpu_op: FPUOp3::MSub,
6457
            size: ScalarSize::Size64,
6458
            rd: writable_vreg(15),
6459
            rn: vreg(30),
6460
            rm: vreg(31),
6461
            ra: vreg(1),
6462
        },
6463
        "CF875F1F",
6464
        "fmsub d15, d30, d31, d1",
6465
    ));
6466

6467
    insns.push((
6468
        Inst::FpuRRRR {
6469
            fpu_op: FPUOp3::NMAdd,
6470
            size: ScalarSize::Size64,
6471
            rd: writable_vreg(15),
6472
            rn: vreg(30),
6473
            rm: vreg(31),
6474
            ra: vreg(1),
6475
        },
6476
        "CF077F1F",
6477
        "fnmadd d15, d30, d31, d1",
6478
    ));
6479

6480
    insns.push((
6481
        Inst::FpuRRRR {
6482
            fpu_op: FPUOp3::NMSub,
6483
            size: ScalarSize::Size64,
6484
            rd: writable_vreg(15),
6485
            rn: vreg(30),
6486
            rm: vreg(31),
6487
            ra: vreg(1),
6488
        },
6489
        "CF877F1F",
6490
        "fnmsub d15, d30, d31, d1",
6491
    ));
6492

6493
    insns.push((
6494
        Inst::FpuRRI {
6495
            fpu_op: FPUOpRI::UShr32(FPURightShiftImm::maybe_from_u8(32, 32).unwrap()),
6496
            rd: writable_vreg(2),
6497
            rn: vreg(5),
6498
        },
6499
        "A204202F",
6500
        "ushr v2.2s, v5.2s, #32",
6501
    ));
6502

6503
    insns.push((
6504
        Inst::FpuRRI {
6505
            fpu_op: FPUOpRI::UShr64(FPURightShiftImm::maybe_from_u8(63, 64).unwrap()),
6506
            rd: writable_vreg(2),
6507
            rn: vreg(5),
6508
        },
6509
        "A204417F",
6510
        "ushr d2, d5, #63",
6511
    ));
6512

6513
    insns.push((
6514
        Inst::FpuRRIMod {
6515
            fpu_op: FPUOpRIMod::Sli32(FPULeftShiftImm::maybe_from_u8(31, 32).unwrap()),
6516
            rd: writable_vreg(4),
6517
            ri: vreg(4),
6518
            rn: vreg(10),
6519
        },
6520
        "44553F2F",
6521
        "sli v4.2s, v4.2s, v10.2s, #31",
6522
    ));
6523

6524
    insns.push((
6525
        Inst::FpuRRIMod {
6526
            fpu_op: FPUOpRIMod::Sli64(FPULeftShiftImm::maybe_from_u8(63, 64).unwrap()),
6527
            rd: writable_vreg(4),
6528
            ri: vreg(4),
6529
            rn: vreg(10),
6530
        },
6531
        "44557F7F",
6532
        "sli d4, d4, d10, #63",
6533
    ));
6534

6535
    insns.push((
6536
        Inst::FpuToInt {
6537
            op: FpuToIntOp::F32ToU32,
6538
            rd: writable_xreg(1),
6539
            rn: vreg(4),
6540
        },
6541
        "8100391E",
6542
        "fcvtzu w1, s4",
6543
    ));
6544

6545
    insns.push((
6546
        Inst::FpuToInt {
6547
            op: FpuToIntOp::F32ToU64,
6548
            rd: writable_xreg(1),
6549
            rn: vreg(4),
6550
        },
6551
        "8100399E",
6552
        "fcvtzu x1, s4",
6553
    ));
6554

6555
    insns.push((
6556
        Inst::FpuToInt {
6557
            op: FpuToIntOp::F32ToI32,
6558
            rd: writable_xreg(1),
6559
            rn: vreg(4),
6560
        },
6561
        "8100381E",
6562
        "fcvtzs w1, s4",
6563
    ));
6564

6565
    insns.push((
6566
        Inst::FpuToInt {
6567
            op: FpuToIntOp::F32ToI64,
6568
            rd: writable_xreg(1),
6569
            rn: vreg(4),
6570
        },
6571
        "8100389E",
6572
        "fcvtzs x1, s4",
6573
    ));
6574

6575
    insns.push((
6576
        Inst::FpuToInt {
6577
            op: FpuToIntOp::F64ToU32,
6578
            rd: writable_xreg(1),
6579
            rn: vreg(4),
6580
        },
6581
        "8100791E",
6582
        "fcvtzu w1, d4",
6583
    ));
6584

6585
    insns.push((
6586
        Inst::FpuToInt {
6587
            op: FpuToIntOp::F64ToU64,
6588
            rd: writable_xreg(1),
6589
            rn: vreg(4),
6590
        },
6591
        "8100799E",
6592
        "fcvtzu x1, d4",
6593
    ));
6594

6595
    insns.push((
6596
        Inst::FpuToInt {
6597
            op: FpuToIntOp::F64ToI32,
6598
            rd: writable_xreg(1),
6599
            rn: vreg(4),
6600
        },
6601
        "8100781E",
6602
        "fcvtzs w1, d4",
6603
    ));
6604

6605
    insns.push((
6606
        Inst::FpuToInt {
6607
            op: FpuToIntOp::F64ToI64,
6608
            rd: writable_xreg(1),
6609
            rn: vreg(4),
6610
        },
6611
        "8100789E",
6612
        "fcvtzs x1, d4",
6613
    ));
6614

6615
    insns.push((
6616
        Inst::IntToFpu {
6617
            op: IntToFpuOp::U32ToF32,
6618
            rd: writable_vreg(1),
6619
            rn: xreg(4),
6620
        },
6621
        "8100231E",
6622
        "ucvtf s1, w4",
6623
    ));
6624

6625
    insns.push((
6626
        Inst::IntToFpu {
6627
            op: IntToFpuOp::I32ToF32,
6628
            rd: writable_vreg(1),
6629
            rn: xreg(4),
6630
        },
6631
        "8100221E",
6632
        "scvtf s1, w4",
6633
    ));
6634

6635
    insns.push((
6636
        Inst::IntToFpu {
6637
            op: IntToFpuOp::U32ToF64,
6638
            rd: writable_vreg(1),
6639
            rn: xreg(4),
6640
        },
6641
        "8100631E",
6642
        "ucvtf d1, w4",
6643
    ));
6644

6645
    insns.push((
6646
        Inst::IntToFpu {
6647
            op: IntToFpuOp::I32ToF64,
6648
            rd: writable_vreg(1),
6649
            rn: xreg(4),
6650
        },
6651
        "8100621E",
6652
        "scvtf d1, w4",
6653
    ));
6654

6655
    insns.push((
6656
        Inst::IntToFpu {
6657
            op: IntToFpuOp::U64ToF32,
6658
            rd: writable_vreg(1),
6659
            rn: xreg(4),
6660
        },
6661
        "8100239E",
6662
        "ucvtf s1, x4",
6663
    ));
6664

6665
    insns.push((
6666
        Inst::IntToFpu {
6667
            op: IntToFpuOp::I64ToF32,
6668
            rd: writable_vreg(1),
6669
            rn: xreg(4),
6670
        },
6671
        "8100229E",
6672
        "scvtf s1, x4",
6673
    ));
6674

6675
    insns.push((
6676
        Inst::IntToFpu {
6677
            op: IntToFpuOp::U64ToF64,
6678
            rd: writable_vreg(1),
6679
            rn: xreg(4),
6680
        },
6681
        "8100639E",
6682
        "ucvtf d1, x4",
6683
    ));
6684

6685
    insns.push((
6686
        Inst::IntToFpu {
6687
            op: IntToFpuOp::I64ToF64,
6688
            rd: writable_vreg(1),
6689
            rn: xreg(4),
6690
        },
6691
        "8100629E",
6692
        "scvtf d1, x4",
6693
    ));
6694

6695
    insns.push((
6696
        Inst::FpuCmp {
6697
            size: ScalarSize::Size32,
6698
            rn: vreg(23),
6699
            rm: vreg(24),
6700
        },
6701
        "E022381E",
6702
        "fcmp s23, s24",
6703
    ));
6704

6705
    insns.push((
6706
        Inst::FpuCmp {
6707
            size: ScalarSize::Size64,
6708
            rn: vreg(23),
6709
            rm: vreg(24),
6710
        },
6711
        "E022781E",
6712
        "fcmp d23, d24",
6713
    ));
6714

6715
    insns.push((
6716
        Inst::FpuLoad16 {
6717
            rd: writable_vreg(16),
6718
            mem: AMode::RegScaled {
6719
                rn: xreg(8),
6720
                rm: xreg(9),
6721
            },
6722
            flags: MemFlags::trusted(),
6723
        },
6724
        "1079697C",
6725
        "ldr h16, [x8, x9, LSL #1]",
6726
    ));
6727

6728
    insns.push((
6729
        Inst::FpuLoad32 {
6730
            rd: writable_vreg(16),
6731
            mem: AMode::RegScaled {
6732
                rn: xreg(8),
6733
                rm: xreg(9),
6734
            },
6735
            flags: MemFlags::trusted(),
6736
        },
6737
        "107969BC",
6738
        "ldr s16, [x8, x9, LSL #2]",
6739
    ));
6740

6741
    insns.push((
6742
        Inst::FpuLoad64 {
6743
            rd: writable_vreg(16),
6744
            mem: AMode::RegScaled {
6745
                rn: xreg(8),
6746
                rm: xreg(9),
6747
            },
6748
            flags: MemFlags::trusted(),
6749
        },
6750
        "107969FC",
6751
        "ldr d16, [x8, x9, LSL #3]",
6752
    ));
6753

6754
    insns.push((
6755
        Inst::FpuLoad128 {
6756
            rd: writable_vreg(16),
6757
            mem: AMode::RegScaled {
6758
                rn: xreg(8),
6759
                rm: xreg(9),
6760
            },
6761
            flags: MemFlags::trusted(),
6762
        },
6763
        "1079E93C",
6764
        "ldr q16, [x8, x9, LSL #4]",
6765
    ));
6766

6767
    insns.push((
6768
        Inst::FpuLoad32 {
6769
            rd: writable_vreg(16),
6770
            mem: AMode::Label {
6771
                label: MemLabel::PCRel(8),
6772
            },
6773
            flags: MemFlags::trusted(),
6774
        },
6775
        "5000001C",
6776
        "ldr s16, pc+8",
6777
    ));
6778

6779
    insns.push((
6780
        Inst::FpuLoad64 {
6781
            rd: writable_vreg(16),
6782
            mem: AMode::Label {
6783
                label: MemLabel::PCRel(8),
6784
            },
6785
            flags: MemFlags::trusted(),
6786
        },
6787
        "5000005C",
6788
        "ldr d16, pc+8",
6789
    ));
6790

6791
    insns.push((
6792
        Inst::FpuLoad128 {
6793
            rd: writable_vreg(16),
6794
            mem: AMode::Label {
6795
                label: MemLabel::PCRel(8),
6796
            },
6797
            flags: MemFlags::trusted(),
6798
        },
6799
        "5000009C",
6800
        "ldr q16, pc+8",
6801
    ));
6802

6803
    insns.push((
6804
        Inst::FpuStore16 {
6805
            rd: vreg(16),
6806
            mem: AMode::RegScaled {
6807
                rn: xreg(8),
6808
                rm: xreg(9),
6809
            },
6810
            flags: MemFlags::trusted(),
6811
        },
6812
        "1079297C",
6813
        "str h16, [x8, x9, LSL #1]",
6814
    ));
6815

6816
    insns.push((
6817
        Inst::FpuStore32 {
6818
            rd: vreg(16),
6819
            mem: AMode::RegScaled {
6820
                rn: xreg(8),
6821
                rm: xreg(9),
6822
            },
6823
            flags: MemFlags::trusted(),
6824
        },
6825
        "107929BC",
6826
        "str s16, [x8, x9, LSL #2]",
6827
    ));
6828

6829
    insns.push((
6830
        Inst::FpuStore64 {
6831
            rd: vreg(16),
6832
            mem: AMode::RegScaled {
6833
                rn: xreg(8),
6834
                rm: xreg(9),
6835
            },
6836
            flags: MemFlags::trusted(),
6837
        },
6838
        "107929FC",
6839
        "str d16, [x8, x9, LSL #3]",
6840
    ));
6841

6842
    insns.push((
6843
        Inst::FpuStore128 {
6844
            rd: vreg(16),
6845
            mem: AMode::RegScaled {
6846
                rn: xreg(8),
6847
                rm: xreg(9),
6848
            },
6849
            flags: MemFlags::trusted(),
6850
        },
6851
        "1079A93C",
6852
        "str q16, [x8, x9, LSL #4]",
6853
    ));
6854

6855
    insns.push((
6856
        Inst::FpuLoadP64 {
6857
            rt: writable_vreg(0),
6858
            rt2: writable_vreg(31),
6859
            mem: PairAMode::SignedOffset {
6860
                reg: xreg(0),
6861
                simm7: simm7_scaled_zero(F64),
6862
            },
6863
            flags: MemFlags::trusted(),
6864
        },
6865
        "007C406D",
6866
        "ldp d0, d31, [x0]",
6867
    ));
6868

6869
    insns.push((
6870
        Inst::FpuLoadP64 {
6871
            rt: writable_vreg(19),
6872
            rt2: writable_vreg(11),
6873
            mem: PairAMode::SPPreIndexed {
6874
                simm7: SImm7Scaled::maybe_from_i64(-512, F64).unwrap(),
6875
            },
6876
            flags: MemFlags::trusted(),
6877
        },
6878
        "F32FE06D",
6879
        "ldp d19, d11, [sp, #-512]!",
6880
    ));
6881

6882
    insns.push((
6883
        Inst::FpuLoadP64 {
6884
            rt: writable_vreg(7),
6885
            rt2: writable_vreg(20),
6886
            mem: PairAMode::SPPostIndexed {
6887
                simm7: SImm7Scaled::maybe_from_i64(64, F64).unwrap(),
6888
            },
6889
            flags: MemFlags::trusted(),
6890
        },
6891
        "E753C46C",
6892
        "ldp d7, d20, [sp], #64",
6893
    ));
6894

6895
    insns.push((
6896
        Inst::FpuStoreP64 {
6897
            rt: vreg(4),
6898
            rt2: vreg(26),
6899
            mem: PairAMode::SignedOffset {
6900
                reg: stack_reg(),
6901
                simm7: SImm7Scaled::maybe_from_i64(504, F64).unwrap(),
6902
            },
6903
            flags: MemFlags::trusted(),
6904
        },
6905
        "E4EB1F6D",
6906
        "stp d4, d26, [sp, #504]",
6907
    ));
6908

6909
    insns.push((
6910
        Inst::FpuStoreP64 {
6911
            rt: vreg(16),
6912
            rt2: vreg(8),
6913
            mem: PairAMode::SPPreIndexed {
6914
                simm7: SImm7Scaled::maybe_from_i64(48, F64).unwrap(),
6915
            },
6916
            flags: MemFlags::trusted(),
6917
        },
6918
        "F023836D",
6919
        "stp d16, d8, [sp, #48]!",
6920
    ));
6921

6922
    insns.push((
6923
        Inst::FpuStoreP64 {
6924
            rt: vreg(5),
6925
            rt2: vreg(6),
6926
            mem: PairAMode::SPPostIndexed {
6927
                simm7: SImm7Scaled::maybe_from_i64(-32, F64).unwrap(),
6928
            },
6929
            flags: MemFlags::trusted(),
6930
        },
6931
        "E51BBE6C",
6932
        "stp d5, d6, [sp], #-32",
6933
    ));
6934

6935
    insns.push((
6936
        Inst::FpuLoadP128 {
6937
            rt: writable_vreg(0),
6938
            rt2: writable_vreg(17),
6939
            mem: PairAMode::SignedOffset {
6940
                reg: xreg(3),
6941
                simm7: simm7_scaled_zero(I8X16),
6942
            },
6943
            flags: MemFlags::trusted(),
6944
        },
6945
        "604440AD",
6946
        "ldp q0, q17, [x3]",
6947
    ));
6948

6949
    insns.push((
6950
        Inst::FpuLoadP128 {
6951
            rt: writable_vreg(29),
6952
            rt2: writable_vreg(9),
6953
            mem: PairAMode::SPPreIndexed {
6954
                simm7: SImm7Scaled::maybe_from_i64(-1024, I8X16).unwrap(),
6955
            },
6956
            flags: MemFlags::trusted(),
6957
        },
6958
        "FD27E0AD",
6959
        "ldp q29, q9, [sp, #-1024]!",
6960
    ));
6961

6962
    insns.push((
6963
        Inst::FpuLoadP128 {
6964
            rt: writable_vreg(10),
6965
            rt2: writable_vreg(20),
6966
            mem: PairAMode::SPPostIndexed {
6967
                simm7: SImm7Scaled::maybe_from_i64(256, I8X16).unwrap(),
6968
            },
6969
            flags: MemFlags::trusted(),
6970
        },
6971
        "EA53C8AC",
6972
        "ldp q10, q20, [sp], #256",
6973
    ));
6974

6975
    insns.push((
6976
        Inst::FpuStoreP128 {
6977
            rt: vreg(9),
6978
            rt2: vreg(31),
6979
            mem: PairAMode::SignedOffset {
6980
                reg: stack_reg(),
6981
                simm7: SImm7Scaled::maybe_from_i64(1008, I8X16).unwrap(),
6982
            },
6983
            flags: MemFlags::trusted(),
6984
        },
6985
        "E9FF1FAD",
6986
        "stp q9, q31, [sp, #1008]",
6987
    ));
6988

6989
    insns.push((
6990
        Inst::FpuStoreP128 {
6991
            rt: vreg(27),
6992
            rt2: vreg(13),
6993
            mem: PairAMode::SPPreIndexed {
6994
                simm7: SImm7Scaled::maybe_from_i64(-192, I8X16).unwrap(),
6995
            },
6996
            flags: MemFlags::trusted(),
6997
        },
6998
        "FB37BAAD",
6999
        "stp q27, q13, [sp, #-192]!",
7000
    ));
7001

7002
    insns.push((
7003
        Inst::FpuStoreP128 {
7004
            rt: vreg(18),
7005
            rt2: vreg(22),
7006
            mem: PairAMode::SPPostIndexed {
7007
                simm7: SImm7Scaled::maybe_from_i64(304, I8X16).unwrap(),
7008
            },
7009
            flags: MemFlags::trusted(),
7010
        },
7011
        "F2DB89AC",
7012
        "stp q18, q22, [sp], #304",
7013
    ));
7014

7015
    insns.push((
7016
        Inst::FpuCSel16 {
7017
            rd: writable_vreg(1),
7018
            rn: vreg(2),
7019
            rm: vreg(3),
7020
            cond: Cond::Hi,
7021
        },
7022
        "418CE31E",
7023
        "fcsel h1, h2, h3, hi",
7024
    ));
7025

7026
    insns.push((
7027
        Inst::FpuCSel32 {
7028
            rd: writable_vreg(1),
7029
            rn: vreg(2),
7030
            rm: vreg(3),
7031
            cond: Cond::Hi,
7032
        },
7033
        "418C231E",
7034
        "fcsel s1, s2, s3, hi",
7035
    ));
7036

7037
    insns.push((
7038
        Inst::FpuCSel64 {
7039
            rd: writable_vreg(1),
7040
            rn: vreg(2),
7041
            rm: vreg(3),
7042
            cond: Cond::Eq,
7043
        },
7044
        "410C631E",
7045
        "fcsel d1, d2, d3, eq",
7046
    ));
7047

7048
    insns.push((
7049
        Inst::FpuRound {
7050
            rd: writable_vreg(23),
7051
            rn: vreg(24),
7052
            op: FpuRoundMode::Minus32,
7053
        },
7054
        "1743251E",
7055
        "frintm s23, s24",
7056
    ));
7057
    insns.push((
7058
        Inst::FpuRound {
7059
            rd: writable_vreg(23),
7060
            rn: vreg(24),
7061
            op: FpuRoundMode::Minus64,
7062
        },
7063
        "1743651E",
7064
        "frintm d23, d24",
7065
    ));
7066
    insns.push((
7067
        Inst::FpuRound {
7068
            rd: writable_vreg(23),
7069
            rn: vreg(24),
7070
            op: FpuRoundMode::Plus32,
7071
        },
7072
        "17C3241E",
7073
        "frintp s23, s24",
7074
    ));
7075
    insns.push((
7076
        Inst::FpuRound {
7077
            rd: writable_vreg(23),
7078
            rn: vreg(24),
7079
            op: FpuRoundMode::Plus64,
7080
        },
7081
        "17C3641E",
7082
        "frintp d23, d24",
7083
    ));
7084
    insns.push((
7085
        Inst::FpuRound {
7086
            rd: writable_vreg(23),
7087
            rn: vreg(24),
7088
            op: FpuRoundMode::Zero32,
7089
        },
7090
        "17C3251E",
7091
        "frintz s23, s24",
7092
    ));
7093
    insns.push((
7094
        Inst::FpuRound {
7095
            rd: writable_vreg(23),
7096
            rn: vreg(24),
7097
            op: FpuRoundMode::Zero64,
7098
        },
7099
        "17C3651E",
7100
        "frintz d23, d24",
7101
    ));
7102
    insns.push((
7103
        Inst::FpuRound {
7104
            rd: writable_vreg(23),
7105
            rn: vreg(24),
7106
            op: FpuRoundMode::Nearest32,
7107
        },
7108
        "1743241E",
7109
        "frintn s23, s24",
7110
    ));
7111
    insns.push((
7112
        Inst::FpuRound {
7113
            rd: writable_vreg(23),
7114
            rn: vreg(24),
7115
            op: FpuRoundMode::Nearest64,
7116
        },
7117
        "1743641E",
7118
        "frintn d23, d24",
7119
    ));
7120

7121
    insns.push((
7122
        Inst::AtomicRMWLoop {
7123
            ty: I8,
7124
            op: AtomicRMWLoopOp::Sub,
7125
            flags: MemFlags::trusted(),
7126
            addr: xreg(25),
7127
            operand: xreg(26),
7128
            oldval: writable_xreg(27),
7129
            scratch1: writable_xreg(24),
7130
            scratch2: writable_xreg(28),
7131
        },
7132
        "3BFF5F087C031A4B3CFF1808B8FFFFB5",
7133
        "atomic_rmw_loop_sub_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7134
    ));
7135
    insns.push((
7136
        Inst::AtomicRMWLoop {
7137
            ty: I16,
7138
            op: AtomicRMWLoopOp::Eor,
7139
            flags: MemFlags::trusted(),
7140
            addr: xreg(25),
7141
            operand: xreg(26),
7142
            oldval: writable_xreg(27),
7143
            scratch1: writable_xreg(24),
7144
            scratch2: writable_xreg(28),
7145
        },
7146
        "3BFF5F487C031A4A3CFF1848B8FFFFB5",
7147
        "atomic_rmw_loop_eor_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7148
    ));
7149
    insns.push((
7150
        Inst::AtomicRMWLoop {
7151
            ty: I8,
7152
            op: AtomicRMWLoopOp::Add,
7153
            flags: MemFlags::trusted(),
7154
            addr: xreg(25),
7155
            operand: xreg(26),
7156
            oldval: writable_xreg(27),
7157
            scratch1: writable_xreg(24),
7158
            scratch2: writable_xreg(28),
7159
        },
7160
        "3BFF5F087C031A0B3CFF1808B8FFFFB5",
7161
        "atomic_rmw_loop_add_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7162
    ));
7163
    insns.push((
7164
        Inst::AtomicRMWLoop {
7165
            ty: I32,
7166
            op: AtomicRMWLoopOp::Orr,
7167
            flags: MemFlags::trusted(),
7168
            addr: xreg(25),
7169
            operand: xreg(26),
7170
            oldval: writable_xreg(27),
7171
            scratch1: writable_xreg(24),
7172
            scratch2: writable_xreg(28),
7173
        },
7174
        "3BFF5F887C031A2A3CFF1888B8FFFFB5",
7175
        "atomic_rmw_loop_orr_32 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7176
    ));
7177
    insns.push((
7178
        Inst::AtomicRMWLoop {
7179
            ty: I64,
7180
            op: AtomicRMWLoopOp::And,
7181
            flags: MemFlags::trusted(),
7182
            addr: xreg(25),
7183
            operand: xreg(26),
7184
            oldval: writable_xreg(27),
7185
            scratch1: writable_xreg(24),
7186
            scratch2: writable_xreg(28),
7187
        },
7188
        "3BFF5FC87C031A8A3CFF18C8B8FFFFB5",
7189
        "atomic_rmw_loop_and_64 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7190
    ));
7191
    insns.push((
7192
        Inst::AtomicRMWLoop {
7193
            ty: I8,
7194
            op: AtomicRMWLoopOp::Xchg,
7195
            flags: MemFlags::trusted(),
7196
            addr: xreg(25),
7197
            operand: xreg(26),
7198
            oldval: writable_xreg(27),
7199
            scratch1: writable_xreg(24),
7200
            scratch2: writable_xreg(28),
7201
        },
7202
        "3BFF5F083AFF1808D8FFFFB5",
7203
        "atomic_rmw_loop_xchg_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7204
    ));
7205
    insns.push((
7206
        Inst::AtomicRMWLoop {
7207
            ty: I16,
7208
            op: AtomicRMWLoopOp::Nand,
7209
            flags: MemFlags::trusted(),
7210
            addr: xreg(25),
7211
            operand: xreg(26),
7212
            oldval: writable_xreg(27),
7213
            scratch1: writable_xreg(24),
7214
            scratch2: writable_xreg(28),
7215
        },
7216
        "3BFF5F487C031A0AFC033C2A3CFF184898FFFFB5",
7217
        "atomic_rmw_loop_nand_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7218
    ));
7219
    insns.push((
7220
        Inst::AtomicRMWLoop {
7221
            ty: I16,
7222
            op: AtomicRMWLoopOp::Smin,
7223
            flags: MemFlags::trusted(),
7224
            addr: xreg(25),
7225
            operand: xreg(26),
7226
            oldval: writable_xreg(27),
7227
            scratch1: writable_xreg(24),
7228
            scratch2: writable_xreg(28),
7229
        },
7230
        "3BFF5F487B3F00137FA33A6B7CB39A9A3CFF184878FFFFB5",
7231
        "atomic_rmw_loop_smin_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7232
    ));
7233
    insns.push((
7234
        Inst::AtomicRMWLoop {
7235
            ty: I32,
7236
            op: AtomicRMWLoopOp::Smin,
7237
            flags: MemFlags::trusted(),
7238
            addr: xreg(25),
7239
            operand: xreg(26),
7240
            oldval: writable_xreg(27),
7241
            scratch1: writable_xreg(24),
7242
            scratch2: writable_xreg(28),
7243
        },
7244
        "3BFF5F887F031A6B7CB39A9A3CFF188898FFFFB5",
7245
        "atomic_rmw_loop_smin_32 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7246
    ));
7247
    insns.push((
7248
        Inst::AtomicRMWLoop {
7249
            ty: I64,
7250
            op: AtomicRMWLoopOp::Smax,
7251
            flags: MemFlags::trusted(),
7252
            addr: xreg(25),
7253
            operand: xreg(26),
7254
            oldval: writable_xreg(27),
7255
            scratch1: writable_xreg(24),
7256
            scratch2: writable_xreg(28),
7257
        },
7258
        "3BFF5FC87F031AEB7CC39A9A3CFF18C898FFFFB5",
7259
        "atomic_rmw_loop_smax_64 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7260
    ));
7261
    insns.push((
7262
        Inst::AtomicRMWLoop {
7263
            ty: I8,
7264
            op: AtomicRMWLoopOp::Smax,
7265
            flags: MemFlags::trusted(),
7266
            addr: xreg(25),
7267
            operand: xreg(26),
7268
            oldval: writable_xreg(27),
7269
            scratch1: writable_xreg(24),
7270
            scratch2: writable_xreg(28),
7271
        },
7272
        "3BFF5F087B1F00137F833A6B7CC39A9A3CFF180878FFFFB5",
7273
        "atomic_rmw_loop_smax_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7274
    ));
7275
    insns.push((
7276
        Inst::AtomicRMWLoop {
7277
            ty: I8,
7278
            op: AtomicRMWLoopOp::Umin,
7279
            flags: MemFlags::trusted(),
7280
            addr: xreg(25),
7281
            operand: xreg(26),
7282
            oldval: writable_xreg(27),
7283
            scratch1: writable_xreg(24),
7284
            scratch2: writable_xreg(28),
7285
        },
7286
        "3BFF5F087F031A6B7C339A9A3CFF180898FFFFB5",
7287
        "atomic_rmw_loop_umin_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7288
    ));
7289
    insns.push((
7290
        Inst::AtomicRMWLoop {
7291
            ty: I16,
7292
            op: AtomicRMWLoopOp::Umax,
7293
            flags: MemFlags::trusted(),
7294
            addr: xreg(25),
7295
            operand: xreg(26),
7296
            oldval: writable_xreg(27),
7297
            scratch1: writable_xreg(24),
7298
            scratch2: writable_xreg(28),
7299
        },
7300
        "3BFF5F487F031A6B7C839A9A3CFF184898FFFFB5",
7301
        "atomic_rmw_loop_umax_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7302
    ));
7303

7304
    insns.push((
7305
        Inst::AtomicRMW {
7306
            ty: I8,
7307
            op: AtomicRMWOp::Add,
7308
            rs: xreg(1),
7309
            rt: writable_xreg(2),
7310
            rn: xreg(3),
7311
            flags: MemFlags::trusted(),
7312
        },
7313
        "6200E138",
7314
        "ldaddalb w1, w2, [x3]",
7315
    ));
7316
    insns.push((
7317
        Inst::AtomicRMW {
7318
            ty: I16,
7319
            op: AtomicRMWOp::Add,
7320
            rs: xreg(4),
7321
            rt: writable_xreg(5),
7322
            rn: xreg(6),
7323
            flags: MemFlags::trusted(),
7324
        },
7325
        "C500E478",
7326
        "ldaddalh w4, w5, [x6]",
7327
    ));
7328
    insns.push((
7329
        Inst::AtomicRMW {
7330
            ty: I32,
7331
            op: AtomicRMWOp::Add,
7332
            rs: xreg(7),
7333
            rt: writable_xreg(8),
7334
            rn: xreg(9),
7335
            flags: MemFlags::trusted(),
7336
        },
7337
        "2801E7B8",
7338
        "ldaddal w7, w8, [x9]",
7339
    ));
7340
    insns.push((
7341
        Inst::AtomicRMW {
7342
            ty: I64,
7343
            op: AtomicRMWOp::Add,
7344
            rs: xreg(10),
7345
            rt: writable_xreg(11),
7346
            rn: xreg(12),
7347
            flags: MemFlags::trusted(),
7348
        },
7349
        "8B01EAF8",
7350
        "ldaddal x10, x11, [x12]",
7351
    ));
7352
    insns.push((
7353
        Inst::AtomicRMW {
7354
            ty: I8,
7355
            op: AtomicRMWOp::Clr,
7356
            rs: xreg(13),
7357
            rt: writable_xreg(14),
7358
            rn: xreg(15),
7359
            flags: MemFlags::trusted(),
7360
        },
7361
        "EE11ED38",
7362
        "ldclralb w13, w14, [x15]",
7363
    ));
7364
    insns.push((
7365
        Inst::AtomicRMW {
7366
            ty: I16,
7367
            op: AtomicRMWOp::Clr,
7368
            rs: xreg(16),
7369
            rt: writable_xreg(17),
7370
            rn: xreg(18),
7371
            flags: MemFlags::trusted(),
7372
        },
7373
        "5112F078",
7374
        "ldclralh w16, w17, [x18]",
7375
    ));
7376
    insns.push((
7377
        Inst::AtomicRMW {
7378
            ty: I32,
7379
            op: AtomicRMWOp::Clr,
7380
            rs: xreg(19),
7381
            rt: writable_xreg(20),
7382
            rn: xreg(21),
7383
            flags: MemFlags::trusted(),
7384
        },
7385
        "B412F3B8",
7386
        "ldclral w19, w20, [x21]",
7387
    ));
7388
    insns.push((
7389
        Inst::AtomicRMW {
7390
            ty: I64,
7391
            op: AtomicRMWOp::Clr,
7392
            rs: xreg(22),
7393
            rt: writable_xreg(23),
7394
            rn: xreg(24),
7395
            flags: MemFlags::trusted(),
7396
        },
7397
        "1713F6F8",
7398
        "ldclral x22, x23, [x24]",
7399
    ));
7400
    insns.push((
7401
        Inst::AtomicRMW {
7402
            ty: I8,
7403
            op: AtomicRMWOp::Eor,
7404
            rs: xreg(25),
7405
            rt: writable_xreg(26),
7406
            rn: xreg(27),
7407
            flags: MemFlags::trusted(),
7408
        },
7409
        "7A23F938",
7410
        "ldeoralb w25, w26, [x27]",
7411
    ));
7412
    insns.push((
7413
        Inst::AtomicRMW {
7414
            ty: I16,
7415
            op: AtomicRMWOp::Eor,
7416
            rs: xreg(28),
7417
            rt: writable_xreg(29),
7418
            rn: xreg(30),
7419
            flags: MemFlags::trusted(),
7420
        },
7421
        "DD23FC78",
7422
        "ldeoralh w28, fp, [lr]",
7423
    ));
7424
    insns.push((
7425
        Inst::AtomicRMW {
7426
            ty: I32,
7427
            op: AtomicRMWOp::Eor,
7428
            rs: xreg(29),
7429
            rt: writable_xreg(28),
7430
            rn: xreg(27),
7431
            flags: MemFlags::trusted(),
7432
        },
7433
        "7C23FDB8",
7434
        "ldeoral fp, w28, [x27]",
7435
    ));
7436
    insns.push((
7437
        Inst::AtomicRMW {
7438
            ty: I64,
7439
            op: AtomicRMWOp::Eor,
7440
            rs: xreg(26),
7441
            rt: writable_xreg(25),
7442
            rn: xreg(24),
7443
            flags: MemFlags::trusted(),
7444
        },
7445
        "1923FAF8",
7446
        "ldeoral x26, x25, [x24]",
7447
    ));
7448
    insns.push((
7449
        Inst::AtomicRMW {
7450
            ty: I8,
7451
            op: AtomicRMWOp::Set,
7452
            rs: xreg(23),
7453
            rt: writable_xreg(22),
7454
            rn: xreg(21),
7455
            flags: MemFlags::trusted(),
7456
        },
7457
        "B632F738",
7458
        "ldsetalb w23, w22, [x21]",
7459
    ));
7460
    insns.push((
7461
        Inst::AtomicRMW {
7462
            ty: I16,
7463
            op: AtomicRMWOp::Set,
7464
            rs: xreg(20),
7465
            rt: writable_xreg(19),
7466
            rn: xreg(18),
7467
            flags: MemFlags::trusted(),
7468
        },
7469
        "5332F478",
7470
        "ldsetalh w20, w19, [x18]",
7471
    ));
7472
    insns.push((
7473
        Inst::AtomicRMW {
7474
            ty: I32,
7475
            op: AtomicRMWOp::Set,
7476
            rs: xreg(17),
7477
            rt: writable_xreg(16),
7478
            rn: xreg(15),
7479
            flags: MemFlags::trusted(),
7480
        },
7481
        "F031F1B8",
7482
        "ldsetal w17, w16, [x15]",
7483
    ));
7484
    insns.push((
7485
        Inst::AtomicRMW {
7486
            ty: I64,
7487
            op: AtomicRMWOp::Set,
7488
            rs: xreg(14),
7489
            rt: writable_xreg(13),
7490
            rn: xreg(12),
7491
            flags: MemFlags::trusted(),
7492
        },
7493
        "8D31EEF8",
7494
        "ldsetal x14, x13, [x12]",
7495
    ));
7496
    insns.push((
7497
        Inst::AtomicRMW {
7498
            ty: I8,
7499
            op: AtomicRMWOp::Smax,
7500
            rs: xreg(11),
7501
            rt: writable_xreg(10),
7502
            rn: xreg(9),
7503
            flags: MemFlags::trusted(),
7504
        },
7505
        "2A41EB38",
7506
        "ldsmaxalb w11, w10, [x9]",
7507
    ));
7508
    insns.push((
7509
        Inst::AtomicRMW {
7510
            ty: I16,
7511
            op: AtomicRMWOp::Smax,
7512
            rs: xreg(8),
7513
            rt: writable_xreg(7),
7514
            rn: xreg(6),
7515
            flags: MemFlags::trusted(),
7516
        },
7517
        "C740E878",
7518
        "ldsmaxalh w8, w7, [x6]",
7519
    ));
7520
    insns.push((
7521
        Inst::AtomicRMW {
7522
            ty: I32,
7523
            op: AtomicRMWOp::Smax,
7524
            rs: xreg(5),
7525
            rt: writable_xreg(4),
7526
            rn: xreg(3),
7527
            flags: MemFlags::trusted(),
7528
        },
7529
        "6440E5B8",
7530
        "ldsmaxal w5, w4, [x3]",
7531
    ));
7532
    insns.push((
7533
        Inst::AtomicRMW {
7534
            ty: I64,
7535
            op: AtomicRMWOp::Smax,
7536
            rs: xreg(2),
7537
            rt: writable_xreg(1),
7538
            rn: xreg(0),
7539
            flags: MemFlags::trusted(),
7540
        },
7541
        "0140E2F8",
7542
        "ldsmaxal x2, x1, [x0]",
7543
    ));
7544
    insns.push((
7545
        Inst::AtomicRMW {
7546
            ty: I8,
7547
            op: AtomicRMWOp::Smin,
7548
            rs: xreg(1),
7549
            rt: writable_xreg(2),
7550
            rn: xreg(3),
7551
            flags: MemFlags::trusted(),
7552
        },
7553
        "6250E138",
7554
        "ldsminalb w1, w2, [x3]",
7555
    ));
7556
    insns.push((
7557
        Inst::AtomicRMW {
7558
            ty: I16,
7559
            op: AtomicRMWOp::Smin,
7560
            rs: xreg(4),
7561
            rt: writable_xreg(5),
7562
            rn: xreg(6),
7563
            flags: MemFlags::trusted(),
7564
        },
7565
        "C550E478",
7566
        "ldsminalh w4, w5, [x6]",
7567
    ));
7568
    insns.push((
7569
        Inst::AtomicRMW {
7570
            ty: I32,
7571
            op: AtomicRMWOp::Smin,
7572
            rs: xreg(7),
7573
            rt: writable_xreg(8),
7574
            rn: xreg(9),
7575
            flags: MemFlags::trusted(),
7576
        },
7577
        "2851E7B8",
7578
        "ldsminal w7, w8, [x9]",
7579
    ));
7580
    insns.push((
7581
        Inst::AtomicRMW {
7582
            ty: I64,
7583
            op: AtomicRMWOp::Smin,
7584
            rs: xreg(10),
7585
            rt: writable_xreg(11),
7586
            rn: xreg(12),
7587
            flags: MemFlags::trusted(),
7588
        },
7589
        "8B51EAF8",
7590
        "ldsminal x10, x11, [x12]",
7591
    ));
7592
    insns.push((
7593
        Inst::AtomicRMW {
7594
            ty: I8,
7595
            op: AtomicRMWOp::Umax,
7596
            rs: xreg(13),
7597
            rt: writable_xreg(14),
7598
            rn: xreg(15),
7599
            flags: MemFlags::trusted(),
7600
        },
7601
        "EE61ED38",
7602
        "ldumaxalb w13, w14, [x15]",
7603
    ));
7604
    insns.push((
7605
        Inst::AtomicRMW {
7606
            ty: I16,
7607
            op: AtomicRMWOp::Umax,
7608
            rs: xreg(16),
7609
            rt: writable_xreg(17),
7610
            rn: xreg(18),
7611
            flags: MemFlags::trusted(),
7612
        },
7613
        "5162F078",
7614
        "ldumaxalh w16, w17, [x18]",
7615
    ));
7616
    insns.push((
7617
        Inst::AtomicRMW {
7618
            ty: I32,
7619
            op: AtomicRMWOp::Umax,
7620
            rs: xreg(19),
7621
            rt: writable_xreg(20),
7622
            rn: xreg(21),
7623
            flags: MemFlags::trusted(),
7624
        },
7625
        "B462F3B8",
7626
        "ldumaxal w19, w20, [x21]",
7627
    ));
7628
    insns.push((
7629
        Inst::AtomicRMW {
7630
            ty: I64,
7631
            op: AtomicRMWOp::Umax,
7632
            rs: xreg(22),
7633
            rt: writable_xreg(23),
7634
            rn: xreg(24),
7635
            flags: MemFlags::trusted(),
7636
        },
7637
        "1763F6F8",
7638
        "ldumaxal x22, x23, [x24]",
7639
    ));
7640
    insns.push((
7641
        Inst::AtomicRMW {
7642
            ty: I8,
7643
            op: AtomicRMWOp::Umin,
7644
            rs: xreg(16),
7645
            rt: writable_xreg(17),
7646
            rn: xreg(18),
7647
            flags: MemFlags::trusted(),
7648
        },
7649
        "5172F038",
7650
        "lduminalb w16, w17, [x18]",
7651
    ));
7652
    insns.push((
7653
        Inst::AtomicRMW {
7654
            ty: I16,
7655
            op: AtomicRMWOp::Umin,
7656
            rs: xreg(19),
7657
            rt: writable_xreg(20),
7658
            rn: xreg(21),
7659
            flags: MemFlags::trusted(),
7660
        },
7661
        "B472F378",
7662
        "lduminalh w19, w20, [x21]",
7663
    ));
7664
    insns.push((
7665
        Inst::AtomicRMW {
7666
            ty: I32,
7667
            op: AtomicRMWOp::Umin,
7668
            rs: xreg(22),
7669
            rt: writable_xreg(23),
7670
            rn: xreg(24),
7671
            flags: MemFlags::trusted(),
7672
        },
7673
        "1773F6B8",
7674
        "lduminal w22, w23, [x24]",
7675
    ));
7676
    insns.push((
7677
        Inst::AtomicRMW {
7678
            ty: I64,
7679
            op: AtomicRMWOp::Umin,
7680
            rs: xreg(25),
7681
            rt: writable_xreg(26),
7682
            rn: xreg(27),
7683
            flags: MemFlags::trusted(),
7684
        },
7685
        "7A73F9F8",
7686
        "lduminal x25, x26, [x27]",
7687
    ));
7688
    insns.push((
7689
        Inst::AtomicRMW {
7690
            ty: I8,
7691
            op: AtomicRMWOp::Swp,
7692
            rs: xreg(28),
7693
            rt: writable_xreg(29),
7694
            rn: xreg(30),
7695
            flags: MemFlags::trusted(),
7696
        },
7697
        "DD83FC38",
7698
        "swpalb w28, fp, [lr]",
7699
    ));
7700
    insns.push((
7701
        Inst::AtomicRMW {
7702
            ty: I16,
7703
            op: AtomicRMWOp::Swp,
7704
            rs: xreg(0),
7705
            rt: writable_xreg(1),
7706
            rn: xreg(2),
7707
            flags: MemFlags::trusted(),
7708
        },
7709
        "4180E078",
7710
        "swpalh w0, w1, [x2]",
7711
    ));
7712
    insns.push((
7713
        Inst::AtomicRMW {
7714
            ty: I32,
7715
            op: AtomicRMWOp::Swp,
7716
            rs: xreg(3),
7717
            rt: writable_xreg(4),
7718
            rn: xreg(5),
7719
            flags: MemFlags::trusted(),
7720
        },
7721
        "A480E3B8",
7722
        "swpal w3, w4, [x5]",
7723
    ));
7724
    insns.push((
7725
        Inst::AtomicRMW {
7726
            ty: I64,
7727
            op: AtomicRMWOp::Swp,
7728
            rs: xreg(6),
7729
            rt: writable_xreg(7),
7730
            rn: xreg(8),
7731
            flags: MemFlags::trusted(),
7732
        },
7733
        "0781E6F8",
7734
        "swpal x6, x7, [x8]",
7735
    ));
7736

7737
    insns.push((
7738
        Inst::AtomicCAS {
7739
            rd: writable_xreg(28),
7740
            rs: xreg(28),
7741
            rt: xreg(20),
7742
            rn: xreg(10),
7743
            ty: I8,
7744
            flags: MemFlags::trusted(),
7745
        },
7746
        "54FDFC08",
7747
        "casalb w28, w28, w20, [x10]",
7748
    ));
7749
    insns.push((
7750
        Inst::AtomicCAS {
7751
            rd: writable_xreg(2),
7752
            rs: xreg(2),
7753
            rt: xreg(19),
7754
            rn: xreg(23),
7755
            ty: I16,
7756
            flags: MemFlags::trusted(),
7757
        },
7758
        "F3FEE248",
7759
        "casalh w2, w2, w19, [x23]",
7760
    ));
7761
    insns.push((
7762
        Inst::AtomicCAS {
7763
            rd: writable_xreg(0),
7764
            rs: xreg(0),
7765
            rt: zero_reg(),
7766
            rn: stack_reg(),
7767
            ty: I32,
7768
            flags: MemFlags::trusted(),
7769
        },
7770
        "FFFFE088",
7771
        "casal w0, w0, wzr, [sp]",
7772
    ));
7773
    insns.push((
7774
        Inst::AtomicCAS {
7775
            rd: writable_xreg(7),
7776
            rs: xreg(7),
7777
            rt: xreg(15),
7778
            rn: xreg(27),
7779
            ty: I64,
7780
            flags: MemFlags::trusted(),
7781
        },
7782
        "6FFFE7C8",
7783
        "casal x7, x7, x15, [x27]",
7784
    ));
7785
    insns.push((
7786
        Inst::AtomicCASLoop {
7787
            ty: I8,
7788
            flags: MemFlags::trusted(),
7789
            addr: xreg(25),
7790
            expected: xreg(26),
7791
            replacement: xreg(28),
7792
            oldval: writable_xreg(27),
7793
            scratch: writable_xreg(24),
7794
        },
7795
        "3BFF5F087F033AEB610000543CFF180898FFFFB5",
7796
        "atomic_cas_loop_8 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7797
    ));
7798

7799
    insns.push((
7800
        Inst::AtomicCASLoop {
7801
            ty: I16,
7802
            flags: MemFlags::trusted(),
7803
            addr: xreg(25),
7804
            expected: xreg(26),
7805
            replacement: xreg(28),
7806
            oldval: writable_xreg(27),
7807
            scratch: writable_xreg(24),
7808
        },
7809
        "3BFF5F487F233AEB610000543CFF184898FFFFB5",
7810
        "atomic_cas_loop_16 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7811
    ));
7812

7813
    insns.push((
7814
        Inst::AtomicCASLoop {
7815
            ty: I32,
7816
            flags: MemFlags::trusted(),
7817
            addr: xreg(25),
7818
            expected: xreg(26),
7819
            replacement: xreg(28),
7820
            oldval: writable_xreg(27),
7821
            scratch: writable_xreg(24),
7822
        },
7823
        "3BFF5F887F031AEB610000543CFF188898FFFFB5",
7824
        "atomic_cas_loop_32 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7825
    ));
7826

7827
    insns.push((
7828
        Inst::AtomicCASLoop {
7829
            ty: I64,
7830
            flags: MemFlags::trusted(),
7831
            addr: xreg(25),
7832
            expected: xreg(26),
7833
            replacement: xreg(28),
7834
            oldval: writable_xreg(27),
7835
            scratch: writable_xreg(24),
7836
        },
7837
        "3BFF5FC87F031AEB610000543CFF18C898FFFFB5",
7838
        "atomic_cas_loop_64 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7839
    ));
7840

7841
    insns.push((
7842
        Inst::LoadAcquire {
7843
            access_ty: I8,
7844
            rt: writable_xreg(7),
7845
            rn: xreg(28),
7846
            flags: MemFlags::trusted(),
7847
        },
7848
        "87FFDF08",
7849
        "ldarb w7, [x28]",
7850
    ));
7851

7852
    insns.push((
7853
        Inst::LoadAcquire {
7854
            access_ty: I16,
7855
            rt: writable_xreg(2),
7856
            rn: xreg(3),
7857
            flags: MemFlags::trusted(),
7858
        },
7859
        "62FCDF48",
7860
        "ldarh w2, [x3]",
7861
    ));
7862

7863
    insns.push((
7864
        Inst::LoadAcquire {
7865
            access_ty: I32,
7866
            rt: writable_xreg(15),
7867
            rn: xreg(0),
7868
            flags: MemFlags::trusted(),
7869
        },
7870
        "0FFCDF88",
7871
        "ldar w15, [x0]",
7872
    ));
7873

7874
    insns.push((
7875
        Inst::LoadAcquire {
7876
            access_ty: I64,
7877
            rt: writable_xreg(28),
7878
            rn: xreg(7),
7879
            flags: MemFlags::trusted(),
7880
        },
7881
        "FCFCDFC8",
7882
        "ldar x28, [x7]",
7883
    ));
7884

7885
    insns.push((
7886
        Inst::StoreRelease {
7887
            access_ty: I8,
7888
            rt: xreg(7),
7889
            rn: xreg(28),
7890
            flags: MemFlags::trusted(),
7891
        },
7892
        "87FF9F08",
7893
        "stlrb w7, [x28]",
7894
    ));
7895

7896
    insns.push((
7897
        Inst::StoreRelease {
7898
            access_ty: I16,
7899
            rt: xreg(2),
7900
            rn: xreg(3),
7901
            flags: MemFlags::trusted(),
7902
        },
7903
        "62FC9F48",
7904
        "stlrh w2, [x3]",
7905
    ));
7906

7907
    insns.push((
7908
        Inst::StoreRelease {
7909
            access_ty: I32,
7910
            rt: xreg(15),
7911
            rn: xreg(0),
7912
            flags: MemFlags::trusted(),
7913
        },
7914
        "0FFC9F88",
7915
        "stlr w15, [x0]",
7916
    ));
7917

7918
    insns.push((
7919
        Inst::StoreRelease {
7920
            access_ty: I64,
7921
            rt: xreg(28),
7922
            rn: xreg(7),
7923
            flags: MemFlags::trusted(),
7924
        },
7925
        "FCFC9FC8",
7926
        "stlr x28, [x7]",
7927
    ));
7928

7929
    insns.push((Inst::Fence {}, "BF3B03D5", "dmb ish"));
7930

7931
    let flags = settings::Flags::new(settings::builder());
7932
    let emit_info = EmitInfo::new(flags);
7933
    for (insn, expected_encoding, expected_printing) in insns {
7934
        println!("AArch64: {insn:?}, {expected_encoding}, {expected_printing}");
7935

7936
        // Check the printed text is as expected.
7937
        let actual_printing = insn.print_with_state(&mut EmitState::default());
7938
        assert_eq!(expected_printing, actual_printing);
7939

7940
        let mut buffer = MachBuffer::new();
7941
        insn.emit(&mut buffer, &emit_info, &mut Default::default());
7942
        let buffer = buffer.finish(&Default::default(), &mut Default::default());
7943
        let actual_encoding = &buffer.stringify_code_bytes();
7944
        assert_eq!(expected_encoding, actual_encoding);
7945
    }
7946
}
7947

7948
#[test]
7949
fn test_cond_invert() {
7950
    for cond in vec![
7951
        Cond::Eq,
7952
        Cond::Ne,
7953
        Cond::Hs,
7954
        Cond::Lo,
7955
        Cond::Mi,
7956
        Cond::Pl,
7957
        Cond::Vs,
7958
        Cond::Vc,
7959
        Cond::Hi,
7960
        Cond::Ls,
7961
        Cond::Ge,
7962
        Cond::Lt,
7963
        Cond::Gt,
7964
        Cond::Le,
7965
        Cond::Al,
7966
        Cond::Nv,
7967
    ]
7968
    .into_iter()
7969
    {
7970
        assert_eq!(cond.invert().invert(), cond);
7971
    }
7972
}
7973

7974
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