Path: blob/main/cranelift/native/src/riscv.rs
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use cranelift_codegen::settings::Configurable;1use std::fs::File;2use std::io::{BufRead, BufReader};34pub fn hwcap_detect(isa_builder: &mut dyn Configurable) -> Result<(), &'static str> {5let v = unsafe { libc::getauxval(libc::AT_HWCAP) };67const HWCAP_RISCV_EXT_A: libc::c_ulong = 1 << (b'a' - b'a');8const HWCAP_RISCV_EXT_C: libc::c_ulong = 1 << (b'c' - b'a');9const HWCAP_RISCV_EXT_D: libc::c_ulong = 1 << (b'd' - b'a');10const HWCAP_RISCV_EXT_F: libc::c_ulong = 1 << (b'f' - b'a');11const HWCAP_RISCV_EXT_M: libc::c_ulong = 1 << (b'm' - b'a');12const HWCAP_RISCV_EXT_V: libc::c_ulong = 1 << (b'v' - b'a');1314if (v & HWCAP_RISCV_EXT_A) != 0 {15isa_builder.enable("has_a").unwrap();16}1718if (v & HWCAP_RISCV_EXT_C) != 0 {19isa_builder.enable("has_c").unwrap();20}2122if (v & HWCAP_RISCV_EXT_D) != 0 {23isa_builder.enable("has_d").unwrap();24}2526if (v & HWCAP_RISCV_EXT_F) != 0 {27isa_builder.enable("has_f").unwrap();2829// TODO: There doesn't seem to be a bit associated with this extension30// rust enables it with the `f` extension:31// https://github.com/rust-lang/stdarch/blob/790411f93c4b5eada3c23abb4c9a063fb0b24d99/crates/std_detect/src/detect/os/linux/riscv.rs#L4332isa_builder.enable("has_zicsr").unwrap();33}3435if (v & HWCAP_RISCV_EXT_M) != 0 {36isa_builder.enable("has_m").unwrap();37}3839if (v & HWCAP_RISCV_EXT_V) != 0 {40isa_builder.enable("has_v").unwrap();41}4243// In general extensions that are longer than one letter44// won't have a bit associated with them. The Linux kernel45// is currently working on a new way to query the extensions.46Ok(())47}4849/// Read the /proc/cpuinfo file and detect the extensions.50///51/// We are looking for the isa line string, which contains the extensions.52/// The format for this string is specified in the linux user space ABI for RISC-V:53/// https://github.com/torvalds/linux/blob/09a9639e56c01c7a00d6c0ca63f4c7c41abe075d/Documentation/riscv/uabi.rst54///55/// The format is fairly similar to the one specified in the RISC-V ISA manual, but56/// all lower case.57///58/// An example ISA string is: rv64imafdcvh_zawrs_zba_zbb_zicbom_zicboz_zicsr_zifencei_zihintpause59pub fn cpuinfo_detect(isa_builder: &mut dyn Configurable) -> Result<(), &'static str> {60let file = File::open("/proc/cpuinfo").map_err(|_| "failed to open /proc/cpuinfo")?;6162let isa_string = BufReader::new(file)63.lines()64.filter_map(Result::ok)65.find_map(|line| {66if let Some((k, v)) = line.split_once(':') {67if k.trim_end() == "isa" {68return Some(v.trim().to_string());69}70}71None72})73.ok_or("failed to find isa line in /proc/cpuinfo")?;7475for ext in isa_string_extensions(&isa_string) {76// Try enabling all the extensions that are parsed.77// Cranelift won't recognize all of them, but that's okay we just ignore them.78// Extensions flags in the RISC-V backend have the format of `has_x` for the `x` extension.79let _ = isa_builder.enable(&format!("has_{ext}"));80}8182Ok(())83}8485/// Parses an ISA string and returns an iterator over the extensions.86fn isa_string_extensions(isa: &str) -> Vec<&str> {87let mut parts = isa.split('_');88let mut extensions = Vec::new();89// The first entry has the form `rv64imafdcvh`, we need to skip the architecture ("rv64").90// Each of the letters after the cpu architecture is an extension, so return them91// individually.92if let Some(letters) = parts.next().unwrap().strip_prefix("rv64") {93extensions.extend(letters.matches(|_| true));94extensions.extend(parts);95}96extensions97}9899#[cfg(test)]100mod tests {101use super::*;102103#[test]104fn parse_isa() {105let isa_string = "rv64imafdcvh_zawrs_zba_zbb_zicbom_zicboz_zicsr_zifencei_zihintpause";106let extensions = vec![107"i",108"m",109"a",110"f",111"d",112"c",113"v",114"h",115"zawrs",116"zba",117"zbb",118"zicbom",119"zicboz",120"zicsr",121"zifencei",122"zihintpause",123];124125assert_eq!(isa_string_extensions(isa_string), extensions,);126}127}128129130