Path: blob/main/crates/jit-icache-coherence/Cargo.toml
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[package]1name = "wasmtime-internal-jit-icache-coherence"2version.workspace = true3authors.workspace = true4description = "INTERNAL: Utilities for JIT icache maintenance"5documentation = "https://docs.rs/jit-icache-coherence"6license = "Apache-2.0 WITH LLVM-exception"7repository = "https://github.com/bytecodealliance/wasmtime"8edition.workspace = true9rust-version.workspace = true1011[lints]12workspace = true1314[dependencies]15cfg-if = { workspace = true }16anyhow = { workspace = true }1718[target.'cfg(target_os = "windows")'.dependencies.windows-sys]19workspace = true20features = [21"Win32_Foundation",22"Win32_System_Threading",23"Win32_System_Diagnostics_Debug",24]2526[target.'cfg(any(target_os = "linux", target_vendor = "apple", target_os = "freebsd", target_os = "android"))'.dependencies]27libc = { workspace = true }2829[features]30# Most modern CPUs are SMP (multicore). However, when only one core is present,31# some aspects of coherence are much cheaper. For example, RISC-V can use32# one instruction `fence.i` rather than a syscall that invokes all other cores.33# This feature enables such optimizations, but the resulting program will *only*34# be safe to run on one-core systems.35one-core = []363738