# Created by: Ying-Chieh Liao <[email protected]> PORTNAME= iverilog PORTVERSION= 11.0 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/ DISTNAME= verilog-${PORTVERSION} MAINTAINER= [email protected] COMMENT= Verilog simulation and synthesis tool LICENSE= GPLv2 GNU_CONFIGURE= yes CONFIGURE_ARGS= --disable-suffix USES= bison compiler:c++11-lang gmake readline .include <bsd.port.mk>
