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freebsd
GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/arm-optimized-routines/math/aarch64/advsimd/cos.c
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/*
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* Double-precision vector cos function.
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*
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* Copyright (c) 2019-2024, Arm Limited.
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* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
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*/
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#include "mathlib.h"
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#include "v_math.h"
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#include "test_defs.h"
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#include "test_sig.h"
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static const struct data
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{
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float64x2_t poly[7];
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float64x2_t range_val, inv_pi, pi_1, pi_2, pi_3;
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} data = {
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/* Worst-case error is 3.3 ulp in [-pi/2, pi/2]. */
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.poly = { V2 (-0x1.555555555547bp-3), V2 (0x1.1111111108a4dp-7),
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V2 (-0x1.a01a019936f27p-13), V2 (0x1.71de37a97d93ep-19),
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V2 (-0x1.ae633919987c6p-26), V2 (0x1.60e277ae07cecp-33),
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V2 (-0x1.9e9540300a1p-41) },
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.inv_pi = V2 (0x1.45f306dc9c883p-2),
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.pi_1 = V2 (0x1.921fb54442d18p+1),
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.pi_2 = V2 (0x1.1a62633145c06p-53),
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.pi_3 = V2 (0x1.c1cd129024e09p-106),
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.range_val = V2 (0x1p23)
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};
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#define C(i) d->poly[i]
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static float64x2_t VPCS_ATTR NOINLINE
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special_case (float64x2_t x, float64x2_t y, uint64x2_t odd, uint64x2_t cmp)
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{
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y = vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd));
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return v_call_f64 (cos, x, y, cmp);
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}
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float64x2_t VPCS_ATTR V_NAME_D1 (cos) (float64x2_t x)
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{
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const struct data *d = ptr_barrier (&data);
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float64x2_t n, r, r2, r3, r4, t1, t2, t3, y;
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uint64x2_t odd, cmp;
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#if WANT_SIMD_EXCEPT
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r = vabsq_f64 (x);
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cmp = vcgeq_u64 (vreinterpretq_u64_f64 (r),
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vreinterpretq_u64_f64 (d->range_val));
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if (unlikely (v_any_u64 (cmp)))
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/* If fenv exceptions are to be triggered correctly, set any special lanes
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to 1 (which is neutral w.r.t. fenv). These lanes will be fixed by
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special-case handler later. */
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r = vbslq_f64 (cmp, v_f64 (1.0), r);
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#else
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cmp = vcageq_f64 (x, d->range_val);
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r = x;
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#endif
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/* n = rint((|x|+pi/2)/pi) - 0.5. */
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n = vrndaq_f64 (vfmaq_f64 (v_f64 (0.5), r, d->inv_pi));
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odd = vshlq_n_u64 (vreinterpretq_u64_s64 (vcvtq_s64_f64 (n)), 63);
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n = vsubq_f64 (n, v_f64 (0.5f));
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/* r = |x| - n*pi (range reduction into -pi/2 .. pi/2). */
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r = vfmsq_f64 (r, d->pi_1, n);
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r = vfmsq_f64 (r, d->pi_2, n);
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r = vfmsq_f64 (r, d->pi_3, n);
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/* sin(r) poly approx. */
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r2 = vmulq_f64 (r, r);
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r3 = vmulq_f64 (r2, r);
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r4 = vmulq_f64 (r2, r2);
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t1 = vfmaq_f64 (C (4), C (5), r2);
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t2 = vfmaq_f64 (C (2), C (3), r2);
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t3 = vfmaq_f64 (C (0), C (1), r2);
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y = vfmaq_f64 (t1, C (6), r4);
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y = vfmaq_f64 (t2, y, r4);
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y = vfmaq_f64 (t3, y, r4);
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y = vfmaq_f64 (r, y, r3);
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if (unlikely (v_any_u64 (cmp)))
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return special_case (x, y, odd, cmp);
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return vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd));
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}
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TEST_SIG (V, D, 1, cos, -3.1, 3.1)
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TEST_ULP (V_NAME_D1 (cos), 3.0)
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TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (cos), WANT_SIMD_EXCEPT)
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TEST_SYM_INTERVAL (V_NAME_D1 (cos), 0, 0x1p23, 500000)
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TEST_SYM_INTERVAL (V_NAME_D1 (cos), 0x1p23, inf, 10000)
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