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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/contrib/arm-optimized-routines/math/aarch64/advsimd/expf_1u.c
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/*

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 * Single-precision vector e^x function.

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 *

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 * Copyright (c) 2019-2024, Arm Limited.

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 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception

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 */

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#include "v_math.h"

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#include "test_defs.h"

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static const struct data

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{

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  float32x4_t shift, inv_ln2;

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  uint32x4_t exponent_bias;

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  float32x4_t c1, c2, c3, c4;

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  float32x4_t special_bound, scale_thresh;

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  uint32x4_t special_offset, special_bias;

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  float ln2_hi, ln2_lo, c0, nothing;

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} data = {

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  .ln2_hi = 0x1.62e4p-1f,

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  .ln2_lo = 0x1.7f7d1cp-20f,

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  .shift = V4 (0x1.8p23f),

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  .inv_ln2 = V4 (0x1.715476p+0f),

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  .exponent_bias = V4 (0x3f800000),

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  .special_bound = V4 (126.0f),

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  .scale_thresh = V4 (192.0f),

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  .special_offset = V4 (0x83000000),

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  .special_bias = V4 (0x7f000000),

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  /*  maxerr: 0.36565 +0.5 ulp.  */

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  .c0 = 0x1.6a6000p-10f,

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  .c1 = V4 (0x1.12718ep-7f),

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  .c2 = V4 (0x1.555af0p-5f),

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  .c3 = V4 (0x1.555430p-3f),

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  .c4 = V4 (0x1.fffff4p-2f),

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};

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static float32x4_t VPCS_ATTR NOINLINE

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specialcase (float32x4_t p, float32x4_t n, uint32x4_t e, const struct data *d)

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{

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  /* 2^n may overflow, break it up into s1*s2.  */

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  uint32x4_t b = vandq_u32 (vclezq_f32 (n), d->special_offset);

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  float32x4_t s1 = vreinterpretq_f32_u32 (vaddq_u32 (b, d->special_bias));

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  float32x4_t s2 = vreinterpretq_f32_u32 (vsubq_u32 (e, b));

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  uint32x4_t cmp = vcagtq_f32 (n, d->scale_thresh);

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  float32x4_t r1 = vmulq_f32 (s1, s1);

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  float32x4_t r0 = vmulq_f32 (vmulq_f32 (p, s1), s2);

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  return vreinterpretq_f32_u32 ((cmp & vreinterpretq_u32_f32 (r1))

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				| (~cmp & vreinterpretq_u32_f32 (r0)));

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}

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float32x4_t VPCS_ATTR

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_ZGVnN4v_expf_1u (float32x4_t x)

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{

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  const struct data *d = ptr_barrier (&data);

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  float32x4_t ln2_c0 = vld1q_f32 (&d->ln2_hi);

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  /* exp(x) = 2^n * poly(r), with poly(r) in [1/sqrt(2),sqrt(2)]

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     x = ln2*n + r, with r in [-ln2/2, ln2/2].  */

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  float32x4_t z = vmulq_f32 (x, d->inv_ln2);

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  float32x4_t n = vrndaq_f32 (z);

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  float32x4_t r = vfmsq_laneq_f32 (x, n, ln2_c0, 0);

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  r = vfmsq_laneq_f32 (r, n, ln2_c0, 1);

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  uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_s32 (vcvtaq_s32_f32 (z)), 23);

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  float32x4_t scale = vreinterpretq_f32_u32 (e + d->exponent_bias);

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  uint32x4_t cmp = vcagtq_f32 (n, d->special_bound);

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  float32x4_t p = vfmaq_laneq_f32 (d->c1, r, ln2_c0, 2);

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  p = vfmaq_f32 (d->c2, p, r);

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  p = vfmaq_f32 (d->c3, p, r);

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  p = vfmaq_f32 (d->c4, p, r);

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  p = vfmaq_f32 (v_f32 (1.0f), p, r);

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  p = vfmaq_f32 (v_f32 (1.0f), p, r);

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  if (unlikely (v_any_u32 (cmp)))

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    return specialcase (p, n, e, d);

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  return scale * p;

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}

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TEST_ULP (_ZGVnN4v_expf_1u, 0.4)

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TEST_DISABLE_FENV (_ZGVnN4v_expf_1u)

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TEST_INTERVAL (_ZGVnN4v_expf_1u, 0, 0xffff0000, 10000)

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TEST_SYM_INTERVAL (_ZGVnN4v_expf_1u, 0x1p-14, 0x1p8, 500000)

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