Path: blob/main/contrib/arm-optimized-routines/math/aarch64/advsimd/hypotf.c
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/*1* Single-precision vector hypot(x) function.2*3* Copyright (c) 2023-2024, Arm Limited.4* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception5*/67#include "v_math.h"8#include "test_sig.h"9#include "test_defs.h"1011#if WANT_SIMD_EXCEPT12static const struct data13{14uint32x4_t tiny_bound, thres;15} data = {16.tiny_bound = V4 (0x20000000), /* asuint (0x1p-63). */17.thres = V4 (0x3f000000), /* asuint (0x1p63) - tiny_bound. */18};19#else20static const struct data21{22uint32x4_t tiny_bound;23uint16x8_t thres;24} data = {25.tiny_bound = V4 (0x0C800000), /* asuint (0x1p-102). */26.thres = V8 (0x7300), /* asuint (inf) - tiny_bound. */27};28#endif2930static float32x4_t VPCS_ATTR NOINLINE31special_case (float32x4_t x, float32x4_t y, float32x4_t sqsum,32uint16x4_t special)33{34return v_call2_f32 (hypotf, x, y, vsqrtq_f32 (sqsum), vmovl_u16 (special));35}3637/* Vector implementation of single-precision hypot.38Maximum error observed is 1.21 ULP:39_ZGVnN4vv_hypotf (0x1.6a419cp-13, 0x1.82a852p-22) got 0x1.6a41d2p-1340want 0x1.6a41dp-13. */41#if WANT_SIMD_EXCEPT4243float32x4_t VPCS_ATTR NOINLINE V_NAME_F2 (hypot) (float32x4_t x, float32x4_t y)44{45const struct data *d = ptr_barrier (&data);4647float32x4_t ax = vabsq_f32 (x);48float32x4_t ay = vabsq_f32 (y);4950uint32x4_t ix = vreinterpretq_u32_f32 (ax);51uint32x4_t iy = vreinterpretq_u32_f32 (ay);5253/* Extreme values, NaNs, and infinities should be handled by the scalar54fallback for correct flag handling. */55uint32x4_t specialx = vcgeq_u32 (vsubq_u32 (ix, d->tiny_bound), d->thres);56uint32x4_t specialy = vcgeq_u32 (vsubq_u32 (iy, d->tiny_bound), d->thres);57ax = v_zerofy_f32 (ax, specialx);58ay = v_zerofy_f32 (ay, specialy);59uint16x4_t special = vaddhn_u32 (specialx, specialy);6061float32x4_t sqsum = vfmaq_f32 (vmulq_f32 (ax, ax), ay, ay);6263if (unlikely (v_any_u16h (special)))64return special_case (x, y, sqsum, special);6566return vsqrtq_f32 (sqsum);67}68#else6970float32x4_t VPCS_ATTR NOINLINE V_NAME_F2 (hypot) (float32x4_t x, float32x4_t y)71{72const struct data *d = ptr_barrier (&data);7374float32x4_t sqsum = vfmaq_f32 (vmulq_f32 (x, x), y, y);7576uint16x4_t special77= vcge_u16 (vsubhn_u32 (vreinterpretq_u32_f32 (sqsum), d->tiny_bound),78vget_low_u16 (d->thres));7980if (unlikely (v_any_u16h (special)))81return special_case (x, y, sqsum, special);8283return vsqrtq_f32 (sqsum);84}85#endif8687HALF_WIDTH_ALIAS_F2 (hypot)8889TEST_SIG (V, F, 2, hypot, -10.0, 10.0)90TEST_ULP (V_NAME_F2 (hypot), 1.21)91TEST_DISABLE_FENV_IF_NOT (V_NAME_F2 (hypot), WANT_SIMD_EXCEPT)92TEST_INTERVAL2 (V_NAME_F2 (hypot), 0, inf, 0, inf, 10000)93TEST_INTERVAL2 (V_NAME_F2 (hypot), 0, inf, -0, -inf, 10000)94TEST_INTERVAL2 (V_NAME_F2 (hypot), -0, -inf, 0, inf, 10000)95TEST_INTERVAL2 (V_NAME_F2 (hypot), -0, -inf, -0, -inf, 10000)969798