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freebsd
GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/arm-optimized-routines/math/aarch64/sve/asinh.c
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/*
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* Double-precision SVE asinh(x) function.
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*
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* Copyright (c) 2022-2024, Arm Limited.
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* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
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*/
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#include "sv_math.h"
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#include "test_sig.h"
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#include "test_defs.h"
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#define SignMask (0x8000000000000000)
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#define One (0x3ff0000000000000)
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#define Thres (0x5fe0000000000000) /* asuint64 (0x1p511). */
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#define IndexMask (((1 << V_LOG_TABLE_BITS) - 1) << 1)
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static const struct data
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{
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double even_coeffs[9];
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double ln2, p3, p1, p4, p0, p2, c1, c3, c5, c7, c9, c11, c13, c15, c17;
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uint64_t off, mask;
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} data = {
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/* Polynomial generated using Remez on [2^-26, 1]. */
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.even_coeffs ={
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-0x1.55555555554a7p-3,
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-0x1.6db6db68332e6p-5,
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-0x1.6e8b8b654a621p-6,
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-0x1.c9871d10885afp-7,
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-0x1.3ddca533e9f54p-7,
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-0x1.b90c7099dd397p-8,
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-0x1.d217026a669ecp-9,
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-0x1.e0f37daef9127p-11,
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-0x1.021a48685e287p-14, },
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.c1 = 0x1.3333333326c7p-4,
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.c3 = 0x1.f1c71b26fb40dp-6,
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.c5 = 0x1.1c4daa9e67871p-6,
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.c7 = 0x1.7a16e8d9d2ecfp-7,
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.c9 = 0x1.0becef748dafcp-7,
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.c11 = 0x1.541f2bb1ffe51p-8,
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.c13 = 0x1.0b5c7977aaf7p-9,
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.c15 = 0x1.388b5fe542a6p-12,
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.c17 = 0x1.93d4ba83d34dap-18,
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.ln2 = 0x1.62e42fefa39efp-1,
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.p0 = -0x1.ffffffffffff7p-2,
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.p1 = 0x1.55555555170d4p-2,
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.p2 = -0x1.0000000399c27p-2,
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.p3 = 0x1.999b2e90e94cap-3,
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.p4 = -0x1.554e550bd501ep-3,
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.off = 0x3fe6900900000000,
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.mask = 0xfffULL << 52,
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};
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static svfloat64_t NOINLINE
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special_case (svfloat64_t x, svfloat64_t y, svbool_t special)
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{
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return sv_call_f64 (asinh, x, y, special);
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}
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static inline svfloat64_t
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__sv_log_inline (svfloat64_t x, const struct data *d, const svbool_t pg)
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{
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/* Double-precision SVE log, copied from SVE log implementation with some
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cosmetic modification and special-cases removed. See that file for details
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of the algorithm used. */
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svuint64_t ix = svreinterpret_u64 (x);
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svuint64_t i_off = svsub_x (pg, ix, d->off);
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svuint64_t i
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= svand_x (pg, svlsr_x (pg, i_off, (51 - V_LOG_TABLE_BITS)), IndexMask);
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svuint64_t iz = svsub_x (pg, ix, svand_x (pg, i_off, d->mask));
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svfloat64_t z = svreinterpret_f64 (iz);
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svfloat64_t invc = svld1_gather_index (pg, &__v_log_data.table[0].invc, i);
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svfloat64_t logc = svld1_gather_index (pg, &__v_log_data.table[0].logc, i);
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svfloat64_t ln2_p3 = svld1rq (svptrue_b64 (), &d->ln2);
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svfloat64_t p1_p4 = svld1rq (svptrue_b64 (), &d->p1);
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svfloat64_t r = svmla_x (pg, sv_f64 (-1.0), invc, z);
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svfloat64_t kd
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= svcvt_f64_x (pg, svasr_x (pg, svreinterpret_s64 (i_off), 52));
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svfloat64_t hi = svmla_lane (svadd_x (pg, logc, r), kd, ln2_p3, 0);
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svfloat64_t r2 = svmul_x (svptrue_b64 (), r, r);
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svfloat64_t y = svmla_lane (sv_f64 (d->p2), r, ln2_p3, 1);
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svfloat64_t p = svmla_lane (sv_f64 (d->p0), r, p1_p4, 0);
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y = svmla_lane (y, r2, p1_p4, 1);
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y = svmla_x (pg, p, r2, y);
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y = svmla_x (pg, hi, r2, y);
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return y;
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}
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/* Double-precision implementation of SVE asinh(x).
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asinh is very sensitive around 1, so it is impractical to devise a single
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low-cost algorithm which is sufficiently accurate on a wide range of input.
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Instead we use two different algorithms:
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asinh(x) = sign(x) * log(|x| + sqrt(x^2 + 1) if |x| >= 1
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= sign(x) * (|x| + |x|^3 * P(x^2)) otherwise
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where log(x) is an optimized log approximation, and P(x) is a polynomial
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shared with the scalar routine. The greatest observed error 2.51 ULP, in
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|x| >= 1:
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_ZGVsMxv_asinh(0x1.170469d024505p+0) got 0x1.e3181c43b0f36p-1
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want 0x1.e3181c43b0f39p-1. */
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svfloat64_t SV_NAME_D1 (asinh) (svfloat64_t x, const svbool_t pg)
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{
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const struct data *d = ptr_barrier (&data);
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svuint64_t ix = svreinterpret_u64 (x);
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svuint64_t iax = svbic_x (pg, ix, SignMask);
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svuint64_t sign = svand_x (pg, ix, SignMask);
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svfloat64_t ax = svreinterpret_f64 (iax);
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svbool_t ge1 = svcmpge (pg, iax, One);
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svbool_t special = svcmpge (pg, iax, Thres);
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/* Option 1: |x| >= 1.
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Compute asinh(x) according by asinh(x) = log(x + sqrt(x^2 + 1)). */
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svfloat64_t option_1 = sv_f64 (0);
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if (likely (svptest_any (pg, ge1)))
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{
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svfloat64_t x2 = svmul_x (svptrue_b64 (), ax, ax);
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option_1 = __sv_log_inline (
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svadd_x (pg, ax, svsqrt_x (pg, svadd_x (pg, x2, 1))), d, pg);
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}
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/* Option 2: |x| < 1.
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Compute asinh(x) using a polynomial.
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The largest observed error in this region is 1.51 ULPs:
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_ZGVsMxv_asinh(0x1.fe12bf8c616a2p-1) got 0x1.c1e649ee2681bp-1
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want 0x1.c1e649ee2681dp-1. */
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svfloat64_t option_2 = sv_f64 (0);
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if (likely (svptest_any (pg, svnot_z (pg, ge1))))
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{
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svfloat64_t x2 = svmul_x (svptrue_b64 (), ax, ax);
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svfloat64_t x4 = svmul_x (svptrue_b64 (), x2, x2);
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/* Order-17 Pairwise Horner scheme. */
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svfloat64_t c13 = svld1rq (svptrue_b64 (), &d->c1);
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svfloat64_t c57 = svld1rq (svptrue_b64 (), &d->c5);
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svfloat64_t c911 = svld1rq (svptrue_b64 (), &d->c9);
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svfloat64_t c1315 = svld1rq (svptrue_b64 (), &d->c13);
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svfloat64_t p01 = svmla_lane (sv_f64 (d->even_coeffs[0]), x2, c13, 0);
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svfloat64_t p23 = svmla_lane (sv_f64 (d->even_coeffs[1]), x2, c13, 1);
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svfloat64_t p45 = svmla_lane (sv_f64 (d->even_coeffs[2]), x2, c57, 0);
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svfloat64_t p67 = svmla_lane (sv_f64 (d->even_coeffs[3]), x2, c57, 1);
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svfloat64_t p89 = svmla_lane (sv_f64 (d->even_coeffs[4]), x2, c911, 0);
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svfloat64_t p1011 = svmla_lane (sv_f64 (d->even_coeffs[5]), x2, c911, 1);
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svfloat64_t p1213
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= svmla_lane (sv_f64 (d->even_coeffs[6]), x2, c1315, 0);
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svfloat64_t p1415
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= svmla_lane (sv_f64 (d->even_coeffs[7]), x2, c1315, 1);
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svfloat64_t p1617 = svmla_x (pg, sv_f64 (d->even_coeffs[8]), x2, d->c17);
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svfloat64_t p = svmla_x (pg, p1415, x4, p1617);
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p = svmla_x (pg, p1213, x4, p);
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p = svmla_x (pg, p1011, x4, p);
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p = svmla_x (pg, p89, x4, p);
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p = svmla_x (pg, p67, x4, p);
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p = svmla_x (pg, p45, x4, p);
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p = svmla_x (pg, p23, x4, p);
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p = svmla_x (pg, p01, x4, p);
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option_2 = svmla_x (pg, ax, p, svmul_x (svptrue_b64 (), x2, ax));
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}
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if (unlikely (svptest_any (pg, special)))
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return special_case (
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x,
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svreinterpret_f64 (sveor_x (
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pg, svreinterpret_u64 (svsel (ge1, option_1, option_2)), sign)),
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special);
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/* Choose the right option for each lane. */
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svfloat64_t y = svsel (ge1, option_1, option_2);
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return svreinterpret_f64 (sveor_x (pg, svreinterpret_u64 (y), sign));
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}
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TEST_SIG (SV, D, 1, asinh, -10.0, 10.0)
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TEST_ULP (SV_NAME_D1 (asinh), 2.52)
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TEST_DISABLE_FENV (SV_NAME_D1 (asinh))
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TEST_SYM_INTERVAL (SV_NAME_D1 (asinh), 0, 0x1p-26, 50000)
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TEST_SYM_INTERVAL (SV_NAME_D1 (asinh), 0x1p-26, 1, 50000)
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TEST_SYM_INTERVAL (SV_NAME_D1 (asinh), 1, 0x1p511, 50000)
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TEST_SYM_INTERVAL (SV_NAME_D1 (asinh), 0x1p511, inf, 40000)
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/* Test vector asinh 3 times, with control lane < 1, > 1 and special.
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Ensures the v_sel is choosing the right option in all cases. */
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TEST_CONTROL_VALUE (SV_NAME_D1 (asinh), 0.5)
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TEST_CONTROL_VALUE (SV_NAME_D1 (asinh), 2)
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TEST_CONTROL_VALUE (SV_NAME_D1 (asinh), 0x1p600)
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CLOSE_SVE_ATTR
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