Path: blob/main/contrib/llvm-project/clang/lib/Headers/__clang_cuda_intrinsics.h
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/*===--- __clang_cuda_intrinsics.h - Device-side CUDA intrinsic wrappers ---===1*2* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3* See https://llvm.org/LICENSE.txt for license information.4* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5*6*===-----------------------------------------------------------------------===7*/8#ifndef __CLANG_CUDA_INTRINSICS_H__9#define __CLANG_CUDA_INTRINSICS_H__10#ifndef __CUDA__11#error "This file is for CUDA compilation only."12#endif1314// sm_30 intrinsics: __shfl_{up,down,xor}.1516#define __SM_30_INTRINSICS_H__17#define __SM_30_INTRINSICS_HPP__1819#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 3002021#pragma push_macro("__MAKE_SHUFFLES")22#define __MAKE_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, __Mask, \23__Type) \24inline __device__ int __FnName(int __val, __Type __offset, \25int __width = warpSize) { \26return __IntIntrinsic(__val, __offset, \27((warpSize - __width) << 8) | (__Mask)); \28} \29inline __device__ float __FnName(float __val, __Type __offset, \30int __width = warpSize) { \31return __FloatIntrinsic(__val, __offset, \32((warpSize - __width) << 8) | (__Mask)); \33} \34inline __device__ unsigned int __FnName(unsigned int __val, __Type __offset, \35int __width = warpSize) { \36return static_cast<unsigned int>( \37::__FnName(static_cast<int>(__val), __offset, __width)); \38} \39inline __device__ long long __FnName(long long __val, __Type __offset, \40int __width = warpSize) { \41struct __Bits { \42int __a, __b; \43}; \44_Static_assert(sizeof(__val) == sizeof(__Bits)); \45_Static_assert(sizeof(__Bits) == 2 * sizeof(int)); \46__Bits __tmp; \47memcpy(&__tmp, &__val, sizeof(__val)); \48__tmp.__a = ::__FnName(__tmp.__a, __offset, __width); \49__tmp.__b = ::__FnName(__tmp.__b, __offset, __width); \50long long __ret; \51memcpy(&__ret, &__tmp, sizeof(__tmp)); \52return __ret; \53} \54inline __device__ long __FnName(long __val, __Type __offset, \55int __width = warpSize) { \56_Static_assert(sizeof(long) == sizeof(long long) || \57sizeof(long) == sizeof(int)); \58if (sizeof(long) == sizeof(long long)) { \59return static_cast<long>( \60::__FnName(static_cast<long long>(__val), __offset, __width)); \61} else if (sizeof(long) == sizeof(int)) { \62return static_cast<long>( \63::__FnName(static_cast<int>(__val), __offset, __width)); \64} \65} \66inline __device__ unsigned long __FnName( \67unsigned long __val, __Type __offset, int __width = warpSize) { \68return static_cast<unsigned long>( \69::__FnName(static_cast<long>(__val), __offset, __width)); \70} \71inline __device__ unsigned long long __FnName( \72unsigned long long __val, __Type __offset, int __width = warpSize) { \73return static_cast<unsigned long long>( \74::__FnName(static_cast<long long>(__val), __offset, __width)); \75} \76inline __device__ double __FnName(double __val, __Type __offset, \77int __width = warpSize) { \78long long __tmp; \79_Static_assert(sizeof(__tmp) == sizeof(__val)); \80memcpy(&__tmp, &__val, sizeof(__val)); \81__tmp = ::__FnName(__tmp, __offset, __width); \82double __ret; \83memcpy(&__ret, &__tmp, sizeof(__ret)); \84return __ret; \85}8687__MAKE_SHUFFLES(__shfl, __nvvm_shfl_idx_i32, __nvvm_shfl_idx_f32, 0x1f, int);88// We use 0 rather than 31 as our mask, because shfl.up applies to lanes >=89// maxLane.90__MAKE_SHUFFLES(__shfl_up, __nvvm_shfl_up_i32, __nvvm_shfl_up_f32, 0,91unsigned int);92__MAKE_SHUFFLES(__shfl_down, __nvvm_shfl_down_i32, __nvvm_shfl_down_f32, 0x1f,93unsigned int);94__MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f,95int);96#pragma pop_macro("__MAKE_SHUFFLES")9798#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 30099100#if CUDA_VERSION >= 9000101#if (!defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 300)102// __shfl_sync_* variants available in CUDA-9103#pragma push_macro("__MAKE_SYNC_SHUFFLES")104#define __MAKE_SYNC_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, \105__Mask, __Type) \106inline __device__ int __FnName(unsigned int __mask, int __val, \107__Type __offset, int __width = warpSize) { \108return __IntIntrinsic(__mask, __val, __offset, \109((warpSize - __width) << 8) | (__Mask)); \110} \111inline __device__ float __FnName(unsigned int __mask, float __val, \112__Type __offset, int __width = warpSize) { \113return __FloatIntrinsic(__mask, __val, __offset, \114((warpSize - __width) << 8) | (__Mask)); \115} \116inline __device__ unsigned int __FnName(unsigned int __mask, \117unsigned int __val, __Type __offset, \118int __width = warpSize) { \119return static_cast<unsigned int>( \120::__FnName(__mask, static_cast<int>(__val), __offset, __width)); \121} \122inline __device__ long long __FnName(unsigned int __mask, long long __val, \123__Type __offset, \124int __width = warpSize) { \125struct __Bits { \126int __a, __b; \127}; \128_Static_assert(sizeof(__val) == sizeof(__Bits)); \129_Static_assert(sizeof(__Bits) == 2 * sizeof(int)); \130__Bits __tmp; \131memcpy(&__tmp, &__val, sizeof(__val)); \132__tmp.__a = ::__FnName(__mask, __tmp.__a, __offset, __width); \133__tmp.__b = ::__FnName(__mask, __tmp.__b, __offset, __width); \134long long __ret; \135memcpy(&__ret, &__tmp, sizeof(__tmp)); \136return __ret; \137} \138inline __device__ unsigned long long __FnName( \139unsigned int __mask, unsigned long long __val, __Type __offset, \140int __width = warpSize) { \141return static_cast<unsigned long long>( \142::__FnName(__mask, static_cast<long long>(__val), __offset, __width)); \143} \144inline __device__ long __FnName(unsigned int __mask, long __val, \145__Type __offset, int __width = warpSize) { \146_Static_assert(sizeof(long) == sizeof(long long) || \147sizeof(long) == sizeof(int)); \148if (sizeof(long) == sizeof(long long)) { \149return static_cast<long>(::__FnName( \150__mask, static_cast<long long>(__val), __offset, __width)); \151} else if (sizeof(long) == sizeof(int)) { \152return static_cast<long>( \153::__FnName(__mask, static_cast<int>(__val), __offset, __width)); \154} \155} \156inline __device__ unsigned long __FnName( \157unsigned int __mask, unsigned long __val, __Type __offset, \158int __width = warpSize) { \159return static_cast<unsigned long>( \160::__FnName(__mask, static_cast<long>(__val), __offset, __width)); \161} \162inline __device__ double __FnName(unsigned int __mask, double __val, \163__Type __offset, int __width = warpSize) { \164long long __tmp; \165_Static_assert(sizeof(__tmp) == sizeof(__val)); \166memcpy(&__tmp, &__val, sizeof(__val)); \167__tmp = ::__FnName(__mask, __tmp, __offset, __width); \168double __ret; \169memcpy(&__ret, &__tmp, sizeof(__ret)); \170return __ret; \171}172__MAKE_SYNC_SHUFFLES(__shfl_sync, __nvvm_shfl_sync_idx_i32,173__nvvm_shfl_sync_idx_f32, 0x1f, int);174// We use 0 rather than 31 as our mask, because shfl.up applies to lanes >=175// maxLane.176__MAKE_SYNC_SHUFFLES(__shfl_up_sync, __nvvm_shfl_sync_up_i32,177__nvvm_shfl_sync_up_f32, 0, unsigned int);178__MAKE_SYNC_SHUFFLES(__shfl_down_sync, __nvvm_shfl_sync_down_i32,179__nvvm_shfl_sync_down_f32, 0x1f, unsigned int);180__MAKE_SYNC_SHUFFLES(__shfl_xor_sync, __nvvm_shfl_sync_bfly_i32,181__nvvm_shfl_sync_bfly_f32, 0x1f, int);182#pragma pop_macro("__MAKE_SYNC_SHUFFLES")183184inline __device__ void __syncwarp(unsigned int mask = 0xffffffff) {185return __nvvm_bar_warp_sync(mask);186}187188inline __device__ void __barrier_sync(unsigned int id) {189__nvvm_barrier_sync(id);190}191192inline __device__ void __barrier_sync_count(unsigned int id,193unsigned int count) {194__nvvm_barrier_sync_cnt(id, count);195}196197inline __device__ int __all_sync(unsigned int mask, int pred) {198return __nvvm_vote_all_sync(mask, pred);199}200201inline __device__ int __any_sync(unsigned int mask, int pred) {202return __nvvm_vote_any_sync(mask, pred);203}204205inline __device__ int __uni_sync(unsigned int mask, int pred) {206return __nvvm_vote_uni_sync(mask, pred);207}208209inline __device__ unsigned int __ballot_sync(unsigned int mask, int pred) {210return __nvvm_vote_ballot_sync(mask, pred);211}212213inline __device__ unsigned int __activemask() {214#if CUDA_VERSION < 9020215return __nvvm_vote_ballot(1);216#else217return __nvvm_activemask();218#endif219}220221inline __device__ unsigned int __fns(unsigned mask, unsigned base, int offset) {222return __nvvm_fns(mask, base, offset);223}224225#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 300226227// Define __match* builtins CUDA-9 headers expect to see.228#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 700229inline __device__ unsigned int __match32_any_sync(unsigned int mask,230unsigned int value) {231return __nvvm_match_any_sync_i32(mask, value);232}233234inline __device__ unsigned int235__match64_any_sync(unsigned int mask, unsigned long long value) {236return __nvvm_match_any_sync_i64(mask, value);237}238239inline __device__ unsigned int240__match32_all_sync(unsigned int mask, unsigned int value, int *pred) {241return __nvvm_match_all_sync_i32p(mask, value, pred);242}243244inline __device__ unsigned int245__match64_all_sync(unsigned int mask, unsigned long long value, int *pred) {246return __nvvm_match_all_sync_i64p(mask, value, pred);247}248#include "crt/sm_70_rt.hpp"249250#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 700251#endif // __CUDA_VERSION >= 9000252253// sm_32 intrinsics: __ldg and __funnelshift_{l,lc,r,rc}.254255// Prevent the vanilla sm_32 intrinsics header from being included.256#define __SM_32_INTRINSICS_H__257#define __SM_32_INTRINSICS_HPP__258259#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 320260261inline __device__ char __ldg(const char *ptr) { return __nvvm_ldg_c(ptr); }262inline __device__ short __ldg(const short *ptr) { return __nvvm_ldg_s(ptr); }263inline __device__ int __ldg(const int *ptr) { return __nvvm_ldg_i(ptr); }264inline __device__ long __ldg(const long *ptr) { return __nvvm_ldg_l(ptr); }265inline __device__ long long __ldg(const long long *ptr) {266return __nvvm_ldg_ll(ptr);267}268inline __device__ unsigned char __ldg(const unsigned char *ptr) {269return __nvvm_ldg_uc(ptr);270}271inline __device__ signed char __ldg(const signed char *ptr) {272return __nvvm_ldg_uc((const unsigned char *)ptr);273}274inline __device__ unsigned short __ldg(const unsigned short *ptr) {275return __nvvm_ldg_us(ptr);276}277inline __device__ unsigned int __ldg(const unsigned int *ptr) {278return __nvvm_ldg_ui(ptr);279}280inline __device__ unsigned long __ldg(const unsigned long *ptr) {281return __nvvm_ldg_ul(ptr);282}283inline __device__ unsigned long long __ldg(const unsigned long long *ptr) {284return __nvvm_ldg_ull(ptr);285}286inline __device__ float __ldg(const float *ptr) { return __nvvm_ldg_f(ptr); }287inline __device__ double __ldg(const double *ptr) { return __nvvm_ldg_d(ptr); }288289inline __device__ char2 __ldg(const char2 *ptr) {290typedef char c2 __attribute__((ext_vector_type(2)));291// We can assume that ptr is aligned at least to char2's alignment, but the292// load will assume that ptr is aligned to char2's alignment. This is only293// safe if alignof(c2) <= alignof(char2).294c2 rv = __nvvm_ldg_c2(reinterpret_cast<const c2 *>(ptr));295char2 ret;296ret.x = rv[0];297ret.y = rv[1];298return ret;299}300inline __device__ char4 __ldg(const char4 *ptr) {301typedef char c4 __attribute__((ext_vector_type(4)));302c4 rv = __nvvm_ldg_c4(reinterpret_cast<const c4 *>(ptr));303char4 ret;304ret.x = rv[0];305ret.y = rv[1];306ret.z = rv[2];307ret.w = rv[3];308return ret;309}310inline __device__ short2 __ldg(const short2 *ptr) {311typedef short s2 __attribute__((ext_vector_type(2)));312s2 rv = __nvvm_ldg_s2(reinterpret_cast<const s2 *>(ptr));313short2 ret;314ret.x = rv[0];315ret.y = rv[1];316return ret;317}318inline __device__ short4 __ldg(const short4 *ptr) {319typedef short s4 __attribute__((ext_vector_type(4)));320s4 rv = __nvvm_ldg_s4(reinterpret_cast<const s4 *>(ptr));321short4 ret;322ret.x = rv[0];323ret.y = rv[1];324ret.z = rv[2];325ret.w = rv[3];326return ret;327}328inline __device__ int2 __ldg(const int2 *ptr) {329typedef int i2 __attribute__((ext_vector_type(2)));330i2 rv = __nvvm_ldg_i2(reinterpret_cast<const i2 *>(ptr));331int2 ret;332ret.x = rv[0];333ret.y = rv[1];334return ret;335}336inline __device__ int4 __ldg(const int4 *ptr) {337typedef int i4 __attribute__((ext_vector_type(4)));338i4 rv = __nvvm_ldg_i4(reinterpret_cast<const i4 *>(ptr));339int4 ret;340ret.x = rv[0];341ret.y = rv[1];342ret.z = rv[2];343ret.w = rv[3];344return ret;345}346inline __device__ longlong2 __ldg(const longlong2 *ptr) {347typedef long long ll2 __attribute__((ext_vector_type(2)));348ll2 rv = __nvvm_ldg_ll2(reinterpret_cast<const ll2 *>(ptr));349longlong2 ret;350ret.x = rv[0];351ret.y = rv[1];352return ret;353}354355inline __device__ uchar2 __ldg(const uchar2 *ptr) {356typedef unsigned char uc2 __attribute__((ext_vector_type(2)));357uc2 rv = __nvvm_ldg_uc2(reinterpret_cast<const uc2 *>(ptr));358uchar2 ret;359ret.x = rv[0];360ret.y = rv[1];361return ret;362}363inline __device__ uchar4 __ldg(const uchar4 *ptr) {364typedef unsigned char uc4 __attribute__((ext_vector_type(4)));365uc4 rv = __nvvm_ldg_uc4(reinterpret_cast<const uc4 *>(ptr));366uchar4 ret;367ret.x = rv[0];368ret.y = rv[1];369ret.z = rv[2];370ret.w = rv[3];371return ret;372}373inline __device__ ushort2 __ldg(const ushort2 *ptr) {374typedef unsigned short us2 __attribute__((ext_vector_type(2)));375us2 rv = __nvvm_ldg_us2(reinterpret_cast<const us2 *>(ptr));376ushort2 ret;377ret.x = rv[0];378ret.y = rv[1];379return ret;380}381inline __device__ ushort4 __ldg(const ushort4 *ptr) {382typedef unsigned short us4 __attribute__((ext_vector_type(4)));383us4 rv = __nvvm_ldg_us4(reinterpret_cast<const us4 *>(ptr));384ushort4 ret;385ret.x = rv[0];386ret.y = rv[1];387ret.z = rv[2];388ret.w = rv[3];389return ret;390}391inline __device__ uint2 __ldg(const uint2 *ptr) {392typedef unsigned int ui2 __attribute__((ext_vector_type(2)));393ui2 rv = __nvvm_ldg_ui2(reinterpret_cast<const ui2 *>(ptr));394uint2 ret;395ret.x = rv[0];396ret.y = rv[1];397return ret;398}399inline __device__ uint4 __ldg(const uint4 *ptr) {400typedef unsigned int ui4 __attribute__((ext_vector_type(4)));401ui4 rv = __nvvm_ldg_ui4(reinterpret_cast<const ui4 *>(ptr));402uint4 ret;403ret.x = rv[0];404ret.y = rv[1];405ret.z = rv[2];406ret.w = rv[3];407return ret;408}409inline __device__ ulonglong2 __ldg(const ulonglong2 *ptr) {410typedef unsigned long long ull2 __attribute__((ext_vector_type(2)));411ull2 rv = __nvvm_ldg_ull2(reinterpret_cast<const ull2 *>(ptr));412ulonglong2 ret;413ret.x = rv[0];414ret.y = rv[1];415return ret;416}417418inline __device__ float2 __ldg(const float2 *ptr) {419typedef float f2 __attribute__((ext_vector_type(2)));420f2 rv = __nvvm_ldg_f2(reinterpret_cast<const f2 *>(ptr));421float2 ret;422ret.x = rv[0];423ret.y = rv[1];424return ret;425}426inline __device__ float4 __ldg(const float4 *ptr) {427typedef float f4 __attribute__((ext_vector_type(4)));428f4 rv = __nvvm_ldg_f4(reinterpret_cast<const f4 *>(ptr));429float4 ret;430ret.x = rv[0];431ret.y = rv[1];432ret.z = rv[2];433ret.w = rv[3];434return ret;435}436inline __device__ double2 __ldg(const double2 *ptr) {437typedef double d2 __attribute__((ext_vector_type(2)));438d2 rv = __nvvm_ldg_d2(reinterpret_cast<const d2 *>(ptr));439double2 ret;440ret.x = rv[0];441ret.y = rv[1];442return ret;443}444445// TODO: Implement these as intrinsics, so the backend can work its magic on446// these. Alternatively, we could implement these as plain C and try to get447// llvm to recognize the relevant patterns.448inline __device__ unsigned __funnelshift_l(unsigned low32, unsigned high32,449unsigned shiftWidth) {450unsigned result;451asm("shf.l.wrap.b32 %0, %1, %2, %3;"452: "=r"(result)453: "r"(low32), "r"(high32), "r"(shiftWidth));454return result;455}456inline __device__ unsigned __funnelshift_lc(unsigned low32, unsigned high32,457unsigned shiftWidth) {458unsigned result;459asm("shf.l.clamp.b32 %0, %1, %2, %3;"460: "=r"(result)461: "r"(low32), "r"(high32), "r"(shiftWidth));462return result;463}464inline __device__ unsigned __funnelshift_r(unsigned low32, unsigned high32,465unsigned shiftWidth) {466unsigned result;467asm("shf.r.wrap.b32 %0, %1, %2, %3;"468: "=r"(result)469: "r"(low32), "r"(high32), "r"(shiftWidth));470return result;471}472inline __device__ unsigned __funnelshift_rc(unsigned low32, unsigned high32,473unsigned shiftWidth) {474unsigned ret;475asm("shf.r.clamp.b32 %0, %1, %2, %3;"476: "=r"(ret)477: "r"(low32), "r"(high32), "r"(shiftWidth));478return ret;479}480481#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 320482483#if CUDA_VERSION >= 11000484extern "C" {485__device__ inline size_t __nv_cvta_generic_to_global_impl(const void *__ptr) {486return (size_t)(void __attribute__((address_space(1))) *)__ptr;487}488__device__ inline size_t __nv_cvta_generic_to_shared_impl(const void *__ptr) {489return (size_t)(void __attribute__((address_space(3))) *)__ptr;490}491__device__ inline size_t __nv_cvta_generic_to_constant_impl(const void *__ptr) {492return (size_t)(void __attribute__((address_space(4))) *)__ptr;493}494__device__ inline size_t __nv_cvta_generic_to_local_impl(const void *__ptr) {495return (size_t)(void __attribute__((address_space(5))) *)__ptr;496}497__device__ inline void *__nv_cvta_global_to_generic_impl(size_t __ptr) {498return (void *)(void __attribute__((address_space(1))) *)__ptr;499}500__device__ inline void *__nv_cvta_shared_to_generic_impl(size_t __ptr) {501return (void *)(void __attribute__((address_space(3))) *)__ptr;502}503__device__ inline void *__nv_cvta_constant_to_generic_impl(size_t __ptr) {504return (void *)(void __attribute__((address_space(4))) *)__ptr;505}506__device__ inline void *__nv_cvta_local_to_generic_impl(size_t __ptr) {507return (void *)(void __attribute__((address_space(5))) *)__ptr;508}509__device__ inline cuuint32_t __nvvm_get_smem_pointer(void *__ptr) {510return __nv_cvta_generic_to_shared_impl(__ptr);511}512} // extern "C"513514#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 800515__device__ inline unsigned __reduce_add_sync(unsigned __mask,516unsigned __value) {517return __nvvm_redux_sync_add(__mask, __value);518}519__device__ inline unsigned __reduce_min_sync(unsigned __mask,520unsigned __value) {521return __nvvm_redux_sync_umin(__mask, __value);522}523__device__ inline unsigned __reduce_max_sync(unsigned __mask,524unsigned __value) {525return __nvvm_redux_sync_umax(__mask, __value);526}527__device__ inline int __reduce_min_sync(unsigned __mask, int __value) {528return __nvvm_redux_sync_min(__mask, __value);529}530__device__ inline int __reduce_max_sync(unsigned __mask, int __value) {531return __nvvm_redux_sync_max(__mask, __value);532}533__device__ inline unsigned __reduce_or_sync(unsigned __mask, unsigned __value) {534return __nvvm_redux_sync_or(__mask, __value);535}536__device__ inline unsigned __reduce_and_sync(unsigned __mask,537unsigned __value) {538return __nvvm_redux_sync_and(__mask, __value);539}540__device__ inline unsigned __reduce_xor_sync(unsigned __mask,541unsigned __value) {542return __nvvm_redux_sync_xor(__mask, __value);543}544545__device__ inline void __nv_memcpy_async_shared_global_4(void *__dst,546const void *__src,547unsigned __src_size) {548__nvvm_cp_async_ca_shared_global_4(549(void __attribute__((address_space(3))) *)__dst,550(const void __attribute__((address_space(1))) *)__src, __src_size);551}552__device__ inline void __nv_memcpy_async_shared_global_8(void *__dst,553const void *__src,554unsigned __src_size) {555__nvvm_cp_async_ca_shared_global_8(556(void __attribute__((address_space(3))) *)__dst,557(const void __attribute__((address_space(1))) *)__src, __src_size);558}559__device__ inline void __nv_memcpy_async_shared_global_16(void *__dst,560const void *__src,561unsigned __src_size) {562__nvvm_cp_async_ca_shared_global_16(563(void __attribute__((address_space(3))) *)__dst,564(const void __attribute__((address_space(1))) *)__src, __src_size);565}566567__device__ inline void *568__nv_associate_access_property(const void *__ptr, unsigned long long __prop) {569// TODO: it appears to provide compiler with some sort of a hint. We do not570// know what exactly it is supposed to do. However, CUDA headers suggest that571// just passing through __ptr should not affect correctness. They do so on572// pre-sm80 GPUs where this builtin is not available.573return (void*)__ptr;574}575#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 800576577#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 900578__device__ inline unsigned __isCtaShared(const void *ptr) {579return __isShared(ptr);580}581582__device__ inline unsigned __isClusterShared(const void *__ptr) {583return __nvvm_isspacep_shared_cluster(__ptr);584}585586__device__ inline void *__cluster_map_shared_rank(const void *__ptr,587unsigned __rank) {588return __nvvm_mapa((void *)__ptr, __rank);589}590591__device__ inline unsigned __cluster_query_shared_rank(const void *__ptr) {592return __nvvm_getctarank((void *)__ptr);593}594595__device__ inline uint2596__cluster_map_shared_multicast(const void *__ptr,597unsigned int __cluster_cta_mask) {598return make_uint2((unsigned)__cvta_generic_to_shared(__ptr),599__cluster_cta_mask);600}601602__device__ inline unsigned __clusterDimIsSpecified() {603return __nvvm_is_explicit_cluster();604}605606__device__ inline dim3 __clusterDim() {607return dim3(__nvvm_read_ptx_sreg_cluster_nctaid_x(),608__nvvm_read_ptx_sreg_cluster_nctaid_y(),609__nvvm_read_ptx_sreg_cluster_nctaid_z());610}611612__device__ inline dim3 __clusterRelativeBlockIdx() {613return dim3(__nvvm_read_ptx_sreg_cluster_ctaid_x(),614__nvvm_read_ptx_sreg_cluster_ctaid_y(),615__nvvm_read_ptx_sreg_cluster_ctaid_z());616}617618__device__ inline dim3 __clusterGridDimInClusters() {619return dim3(__nvvm_read_ptx_sreg_nclusterid_x(),620__nvvm_read_ptx_sreg_nclusterid_y(),621__nvvm_read_ptx_sreg_nclusterid_z());622}623624__device__ inline dim3 __clusterIdx() {625return dim3(__nvvm_read_ptx_sreg_clusterid_x(),626__nvvm_read_ptx_sreg_clusterid_y(),627__nvvm_read_ptx_sreg_clusterid_z());628}629630__device__ inline unsigned __clusterRelativeBlockRank() {631return __nvvm_read_ptx_sreg_cluster_ctarank();632}633634__device__ inline unsigned __clusterSizeInBlocks() {635return __nvvm_read_ptx_sreg_cluster_nctarank();636}637638__device__ inline void __cluster_barrier_arrive() {639__nvvm_barrier_cluster_arrive();640}641642__device__ inline void __cluster_barrier_arrive_relaxed() {643__nvvm_barrier_cluster_arrive_relaxed();644}645646__device__ inline void __cluster_barrier_wait() {647__nvvm_barrier_cluster_wait();648}649650__device__ inline void __threadfence_cluster() { __nvvm_fence_sc_cluster(); }651652__device__ inline float2 atomicAdd(float2 *__ptr, float2 __val) {653float2 __ret;654__asm__("atom.add.v2.f32 {%0, %1}, [%2], {%3, %4};"655: "=f"(__ret.x), "=f"(__ret.y)656: "l"(__ptr), "f"(__val.x), "f"(__val.y));657return __ret;658}659660__device__ inline float2 atomicAdd_block(float2 *__ptr, float2 __val) {661float2 __ret;662__asm__("atom.cta.add.v2.f32 {%0, %1}, [%2], {%3, %4};"663: "=f"(__ret.x), "=f"(__ret.y)664: "l"(__ptr), "f"(__val.x), "f"(__val.y));665return __ret;666}667668__device__ inline float2 atomicAdd_system(float2 *__ptr, float2 __val) {669float2 __ret;670__asm__("atom.sys.add.v2.f32 {%0, %1}, [%2], {%3, %4};"671: "=f"(__ret.x), "=f"(__ret.y)672: "l"(__ptr), "f"(__val.x), "f"(__val.y));673return __ret;674}675676__device__ inline float4 atomicAdd(float4 *__ptr, float4 __val) {677float4 __ret;678__asm__("atom.add.v4.f32 {%0, %1, %2, %3}, [%4], {%5, %6, %7, %8};"679: "=f"(__ret.x), "=f"(__ret.y), "=f"(__ret.z), "=f"(__ret.w)680: "l"(__ptr), "f"(__val.x), "f"(__val.y), "f"(__val.z), "f"(__val.w));681return __ret;682}683684__device__ inline float4 atomicAdd_block(float4 *__ptr, float4 __val) {685float4 __ret;686__asm__(687"atom.cta.add.v4.f32 {%0, %1, %2, %3}, [%4], {%5, %6, %7, %8};"688: "=f"(__ret.x), "=f"(__ret.y), "=f"(__ret.z), "=f"(__ret.w)689: "l"(__ptr), "f"(__val.x), "f"(__val.y), "f"(__val.z), "f"(__val.w));690return __ret;691}692693__device__ inline float4 atomicAdd_system(float4 *__ptr, float4 __val) {694float4 __ret;695__asm__(696"atom.sys.add.v4.f32 {%0, %1, %2, %3}, [%4], {%5, %6, %7, %8};"697: "=f"(__ret.x), "=f"(__ret.y), "=f"(__ret.z), "=f"(__ret.w)698: "l"(__ptr), "f"(__val.x), "f"(__val.y), "f"(__val.z), "f"(__val.w)699:);700return __ret;701}702703#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 900704#endif // CUDA_VERSION >= 11000705706#endif // defined(__CLANG_CUDA_INTRINSICS_H__)707708709