CoCalc -- arm

GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/llvm-project/clang/lib/Headers/arm_acle.h
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/*===---- arm_acle.h - ARM Non-Neon intrinsics -----------------------------===
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 *
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 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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 * See https://llvm.org/LICENSE.txt for license information.
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 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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 *
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 * The Arm C Language Extensions specifications can be found in the following
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 * link: https://github.com/ARM-software/acle/releases
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 *
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 * The ACLE section numbers are subject to change. When consulting the
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 * specifications, it is recommended to search using section titles if
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 * the section numbers look outdated.
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 *
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 *===-----------------------------------------------------------------------===
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 */
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#ifndef __ARM_ACLE_H
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#define __ARM_ACLE_H
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#ifndef __ARM_ACLE
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#error "ACLE intrinsics support not enabled."
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#endif
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#include <stdint.h>
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* 7 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
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/* 7.3 Memory barriers */
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#if !__has_builtin(__dmb)
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#define __dmb(i) __builtin_arm_dmb(i)
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#endif
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#if !__has_builtin(__dsb)
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#define __dsb(i) __builtin_arm_dsb(i)
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#endif
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#if !__has_builtin(__isb)
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#define __isb(i) __builtin_arm_isb(i)
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#endif
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/* 7.4 Hints */
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#if !__has_builtin(__wfi)
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static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfi(void) {
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  __builtin_arm_wfi();
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}
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#endif
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#if !__has_builtin(__wfe)
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static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfe(void) {
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  __builtin_arm_wfe();
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}
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#endif
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#if !__has_builtin(__sev)
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static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sev(void) {
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  __builtin_arm_sev();
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}
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#endif
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#if !__has_builtin(__sevl)
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static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sevl(void) {
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  __builtin_arm_sevl();
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}
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#endif
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#if !__has_builtin(__yield)
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static __inline__ void __attribute__((__always_inline__, __nodebug__)) __yield(void) {
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  __builtin_arm_yield();
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}
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#endif
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#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
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#define __dbg(t) __builtin_arm_dbg(t)
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#endif
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#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
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#define _CHKFEAT_GCS 1
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static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
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__chkfeat(uint64_t __features) {
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  return __builtin_arm_chkfeat(__features) ^ __features;
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}
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#endif
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/* 7.5 Swap */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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__swp(uint32_t __x, volatile uint32_t *__p) {
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  uint32_t v;
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  do
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    v = __builtin_arm_ldrex(__p);
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  while (__builtin_arm_strex(__x, __p));
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  return v;
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}
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/* 7.6 Memory prefetch intrinsics */
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/* 7.6.1 Data prefetch */
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#define __pld(addr) __pldx(0, 0, 0, addr)
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#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
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#define __pldx(access_kind, cache_level, retention_policy, addr) \
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  __builtin_arm_prefetch(addr, access_kind, 1)
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#else
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#define __pldx(access_kind, cache_level, retention_policy, addr) \
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  __builtin_arm_prefetch(addr, access_kind, cache_level, retention_policy, 1)
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#endif
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/* 7.6.2 Instruction prefetch */
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#define __pli(addr) __plix(0, 0, addr)
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#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
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#define __plix(cache_level, retention_policy, addr) \
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  __builtin_arm_prefetch(addr, 0, 0)
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#else
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#define __plix(cache_level, retention_policy, addr) \
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  __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0)
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#endif
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/* 7.7 NOP */
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#if !defined(_MSC_VER) || (!defined(__aarch64__) && !defined(__arm64ec__))
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static __inline__ void __attribute__((__always_inline__, __nodebug__)) __nop(void) {
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  __builtin_arm_nop();
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}
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#endif
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/* 8 DATA-PROCESSING INTRINSICS */
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/* 8.2 Miscellaneous data-processing intrinsics */
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/* ROR */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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__ror(uint32_t __x, uint32_t __y) {
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  __y %= 32;
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  if (__y == 0)
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    return __x;
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  return (__x >> __y) | (__x << (32 - __y));
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}
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static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
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__rorll(uint64_t __x, uint32_t __y) {
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  __y %= 64;
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  if (__y == 0)
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    return __x;
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  return (__x >> __y) | (__x << (64 - __y));
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}
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static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
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__rorl(unsigned long __x, uint32_t __y) {
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#if __SIZEOF_LONG__ == 4
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  return __ror(__x, __y);
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#else
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  return __rorll(__x, __y);
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#endif
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}
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/* CLZ */
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clz(uint32_t __t) {
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  return __builtin_arm_clz(__t);
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}
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clzl(unsigned long __t) {
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#if __SIZEOF_LONG__ == 4
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  return __builtin_arm_clz(__t);
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#else
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  return __builtin_arm_clz64(__t);
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#endif
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}
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clzll(uint64_t __t) {
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  return __builtin_arm_clz64(__t);
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}
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/* CLS */
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__cls(uint32_t __t) {
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  return __builtin_arm_cls(__t);
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}
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clsl(unsigned long __t) {
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#if __SIZEOF_LONG__ == 4
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  return __builtin_arm_cls(__t);
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#else
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  return __builtin_arm_cls64(__t);
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#endif
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}
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clsll(uint64_t __t) {
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  return __builtin_arm_cls64(__t);
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}
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/* REV */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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__rev(uint32_t __t) {
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  return __builtin_bswap32(__t);
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}
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static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
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__revl(unsigned long __t) {
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#if __SIZEOF_LONG__ == 4
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  return __builtin_bswap32(__t);
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#else
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  return __builtin_bswap64(__t);
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#endif
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}
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static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
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__revll(uint64_t __t) {
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  return __builtin_bswap64(__t);
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}
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/* REV16 */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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__rev16(uint32_t __t) {
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  return __ror(__rev(__t), 16);
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}
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static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
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__rev16ll(uint64_t __t) {
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  return (((uint64_t)__rev16(__t >> 32)) << 32) | (uint64_t)__rev16((uint32_t)__t);
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}
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static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
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__rev16l(unsigned long __t) {
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#if __SIZEOF_LONG__ == 4
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    return __rev16(__t);
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#else
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    return __rev16ll(__t);
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#endif
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}
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/* REVSH */
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static __inline__ int16_t __attribute__((__always_inline__, __nodebug__))
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__revsh(int16_t __t) {
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  return (int16_t)__builtin_bswap16((uint16_t)__t);
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}
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/* RBIT */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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__rbit(uint32_t __t) {
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  return __builtin_arm_rbit(__t);
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}
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static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
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__rbitll(uint64_t __t) {
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#if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE
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  return (((uint64_t)__builtin_arm_rbit(__t)) << 32) |
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         __builtin_arm_rbit(__t >> 32);
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#else
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  return __builtin_arm_rbit64(__t);
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#endif
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}
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static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
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__rbitl(unsigned long __t) {
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#if __SIZEOF_LONG__ == 4
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  return __rbit(__t);
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#else
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  return __rbitll(__t);
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#endif
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}
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/* 8.3 16-bit multiplications */
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#if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP
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static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
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__smulbb(int32_t __a, int32_t __b) {
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  return __builtin_arm_smulbb(__a, __b);
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}
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static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
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__smulbt(int32_t __a, int32_t __b) {
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  return __builtin_arm_smulbt(__a, __b);
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}
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static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
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__smultb(int32_t __a, int32_t __b) {
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  return __builtin_arm_smultb(__a, __b);
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}
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static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
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__smultt(int32_t __a, int32_t __b) {
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  return __builtin_arm_smultt(__a, __b);
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}
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static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
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__smulwb(int32_t __a, int32_t __b) {
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  return __builtin_arm_smulwb(__a, __b);
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}
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static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
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__smulwt(int32_t __a, int32_t __b) {
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  return __builtin_arm_smulwt(__a, __b);
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}
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#endif
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/*
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 * 8.4 Saturating intrinsics
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 *
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 * FIXME: Change guard to their corresponding __ARM_FEATURE flag when Q flag
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 * intrinsics are implemented and the flag is enabled.
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 */
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/* 8.4.1 Width-specified saturation intrinsics */
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#if defined(__ARM_FEATURE_SAT) && __ARM_FEATURE_SAT
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#define __ssat(x, y) __builtin_arm_ssat(x, y)
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#define __usat(x, y) __builtin_arm_usat(x, y)
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#endif
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/* 8.4.2 Saturating addition and subtraction intrinsics */
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#if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__qadd(int32_t __t, int32_t __v) {
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  return __builtin_arm_qadd(__t, __v);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__qsub(int32_t __t, int32_t __v) {
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  return __builtin_arm_qsub(__t, __v);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__qdbl(int32_t __t) {
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  return __builtin_arm_qadd(__t, __t);
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}
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#endif
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/* 8.4.3 Accumulating multiplications */
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#if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__smlabb(int32_t __a, int32_t __b, int32_t __c) {
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  return __builtin_arm_smlabb(__a, __b, __c);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__smlabt(int32_t __a, int32_t __b, int32_t __c) {
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  return __builtin_arm_smlabt(__a, __b, __c);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__smlatb(int32_t __a, int32_t __b, int32_t __c) {
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  return __builtin_arm_smlatb(__a, __b, __c);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__smlatt(int32_t __a, int32_t __b, int32_t __c) {
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  return __builtin_arm_smlatt(__a, __b, __c);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__smlawb(int32_t __a, int32_t __b, int32_t __c) {
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  return __builtin_arm_smlawb(__a, __b, __c);
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}
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static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
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__smlawt(int32_t __a, int32_t __b, int32_t __c) {
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  return __builtin_arm_smlawt(__a, __b, __c);
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}
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#endif
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/* 8.5.4 Parallel 16-bit saturation */
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#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
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#define __ssat16(x, y) __builtin_arm_ssat16(x, y)
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#define __usat16(x, y) __builtin_arm_usat16(x, y)
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#endif
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/* 8.5.5 Packing and unpacking */
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#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
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typedef int32_t int8x4_t;
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typedef int32_t int16x2_t;
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typedef uint32_t uint8x4_t;
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typedef uint32_t uint16x2_t;
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static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
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__sxtab16(int16x2_t __a, int8x4_t __b) {
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  return __builtin_arm_sxtab16(__a, __b);
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}
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static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
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__sxtb16(int8x4_t __a) {
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  return __builtin_arm_sxtb16(__a);
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}
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static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
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__uxtab16(int16x2_t __a, int8x4_t __b) {
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  return __builtin_arm_uxtab16(__a, __b);
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}
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static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
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__uxtb16(int8x4_t __a) {
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  return __builtin_arm_uxtb16(__a);
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}
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#endif
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/* 8.5.6 Parallel selection */
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#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
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static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
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__sel(uint8x4_t __a, uint8x4_t __b) {
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  return __builtin_arm_sel(__a, __b);
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}
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#endif
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/* 8.5.7 Parallel 8-bit addition and subtraction */
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#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
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static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
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__qadd8(int8x4_t __a, int8x4_t __b) {
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  return __builtin_arm_qadd8(__a, __b);
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}
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static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
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__qsub8(int8x4_t __a, int8x4_t __b) {
400
  return __builtin_arm_qsub8(__a, __b);
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}
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static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
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__sadd8(int8x4_t __a, int8x4_t __b) {
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  return __builtin_arm_sadd8(__a, __b);
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}
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static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
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__shadd8(int8x4_t __a, int8x4_t __b) {
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  return __builtin_arm_shadd8(__a, __b);
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}
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static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
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__shsub8(int8x4_t __a, int8x4_t __b) {
412
  return __builtin_arm_shsub8(__a, __b);
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}
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static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
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__ssub8(int8x4_t __a, int8x4_t __b) {
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  return __builtin_arm_ssub8(__a, __b);
417
}
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static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
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__uadd8(uint8x4_t __a, uint8x4_t __b) {
420
  return __builtin_arm_uadd8(__a, __b);
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}
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static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
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__uhadd8(uint8x4_t __a, uint8x4_t __b) {
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  return __builtin_arm_uhadd8(__a, __b);
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}
426
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
427
__uhsub8(uint8x4_t __a, uint8x4_t __b) {
428
  return __builtin_arm_uhsub8(__a, __b);
429
}
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static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
431
__uqadd8(uint8x4_t __a, uint8x4_t __b) {
432
  return __builtin_arm_uqadd8(__a, __b);
433
}
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static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
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__uqsub8(uint8x4_t __a, uint8x4_t __b) {
436
  return __builtin_arm_uqsub8(__a, __b);
437
}
438
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
439
__usub8(uint8x4_t __a, uint8x4_t __b) {
440
  return __builtin_arm_usub8(__a, __b);
441
}
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#endif
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444
/* 8.5.8 Sum of 8-bit absolute differences */
445
#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
446
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
447
__usad8(uint8x4_t __a, uint8x4_t __b) {
448
  return __builtin_arm_usad8(__a, __b);
449
}
450
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
451
__usada8(uint8x4_t __a, uint8x4_t __b, uint32_t __c) {
452
  return __builtin_arm_usada8(__a, __b, __c);
453
}
454
#endif
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/* 8.5.9 Parallel 16-bit addition and subtraction */
457
#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
458
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
459
__qadd16(int16x2_t __a, int16x2_t __b) {
460
  return __builtin_arm_qadd16(__a, __b);
461
}
462
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
463
__qasx(int16x2_t __a, int16x2_t __b) {
464
  return __builtin_arm_qasx(__a, __b);
465
}
466
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
467
__qsax(int16x2_t __a, int16x2_t __b) {
468
  return __builtin_arm_qsax(__a, __b);
469
}
470
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
471
__qsub16(int16x2_t __a, int16x2_t __b) {
472
  return __builtin_arm_qsub16(__a, __b);
473
}
474
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
475
__sadd16(int16x2_t __a, int16x2_t __b) {
476
  return __builtin_arm_sadd16(__a, __b);
477
}
478
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
479
__sasx(int16x2_t __a, int16x2_t __b) {
480
  return __builtin_arm_sasx(__a, __b);
481
}
482
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
483
__shadd16(int16x2_t __a, int16x2_t __b) {
484
  return __builtin_arm_shadd16(__a, __b);
485
}
486
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
487
__shasx(int16x2_t __a, int16x2_t __b) {
488
  return __builtin_arm_shasx(__a, __b);
489
}
490
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
491
__shsax(int16x2_t __a, int16x2_t __b) {
492
  return __builtin_arm_shsax(__a, __b);
493
}
494
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
495
__shsub16(int16x2_t __a, int16x2_t __b) {
496
  return __builtin_arm_shsub16(__a, __b);
497
}
498
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
499
__ssax(int16x2_t __a, int16x2_t __b) {
500
  return __builtin_arm_ssax(__a, __b);
501
}
502
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
503
__ssub16(int16x2_t __a, int16x2_t __b) {
504
  return __builtin_arm_ssub16(__a, __b);
505
}
506
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
507
__uadd16(uint16x2_t __a, uint16x2_t __b) {
508
  return __builtin_arm_uadd16(__a, __b);
509
}
510
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
511
__uasx(uint16x2_t __a, uint16x2_t __b) {
512
  return __builtin_arm_uasx(__a, __b);
513
}
514
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
515
__uhadd16(uint16x2_t __a, uint16x2_t __b) {
516
  return __builtin_arm_uhadd16(__a, __b);
517
}
518
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
519
__uhasx(uint16x2_t __a, uint16x2_t __b) {
520
  return __builtin_arm_uhasx(__a, __b);
521
}
522
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
523
__uhsax(uint16x2_t __a, uint16x2_t __b) {
524
  return __builtin_arm_uhsax(__a, __b);
525
}
526
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
527
__uhsub16(uint16x2_t __a, uint16x2_t __b) {
528
  return __builtin_arm_uhsub16(__a, __b);
529
}
530
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
531
__uqadd16(uint16x2_t __a, uint16x2_t __b) {
532
  return __builtin_arm_uqadd16(__a, __b);
533
}
534
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
535
__uqasx(uint16x2_t __a, uint16x2_t __b) {
536
  return __builtin_arm_uqasx(__a, __b);
537
}
538
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
539
__uqsax(uint16x2_t __a, uint16x2_t __b) {
540
  return __builtin_arm_uqsax(__a, __b);
541
}
542
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
543
__uqsub16(uint16x2_t __a, uint16x2_t __b) {
544
  return __builtin_arm_uqsub16(__a, __b);
545
}
546
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
547
__usax(uint16x2_t __a, uint16x2_t __b) {
548
  return __builtin_arm_usax(__a, __b);
549
}
550
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
551
__usub16(uint16x2_t __a, uint16x2_t __b) {
552
  return __builtin_arm_usub16(__a, __b);
553
}
554
#endif
555

556
/* 8.5.10 Parallel 16-bit multiplication */
557
#if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32
558
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
559
__smlad(int16x2_t __a, int16x2_t __b, int32_t __c) {
560
  return __builtin_arm_smlad(__a, __b, __c);
561
}
562
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
563
__smladx(int16x2_t __a, int16x2_t __b, int32_t __c) {
564
  return __builtin_arm_smladx(__a, __b, __c);
565
}
566
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
567
__smlald(int16x2_t __a, int16x2_t __b, int64_t __c) {
568
  return __builtin_arm_smlald(__a, __b, __c);
569
}
570
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
571
__smlaldx(int16x2_t __a, int16x2_t __b, int64_t __c) {
572
  return __builtin_arm_smlaldx(__a, __b, __c);
573
}
574
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
575
__smlsd(int16x2_t __a, int16x2_t __b, int32_t __c) {
576
  return __builtin_arm_smlsd(__a, __b, __c);
577
}
578
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
579
__smlsdx(int16x2_t __a, int16x2_t __b, int32_t __c) {
580
  return __builtin_arm_smlsdx(__a, __b, __c);
581
}
582
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
583
__smlsld(int16x2_t __a, int16x2_t __b, int64_t __c) {
584
  return __builtin_arm_smlsld(__a, __b, __c);
585
}
586
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
587
__smlsldx(int16x2_t __a, int16x2_t __b, int64_t __c) {
588
  return __builtin_arm_smlsldx(__a, __b, __c);
589
}
590
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
591
__smuad(int16x2_t __a, int16x2_t __b) {
592
  return __builtin_arm_smuad(__a, __b);
593
}
594
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
595
__smuadx(int16x2_t __a, int16x2_t __b) {
596
  return __builtin_arm_smuadx(__a, __b);
597
}
598
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
599
__smusd(int16x2_t __a, int16x2_t __b) {
600
  return __builtin_arm_smusd(__a, __b);
601
}
602
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
603
__smusdx(int16x2_t __a, int16x2_t __b) {
604
  return __builtin_arm_smusdx(__a, __b);
605
}
606
#endif
607

608
/* 8.6 Floating-point data-processing intrinsics */
609
#if (defined(__ARM_FEATURE_DIRECTED_ROUNDING)    &&                         \
610
  (__ARM_FEATURE_DIRECTED_ROUNDING))             &&                         \
611
  (defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE)
612
static __inline__ double __attribute__((__always_inline__, __nodebug__))
613
__rintn(double __a) {
614
  return __builtin_roundeven(__a);
615
}
616

617
static __inline__ float __attribute__((__always_inline__, __nodebug__))
618
__rintnf(float __a) {
619
  return __builtin_roundevenf(__a);
620
}
621
#endif
622

623
/* 8.8 CRC32 intrinsics */
624
#if (defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32) ||                   \
625
    (defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE)
626
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
627
__crc32b(uint32_t __a, uint8_t __b) {
628
  return __builtin_arm_crc32b(__a, __b);
629
}
630

631
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
632
__crc32h(uint32_t __a, uint16_t __b) {
633
  return __builtin_arm_crc32h(__a, __b);
634
}
635

636
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
637
__crc32w(uint32_t __a, uint32_t __b) {
638
  return __builtin_arm_crc32w(__a, __b);
639
}
640

641
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
642
__crc32d(uint32_t __a, uint64_t __b) {
643
  return __builtin_arm_crc32d(__a, __b);
644
}
645

646
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
647
__crc32cb(uint32_t __a, uint8_t __b) {
648
  return __builtin_arm_crc32cb(__a, __b);
649
}
650

651
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
652
__crc32ch(uint32_t __a, uint16_t __b) {
653
  return __builtin_arm_crc32ch(__a, __b);
654
}
655

656
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
657
__crc32cw(uint32_t __a, uint32_t __b) {
658
  return __builtin_arm_crc32cw(__a, __b);
659
}
660

661
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
662
__crc32cd(uint32_t __a, uint64_t __b) {
663
  return __builtin_arm_crc32cd(__a, __b);
664
}
665
#endif
666

667
/* 8.6 Floating-point data-processing intrinsics */
668
/* Armv8.3-A Javascript conversion intrinsic */
669
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
670
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__, target("v8.3a")))
671
__jcvt(double __a) {
672
  return __builtin_arm_jcvt(__a);
673
}
674
#endif
675

676
/* Armv8.5-A FP rounding intrinsics */
677
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
678
static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
679
__rint32zf(float __a) {
680
  return __builtin_arm_rint32zf(__a);
681
}
682

683
static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
684
__rint32z(double __a) {
685
  return __builtin_arm_rint32z(__a);
686
}
687

688
static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
689
__rint64zf(float __a) {
690
  return __builtin_arm_rint64zf(__a);
691
}
692

693
static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
694
__rint64z(double __a) {
695
  return __builtin_arm_rint64z(__a);
696
}
697

698
static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
699
__rint32xf(float __a) {
700
  return __builtin_arm_rint32xf(__a);
701
}
702

703
static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
704
__rint32x(double __a) {
705
  return __builtin_arm_rint32x(__a);
706
}
707

708
static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
709
__rint64xf(float __a) {
710
  return __builtin_arm_rint64xf(__a);
711
}
712

713
static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a")))
714
__rint64x(double __a) {
715
  return __builtin_arm_rint64x(__a);
716
}
717
#endif
718

719
/* 8.9 Armv8.7-A load/store 64-byte intrinsics */
720
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
721
typedef struct {
722
    uint64_t val[8];
723
} data512_t;
724

725
static __inline__ data512_t __attribute__((__always_inline__, __nodebug__, target("ls64")))
726
__arm_ld64b(const void *__addr) {
727
  data512_t __value;
728
  __builtin_arm_ld64b(__addr, __value.val);
729
  return __value;
730
}
731
static __inline__ void __attribute__((__always_inline__, __nodebug__, target("ls64")))
732
__arm_st64b(void *__addr, data512_t __value) {
733
  __builtin_arm_st64b(__addr, __value.val);
734
}
735
static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__, target("ls64")))
736
__arm_st64bv(void *__addr, data512_t __value) {
737
  return __builtin_arm_st64bv(__addr, __value.val);
738
}
739
static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__, target("ls64")))
740
__arm_st64bv0(void *__addr, data512_t __value) {
741
  return __builtin_arm_st64bv0(__addr, __value.val);
742
}
743
#endif
744

745
/* 11.1 Special register intrinsics */
746
#define __arm_rsr(sysreg) __builtin_arm_rsr(sysreg)
747
#define __arm_rsr64(sysreg) __builtin_arm_rsr64(sysreg)
748
#define __arm_rsr128(sysreg) __builtin_arm_rsr128(sysreg)
749
#define __arm_rsrp(sysreg) __builtin_arm_rsrp(sysreg)
750
#define __arm_rsrf(sysreg) __builtin_bit_cast(float, __arm_rsr(sysreg))
751
#define __arm_rsrf64(sysreg) __builtin_bit_cast(double, __arm_rsr64(sysreg))
752
#define __arm_wsr(sysreg, v) __builtin_arm_wsr(sysreg, v)
753
#define __arm_wsr64(sysreg, v) __builtin_arm_wsr64(sysreg, v)
754
#define __arm_wsr128(sysreg, v) __builtin_arm_wsr128(sysreg, v)
755
#define __arm_wsrp(sysreg, v) __builtin_arm_wsrp(sysreg, v)
756
#define __arm_wsrf(sysreg, v) __arm_wsr(sysreg, __builtin_bit_cast(uint32_t, v))
757
#define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg, __builtin_bit_cast(uint64_t, v))
758

759
/* 10.3 MTE intrinsics */
760
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
761
#define __arm_mte_create_random_tag(__ptr, __mask)  __builtin_arm_irg(__ptr, __mask)
762
#define __arm_mte_increment_tag(__ptr, __tag_offset)  __builtin_arm_addg(__ptr, __tag_offset)
763
#define __arm_mte_exclude_tag(__ptr, __excluded)  __builtin_arm_gmi(__ptr, __excluded)
764
#define __arm_mte_get_tag(__ptr) __builtin_arm_ldg(__ptr)
765
#define __arm_mte_set_tag(__ptr) __builtin_arm_stg(__ptr)
766
#define __arm_mte_ptrdiff(__ptra, __ptrb) __builtin_arm_subp(__ptra, __ptrb)
767

768
/* 18 memcpy family of operations intrinsics - MOPS */
769
#define __arm_mops_memset_tag(__tagged_address, __value, __size)    \
770
  __builtin_arm_mops_memset_tag(__tagged_address, __value, __size)
771
#endif
772

773
/* 11.3 Coprocessor Intrinsics */
774
#if defined(__ARM_FEATURE_COPROC)
775

776
#if (__ARM_FEATURE_COPROC & 0x1)
777

778
#if (__ARM_ARCH < 8)
779
#define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)                           \
780
  __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)
781
#endif /* __ARM_ARCH < 8 */
782

783
#define __arm_ldc(coproc, CRd, p) __builtin_arm_ldc(coproc, CRd, p)
784
#define __arm_stc(coproc, CRd, p) __builtin_arm_stc(coproc, CRd, p)
785

786
#define __arm_mcr(coproc, opc1, value, CRn, CRm, opc2)                         \
787
  __builtin_arm_mcr(coproc, opc1, value, CRn, CRm, opc2)
788
#define __arm_mrc(coproc, opc1, CRn, CRm, opc2)                                \
789
  __builtin_arm_mrc(coproc, opc1, CRn, CRm, opc2)
790

791
#if (__ARM_ARCH != 4) && (__ARM_ARCH < 8)
792
#define __arm_ldcl(coproc, CRd, p) __builtin_arm_ldcl(coproc, CRd, p)
793
#define __arm_stcl(coproc, CRd, p) __builtin_arm_stcl(coproc, CRd, p)
794
#endif /* (__ARM_ARCH != 4) && (__ARM_ARCH != 8) */
795

796
#if (__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8_1M_MAIN__)
797
#define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)                           \
798
  __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)
799
#define __arm_ldcl(coproc, CRd, p) __builtin_arm_ldcl(coproc, CRd, p)
800
#define __arm_stcl(coproc, CRd, p) __builtin_arm_stcl(coproc, CRd, p)
801
#endif /* ___ARM_ARCH_8M_MAIN__ */
802

803
#endif /* __ARM_FEATURE_COPROC & 0x1 */
804

805
#if (__ARM_FEATURE_COPROC & 0x2)
806
#define __arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2)                          \
807
  __builtin_arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2)
808
#define __arm_ldc2(coproc, CRd, p) __builtin_arm_ldc2(coproc, CRd, p)
809
#define __arm_stc2(coproc, CRd, p) __builtin_arm_stc2(coproc, CRd, p)
810
#define __arm_ldc2l(coproc, CRd, p) __builtin_arm_ldc2l(coproc, CRd, p)
811
#define __arm_stc2l(coproc, CRd, p) __builtin_arm_stc2l(coproc, CRd, p)
812
#define __arm_mcr2(coproc, opc1, value, CRn, CRm, opc2)                        \
813
  __builtin_arm_mcr2(coproc, opc1, value, CRn, CRm, opc2)
814
#define __arm_mrc2(coproc, opc1, CRn, CRm, opc2)                               \
815
  __builtin_arm_mrc2(coproc, opc1, CRn, CRm, opc2)
816
#endif
817

818
#if (__ARM_FEATURE_COPROC & 0x4)
819
#define __arm_mcrr(coproc, opc1, value, CRm)                                   \
820
  __builtin_arm_mcrr(coproc, opc1, value, CRm)
821
#define __arm_mrrc(coproc, opc1, CRm) __builtin_arm_mrrc(coproc, opc1, CRm)
822
#endif
823

824
#if (__ARM_FEATURE_COPROC & 0x8)
825
#define __arm_mcrr2(coproc, opc1, value, CRm)                                  \
826
  __builtin_arm_mcrr2(coproc, opc1, value, CRm)
827
#define __arm_mrrc2(coproc, opc1, CRm) __builtin_arm_mrrc2(coproc, opc1, CRm)
828
#endif
829

830
#endif // __ARM_FEATURE_COPROC
831

832
/* 17 Transactional Memory Extension (TME) Intrinsics */
833
#if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME
834

835
#define _TMFAILURE_REASON  0x00007fffu
836
#define _TMFAILURE_RTRY    0x00008000u
837
#define _TMFAILURE_CNCL    0x00010000u
838
#define _TMFAILURE_MEM     0x00020000u
839
#define _TMFAILURE_IMP     0x00040000u
840
#define _TMFAILURE_ERR     0x00080000u
841
#define _TMFAILURE_SIZE    0x00100000u
842
#define _TMFAILURE_NEST    0x00200000u
843
#define _TMFAILURE_DBG     0x00400000u
844
#define _TMFAILURE_INT     0x00800000u
845
#define _TMFAILURE_TRIVIAL 0x01000000u
846

847
#define __tstart()        __builtin_arm_tstart()
848
#define __tcommit()       __builtin_arm_tcommit()
849
#define __tcancel(__arg)  __builtin_arm_tcancel(__arg)
850
#define __ttest()         __builtin_arm_ttest()
851

852
#endif /* __ARM_FEATURE_TME */
853

854
/* 8.7 Armv8.5-A Random number generation intrinsics */
855
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
856
static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand")))
857
__rndr(uint64_t *__p) {
858
  return __builtin_arm_rndr(__p);
859
}
860
static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand")))
861
__rndrrs(uint64_t *__p) {
862
  return __builtin_arm_rndrrs(__p);
863
}
864
#endif
865

866
/* 11.2 Guarded Control Stack intrinsics */
867
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
868
static __inline__ void * __attribute__((__always_inline__, __nodebug__))
869
__gcspr() {
870
  return (void *)__builtin_arm_rsr64("gcspr_el0");
871
}
872

873
static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__, target("gcs")))
874
__gcspopm() {
875
  return __builtin_arm_gcspopm(0);
876
}
877

878
static __inline__ const void * __attribute__((__always_inline__, __nodebug__, target("gcs")))
879
__gcsss(const void *__stack) {
880
  return __builtin_arm_gcsss(__stack);
881
}
882
#endif
883

884
#if defined(__cplusplus)
885
}
886
#endif
887

888
#endif /* __ARM_ACLE_H */
889

890
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