CoCalc -- RISCVCInstructions.h

GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
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//===-- RISCVCInstructions.h ----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H
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#define LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H
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#include <cstdint>
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#include <variant>
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#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
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#include "RISCVInstructions.h"
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namespace lldb_private {
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/// Unified RISC-V C register encoding.
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struct RxC {
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  uint32_t rd;
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  bool shift = true;
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  operator int() { return rd; }
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  operator Rd() { return Rd{rd + (shift ? 8 : 0)}; }
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  operator Rs() { return Rs{rd + (shift ? 8 : 0)}; }
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};
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// decode register for RVC
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constexpr RxC DecodeCR_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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constexpr RxC DecodeCI_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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constexpr RxC DecodeCR_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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constexpr RxC DecodeCI_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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constexpr RxC DecodeCR_RS2(uint32_t inst) {
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  return RxC{(inst & 0x7C) >> 2, false};
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}
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constexpr RxC DecodeCIW_RD(uint32_t inst) { return RxC{(inst & 0x1C) >> 2}; }
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constexpr RxC DecodeCL_RD(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; }
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constexpr RxC DecodeCA_RD(uint32_t inst) { return RxC{(inst & 0x380) >> 7}; }
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constexpr RxC DecodeCB_RD(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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constexpr RxC DecodeCL_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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constexpr RxC DecodeCS_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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constexpr RxC DecodeCA_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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constexpr RxC DecodeCB_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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constexpr RxC DecodeCSS_RS2(uint32_t inst) { return DecodeCR_RS2(inst); }
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constexpr RxC DecodeCS_RS2(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; }
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constexpr RxC DecodeCA_RS2(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; }
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RISCVInst DecodeC_LWSP(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  uint16_t offset = ((inst << 4) & 0xc0)    // offset[7:6]
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                    | ((inst >> 7) & 0x20)  // offset[5]
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                    | ((inst >> 2) & 0x1c); // offset[4:2]
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  if (rd == 0)
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    return RESERVED{inst};
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  return LW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
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}
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RISCVInst DecodeC_LDSP(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  uint16_t offset = ((inst << 4) & 0x1c0)   // offset[8:6]
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                    | ((inst >> 7) & 0x20)  // offset[5]
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                    | ((inst >> 2) & 0x18); // offset[4:3]
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  if (rd == 0)
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    return RESERVED{inst};
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  return LD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
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}
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RISCVInst DecodeC_SWSP(uint32_t inst) {
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  uint16_t offset = ((inst >> 1) & 0xc0)    // offset[7:6]
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                    | ((inst >> 7) & 0x3c); // offset[5:2]
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  return SW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_SDSP(uint32_t inst) {
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  uint16_t offset = ((inst >> 1) & 0x1c0)   // offset[8:6]
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                    | ((inst >> 7) & 0x38); // offset[5:3]
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  return SD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_LW(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
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                    | ((inst >> 7) & 0x38) // imm[5:3]
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                    | ((inst >> 4) & 0x4); // imm[2]
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  return LW{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_LD(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
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                    | ((inst >> 7) & 0x38); // imm[5:3]
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  return LD{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_SW(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
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                    | ((inst >> 7) & 0x38) // imm[5:3]
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                    | ((inst >> 4) & 0x4); // imm[2]
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  return SW{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_SD(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
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                    | ((inst >> 7) & 0x38); // imm[5:3]
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  return SD{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_J(uint32_t inst) {
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  uint16_t offset = ((inst >> 1) & 0x800)   // offset[11]
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                    | ((inst << 2) & 0x400) // offset[10]
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                    | ((inst >> 1) & 0x300) // offset[9:8]
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                    | ((inst << 1) & 0x80)  // offset[7]
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                    | ((inst >> 1) & 0x40)  // offset[6]
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                    | ((inst << 3) & 0x20)  // offset[5]
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                    | ((inst >> 7) & 0x10)  // offset[4]
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                    | ((inst >> 2) & 0xe);  // offset[3:1]
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  if ((offset & 0x800) == 0)
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    return JAL{Rd{0}, uint32_t(offset)};
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  return JAL{Rd{0}, uint32_t(int32_t(int16_t(offset | 0xf000)))};
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}
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RISCVInst DecodeC_JR(uint32_t inst) {
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  auto rs1 = DecodeCR_RS1(inst);
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  if (rs1 == 0)
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    return RESERVED{inst};
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  return JALR{Rd{0}, rs1, 0};
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}
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RISCVInst DecodeC_JALR(uint32_t inst) {
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  auto rs1 = DecodeCR_RS1(inst);
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  if (rs1 == 0)
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    return EBREAK{inst};
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  return JALR{Rd{1}, rs1, 0};
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}
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constexpr uint16_t BOffset(uint32_t inst) {
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  return ((inst >> 4) & 0x100)  // offset[8]
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         | ((inst << 1) & 0xc0) // offset[7:6]
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         | ((inst << 3) & 0x20) // offset[5]
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         | ((inst >> 7) & 0x18) // offset[4:3]
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         | ((inst >> 2) & 0x6); // offset[2:1]
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}
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RISCVInst DecodeC_BNEZ(uint32_t inst) {
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  auto rs1 = DecodeCB_RS1(inst);
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  uint16_t offset = BOffset(inst);
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  if ((offset & 0x100) == 0)
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    return B{rs1, Rs{0}, uint32_t(offset), 0b001};
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  return B{rs1, Rs{0}, uint32_t(int32_t(int16_t(offset | 0xfe00))), 0b001};
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}
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RISCVInst DecodeC_BEQZ(uint32_t inst) {
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  auto rs1 = DecodeCB_RS1(inst);
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  uint16_t offset = BOffset(inst);
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  if ((offset & 0x100) == 0)
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    return B{rs1, Rs{0}, uint32_t(offset), 0b000};
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  return B{rs1, Rs{0}, uint32_t(int32_t(int16_t(offset | 0xfe00))), 0b000};
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}
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RISCVInst DecodeC_LI(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if ((imm & 0x20) == 0)
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    return ADDI{rd, Rs{0}, uint32_t(imm)};
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  return ADDI{rd, Rs{0}, uint32_t(int32_t(int8_t(imm | 0xc0)))};
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}
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RISCVInst DecodeC_LUI_ADDI16SP(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  if (rd == 0)
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    return HINT{inst};
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  if (rd == 2) {
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    uint16_t nzimm = ((inst >> 3) & 0x200)   // nzimm[9]
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                     | ((inst >> 2) & 0x10)  // nzimm[4]
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                     | ((inst << 1) & 0x40)  // nzimm[6]
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                     | ((inst << 4) & 0x180) // nzimm[8:7]
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                     | ((inst << 3) & 0x20); // nzimm[5]
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    if (nzimm == 0)
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      return RESERVED{inst};
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    if ((nzimm & 0x200) == 0)
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      return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)};
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    return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv},
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                uint32_t(int32_t(int16_t(nzimm | 0xfc00)))};
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  }
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  uint32_t imm =
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      ((uint32_t(inst) << 5) & 0x20000) | ((uint32_t(inst) << 10) & 0x1f000);
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  if ((imm & 0x20000) == 0)
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    return LUI{rd, imm};
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  return LUI{rd, uint32_t(int32_t(imm | 0xfffc0000))};
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}
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RISCVInst DecodeC_ADDI(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  if (rd == 0)
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    return NOP{inst};
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  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if ((imm & 0x20) == 0)
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    return ADDI{rd, rd, uint32_t(imm)};
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  return ADDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))};
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}
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RISCVInst DecodeC_ADDIW(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  if (rd == 0)
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    return RESERVED{inst};
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  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if ((imm & 0x20) == 0)
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    return ADDIW{rd, rd, uint32_t(imm)};
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  return ADDIW{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))};
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}
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RISCVInst DecodeC_ADDI4SPN(uint32_t inst) {
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  auto rd = DecodeCIW_RD(inst);
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  uint16_t nzuimm = ((inst >> 1) & 0x3c0)  // nzuimm[9:6]
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                    | ((inst >> 7) & 0x30) // nzuimm[5:4]
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                    | ((inst >> 2) & 0x8)  // nzuimm[3]
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                    | ((inst >> 4) & 0x4); // nzuimm[2]
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  if (rd == 0 && nzuimm == 0)
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    return INVALID{inst};
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  if (nzuimm == 0)
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    return RESERVED{inst};
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  return ADDI{rd, Rs{gpr_sp_riscv}, uint32_t(nzuimm)};
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}
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RISCVInst DecodeC_SLLI(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if (rd == 0 || shamt == 0)
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    return HINT{inst};
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  return SLLI{rd, rd, uint8_t(shamt)};
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}
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RISCVInst DecodeC_SRLI(uint32_t inst) {
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  auto rd = DecodeCB_RD(inst);
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  uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if (shamt == 0)
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    return HINT{inst};
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  return SRLI{rd, rd, uint8_t(shamt)};
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}
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RISCVInst DecodeC_SRAI(uint32_t inst) {
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  auto rd = DecodeCB_RD(inst);
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  uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if (shamt == 0)
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    return HINT{inst};
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  return SRAI{rd, rd, uint8_t(shamt)};
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}
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RISCVInst DecodeC_ANDI(uint32_t inst) {
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  auto rd = DecodeCB_RD(inst);
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  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
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  if ((imm & 0x20) == 0)
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    return ANDI{rd, rd, uint32_t(imm)};
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  return ANDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))};
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}
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RISCVInst DecodeC_MV(uint32_t inst) {
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  auto rd = DecodeCR_RD(inst);
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  auto rs2 = DecodeCR_RS2(inst);
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  if (rd == 0)
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    return HINT{inst};
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  return ADD{rd, Rs{0}, rs2};
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}
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RISCVInst DecodeC_ADD(uint32_t inst) {
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  auto rd = DecodeCR_RD(inst);
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  return ADD{rd, rd, DecodeCR_RS2(inst)};
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}
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RISCVInst DecodeC_AND(uint32_t inst) {
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  auto rd = DecodeCA_RD(inst);
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  return AND{rd, rd, DecodeCA_RS2(inst)};
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}
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RISCVInst DecodeC_OR(uint32_t inst) {
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  auto rd = DecodeCA_RD(inst);
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  return OR{rd, rd, DecodeCA_RS2(inst)};
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}
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RISCVInst DecodeC_XOR(uint32_t inst) {
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  auto rd = DecodeCA_RD(inst);
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  return XOR{rd, rd, DecodeCA_RS2(inst)};
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}
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RISCVInst DecodeC_SUB(uint32_t inst) {
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  auto rd = DecodeCA_RD(inst);
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  return SUB{rd, rd, DecodeCA_RS2(inst)};
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}
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RISCVInst DecodeC_SUBW(uint32_t inst) {
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  auto rd = DecodeCA_RD(inst);
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  return SUBW{rd, rd, DecodeCA_RS2(inst)};
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}
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RISCVInst DecodeC_ADDW(uint32_t inst) {
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  auto rd = DecodeCA_RD(inst);
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  return ADDW{rd, rd, DecodeCA_RS2(inst)};
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}
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RISCVInst DecodeC_FLW(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
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                    | ((inst >> 7) & 0x38) // imm[5:3]
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                    | ((inst >> 4) & 0x4); // imm[2]
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  return FLW{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_FSW(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
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                    | ((inst >> 7) & 0x38) // imm[5:3]
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                    | ((inst >> 4) & 0x4); // imm[2]
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  return FSW{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_FLWSP(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  uint16_t offset = ((inst << 4) & 0xc0)    // offset[7:6]
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                    | ((inst >> 7) & 0x20)  // offset[5]
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                    | ((inst >> 2) & 0x1c); // offset[4:2]
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  return FLW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
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}
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RISCVInst DecodeC_FSWSP(uint32_t inst) {
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  uint16_t offset = ((inst >> 1) & 0xc0)    // offset[7:6]
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                    | ((inst >> 7) & 0x3c); // offset[5:2]
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  return FSW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_FLDSP(uint32_t inst) {
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  auto rd = DecodeCI_RD(inst);
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  uint16_t offset = ((inst << 4) & 0x1c0)   // offset[8:6]
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                    | ((inst >> 7) & 0x20)  // offset[5]
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                    | ((inst >> 2) & 0x18); // offset[4:3]
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  return FLD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
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}
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RISCVInst DecodeC_FSDSP(uint32_t inst) {
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  uint16_t offset = ((inst >> 1) & 0x1c0)   // offset[8:6]
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                    | ((inst >> 7) & 0x38); // offset[5:3]
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  return FSD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_FLD(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
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                    | ((inst >> 7) & 0x38); // imm[5:3]
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  return FLD{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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}
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RISCVInst DecodeC_FSD(uint32_t inst) {
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  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
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                    | ((inst >> 7) & 0x38); // imm[5:3]
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  return FSD{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
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}
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} // namespace lldb_private
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#endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H
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