CoCalc -- RegisterContextMinidump

GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/llvm-project/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM.cpp
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//===-- RegisterContextMinidump_ARM.cpp -----------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RegisterContextMinidump_ARM.h"
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#include "Utility/ARM_DWARF_Registers.h"
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#include "Utility/ARM_ehframe_Registers.h"
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#include "lldb/Utility/RegisterValue.h"
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#include "lldb/Utility/DataExtractor.h"
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#include "lldb/Utility/LLDBAssert.h"
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#include "lldb/lldb-enumerations.h"
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// C includes
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#include <cassert>
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// C++ includes
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using namespace lldb;
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using namespace lldb_private;
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using namespace minidump;
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#define INV LLDB_INVALID_REGNUM
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#define OFFSET(r) (offsetof(RegisterContextMinidump_ARM::Context, r))
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#define DEF_R(i)                                                               \
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  {                                                                            \
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    "r" #i, nullptr, 4, OFFSET(r) + i * 4, eEncodingUint, eFormatHex,          \
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        {ehframe_r##i, dwarf_r##i, INV, INV, reg_r##i}, nullptr, nullptr,      \
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        nullptr,                                                               \
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  }
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#define DEF_R_ARG(i, n)                                                        \
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  {                                                                            \
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    "r" #i, "arg" #n, 4, OFFSET(r) + i * 4, eEncodingUint, eFormatHex,         \
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        {ehframe_r##i, dwarf_r##i, LLDB_REGNUM_GENERIC_ARG1 + i, INV,          \
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         reg_r##i},                                                            \
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        nullptr, nullptr, nullptr,                                             \
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  }
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#define DEF_D(i)                                                               \
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  {                                                                            \
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    "d" #i, nullptr, 8, OFFSET(d) + i * 8, eEncodingVector,                    \
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        eFormatVectorOfUInt8, {dwarf_d##i, dwarf_d##i, INV, INV, reg_d##i},    \
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        nullptr, nullptr, nullptr,                                             \
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  }
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#define DEF_S(i)                                                               \
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  {                                                                            \
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    "s" #i, nullptr, 4, OFFSET(s) + i * 4, eEncodingIEEE754, eFormatFloat,     \
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        {dwarf_s##i, dwarf_s##i, INV, INV, reg_s##i}, nullptr, nullptr,        \
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        nullptr,                                                               \
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  }
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#define DEF_Q(i)                                                               \
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  {                                                                            \
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    "q" #i, nullptr, 16, OFFSET(q) + i * 16, eEncodingVector,                  \
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        eFormatVectorOfUInt8, {dwarf_q##i, dwarf_q##i, INV, INV, reg_q##i},    \
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        nullptr, nullptr, nullptr,                                             \
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  }
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// Zero based LLDB register numbers for this register context
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enum {
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  // General Purpose Registers
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  reg_r0,
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  reg_r1,
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  reg_r2,
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  reg_r3,
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  reg_r4,
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  reg_r5,
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  reg_r6,
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  reg_r7,
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  reg_r8,
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  reg_r9,
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  reg_r10,
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  reg_r11,
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  reg_r12,
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  reg_sp,
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  reg_lr,
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  reg_pc,
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  reg_cpsr,
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  // Floating Point Registers
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  reg_fpscr,
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  reg_d0,
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  reg_d1,
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  reg_d2,
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  reg_d3,
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  reg_d4,
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  reg_d5,
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  reg_d6,
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  reg_d7,
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  reg_d8,
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  reg_d9,
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  reg_d10,
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  reg_d11,
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  reg_d12,
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  reg_d13,
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  reg_d14,
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  reg_d15,
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  reg_d16,
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  reg_d17,
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  reg_d18,
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  reg_d19,
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  reg_d20,
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  reg_d21,
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  reg_d22,
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  reg_d23,
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  reg_d24,
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  reg_d25,
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  reg_d26,
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  reg_d27,
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  reg_d28,
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  reg_d29,
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  reg_d30,
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  reg_d31,
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  reg_s0,
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  reg_s1,
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  reg_s2,
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  reg_s3,
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  reg_s4,
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  reg_s5,
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  reg_s6,
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  reg_s7,
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  reg_s8,
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  reg_s9,
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  reg_s10,
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  reg_s11,
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  reg_s12,
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  reg_s13,
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  reg_s14,
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  reg_s15,
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  reg_s16,
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  reg_s17,
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  reg_s18,
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  reg_s19,
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  reg_s20,
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  reg_s21,
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  reg_s22,
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  reg_s23,
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  reg_s24,
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  reg_s25,
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  reg_s26,
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  reg_s27,
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  reg_s28,
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  reg_s29,
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  reg_s30,
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  reg_s31,
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  reg_q0,
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  reg_q1,
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  reg_q2,
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  reg_q3,
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  reg_q4,
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  reg_q5,
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  reg_q6,
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  reg_q7,
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  reg_q8,
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  reg_q9,
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  reg_q10,
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  reg_q11,
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  reg_q12,
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  reg_q13,
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  reg_q14,
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  reg_q15,
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  k_num_regs
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};
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static RegisterInfo g_reg_info_apple_fp = {
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    "fp",
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    "r7",
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    4,
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    OFFSET(r) + 7 * 4,
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    eEncodingUint,
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    eFormatHex,
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    {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, INV, reg_r7},
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    nullptr,
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    nullptr,
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    nullptr,
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};
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static RegisterInfo g_reg_info_fp = {
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    "fp",
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    "r11",
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    4,
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    OFFSET(r) + 11 * 4,
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    eEncodingUint,
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    eFormatHex,
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    {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, INV, reg_r11},
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    nullptr,
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    nullptr,
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    nullptr,
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};
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// Register info definitions for this register context
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static RegisterInfo g_reg_infos[] = {
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    DEF_R_ARG(0, 1),
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    DEF_R_ARG(1, 2),
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    DEF_R_ARG(2, 3),
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    DEF_R_ARG(3, 4),
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    DEF_R(4),
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    DEF_R(5),
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    DEF_R(6),
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    DEF_R(7),
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    DEF_R(8),
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    DEF_R(9),
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    DEF_R(10),
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    DEF_R(11),
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    DEF_R(12),
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    {"sp",
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     "r13",
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     4,
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     OFFSET(r) + 13 * 4,
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     eEncodingUint,
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     eFormatHex,
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     {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, INV, reg_sp},
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     nullptr,
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     nullptr,
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     nullptr,
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    },
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    {"lr",
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     "r14",
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     4,
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     OFFSET(r) + 14 * 4,
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     eEncodingUint,
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     eFormatHex,
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     {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, INV, reg_lr},
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     nullptr,
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     nullptr,
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     nullptr,
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    },
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    {"pc",
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     "r15",
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     4,
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     OFFSET(r) + 15 * 4,
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     eEncodingUint,
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     eFormatHex,
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     {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, INV, reg_pc},
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     nullptr,
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     nullptr,
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     nullptr,
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    },
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    {"cpsr",
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     "psr",
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     4,
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     OFFSET(cpsr),
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     eEncodingUint,
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     eFormatHex,
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     {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, INV, reg_cpsr},
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     nullptr,
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     nullptr,
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     nullptr,
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    },
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    {"fpscr",
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     nullptr,
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     8,
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     OFFSET(fpscr),
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     eEncodingUint,
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     eFormatHex,
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     {INV, INV, INV, INV, reg_fpscr},
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     nullptr,
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     nullptr,
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     nullptr,
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    },
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    DEF_D(0),
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    DEF_D(1),
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    DEF_D(2),
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    DEF_D(3),
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    DEF_D(4),
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    DEF_D(5),
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    DEF_D(6),
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    DEF_D(7),
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    DEF_D(8),
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    DEF_D(9),
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    DEF_D(10),
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    DEF_D(11),
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    DEF_D(12),
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    DEF_D(13),
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    DEF_D(14),
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    DEF_D(15),
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    DEF_D(16),
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    DEF_D(17),
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    DEF_D(18),
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    DEF_D(19),
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    DEF_D(20),
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    DEF_D(21),
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    DEF_D(22),
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    DEF_D(23),
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    DEF_D(24),
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    DEF_D(25),
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    DEF_D(26),
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    DEF_D(27),
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    DEF_D(28),
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    DEF_D(29),
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    DEF_D(30),
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    DEF_D(31),
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    DEF_S(0),
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    DEF_S(1),
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    DEF_S(2),
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    DEF_S(3),
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    DEF_S(4),
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    DEF_S(5),
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    DEF_S(6),
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    DEF_S(7),
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    DEF_S(8),
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    DEF_S(9),
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    DEF_S(10),
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    DEF_S(11),
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    DEF_S(12),
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    DEF_S(13),
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    DEF_S(14),
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    DEF_S(15),
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    DEF_S(16),
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    DEF_S(17),
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    DEF_S(18),
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    DEF_S(19),
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    DEF_S(20),
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    DEF_S(21),
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    DEF_S(22),
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    DEF_S(23),
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    DEF_S(24),
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    DEF_S(25),
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    DEF_S(26),
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    DEF_S(27),
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    DEF_S(28),
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    DEF_S(29),
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    DEF_S(30),
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    DEF_S(31),
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    DEF_Q(0),
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    DEF_Q(1),
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    DEF_Q(2),
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    DEF_Q(3),
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    DEF_Q(4),
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    DEF_Q(5),
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    DEF_Q(6),
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    DEF_Q(7),
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    DEF_Q(8),
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    DEF_Q(9),
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    DEF_Q(10),
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    DEF_Q(11),
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    DEF_Q(12),
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    DEF_Q(13),
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    DEF_Q(14),
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    DEF_Q(15)};
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constexpr size_t k_num_reg_infos = std::size(g_reg_infos);
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// ARM general purpose registers.
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const uint32_t g_gpr_regnums[] = {
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    reg_r0,
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    reg_r1,
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    reg_r2,
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    reg_r3,
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    reg_r4,
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    reg_r5,
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    reg_r6,
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    reg_r7,
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    reg_r8,
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    reg_r9,
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    reg_r10,
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    reg_r11,
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    reg_r12,
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    reg_sp,
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    reg_lr,
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    reg_pc,
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    reg_cpsr,
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    LLDB_INVALID_REGNUM // register sets need to end with this flag
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};
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const uint32_t g_fpu_regnums[] = {
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    reg_fpscr,
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    reg_d0,
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    reg_d1,
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    reg_d2,
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    reg_d3,
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    reg_d4,
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    reg_d5,
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    reg_d6,
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    reg_d7,
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    reg_d8,
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    reg_d9,
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    reg_d10,
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    reg_d11,
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    reg_d12,
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    reg_d13,
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    reg_d14,
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    reg_d15,
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    reg_d16,
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    reg_d17,
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    reg_d18,
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    reg_d19,
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    reg_d20,
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    reg_d21,
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    reg_d22,
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    reg_d23,
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    reg_d24,
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    reg_d25,
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    reg_d26,
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    reg_d27,
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    reg_d28,
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    reg_d29,
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    reg_d30,
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    reg_d31,
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    reg_s0,
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    reg_s1,
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    reg_s2,
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    reg_s3,
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    reg_s4,
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    reg_s5,
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    reg_s6,
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    reg_s7,
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    reg_s8,
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    reg_s9,
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    reg_s10,
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    reg_s11,
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    reg_s12,
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    reg_s13,
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    reg_s14,
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    reg_s15,
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    reg_s16,
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    reg_s17,
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    reg_s18,
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    reg_s19,
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    reg_s20,
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    reg_s21,
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    reg_s22,
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    reg_s23,
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    reg_s24,
430
    reg_s25,
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    reg_s26,
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    reg_s27,
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    reg_s28,
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    reg_s29,
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    reg_s30,
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    reg_s31,
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    reg_q0,
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    reg_q1,
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    reg_q2,
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    reg_q3,
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    reg_q4,
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    reg_q5,
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    reg_q6,
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    reg_q7,
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    reg_q8,
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    reg_q9,
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    reg_q10,
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    reg_q11,
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    reg_q12,
450
    reg_q13,
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    reg_q14,
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    reg_q15,
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    LLDB_INVALID_REGNUM // register sets need to end with this flag
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};
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// Skip the last LLDB_INVALID_REGNUM in each count below by subtracting 1
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constexpr size_t k_num_gpr_regs = std::size(g_gpr_regnums) - 1;
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constexpr size_t k_num_fpu_regs = std::size(g_fpu_regnums) - 1;
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static RegisterSet g_reg_sets[] = {
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    {"General Purpose Registers", "gpr", k_num_gpr_regs, g_gpr_regnums},
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    {"Floating Point Registers", "fpu", k_num_fpu_regs, g_fpu_regnums},
463
};
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constexpr size_t k_num_reg_sets = std::size(g_reg_sets);
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RegisterContextMinidump_ARM::RegisterContextMinidump_ARM(
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    lldb_private::Thread &thread, const DataExtractor &data, bool apple)
469
    : RegisterContext(thread, 0), m_apple(apple) {
470
  lldb::offset_t offset = 0;
471
  m_regs.context_flags = data.GetU32(&offset);
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  for (unsigned i = 0; i < std::size(m_regs.r); ++i)
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    m_regs.r[i] = data.GetU32(&offset);
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  m_regs.cpsr = data.GetU32(&offset);
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  m_regs.fpscr = data.GetU64(&offset);
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  for (unsigned i = 0; i < std::size(m_regs.d); ++i)
477
    m_regs.d[i] = data.GetU64(&offset);
478
  lldbassert(k_num_regs == k_num_reg_infos);
479
}
480

481
size_t RegisterContextMinidump_ARM::GetRegisterCountStatic() {
482
  return k_num_regs;
483
}
484

485
// Used for unit testing so we can verify register info is filled in for
486
// all register flavors (DWARF, EH Frame, generic, etc).
487
size_t RegisterContextMinidump_ARM::GetRegisterCount() {
488
  return GetRegisterCountStatic();
489
}
490

491
// Used for unit testing so we can verify register info is filled in.
492
const RegisterInfo *
493
RegisterContextMinidump_ARM::GetRegisterInfoAtIndexStatic(size_t reg,
494
                                                          bool apple) {
495
  if (reg < k_num_reg_infos) {
496
    if (apple) {
497
      if (reg == reg_r7)
498
        return &g_reg_info_apple_fp;
499
    } else {
500
      if (reg == reg_r11)
501
        return &g_reg_info_fp;
502
    }
503
    return &g_reg_infos[reg];
504
  }
505
  return nullptr;
506
}
507

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const RegisterInfo *
509
RegisterContextMinidump_ARM::GetRegisterInfoAtIndex(size_t reg) {
510
  return GetRegisterInfoAtIndexStatic(reg, m_apple);
511
}
512

513
size_t RegisterContextMinidump_ARM::GetRegisterSetCount() {
514
  return k_num_reg_sets;
515
}
516

517
const RegisterSet *RegisterContextMinidump_ARM::GetRegisterSet(size_t set) {
518
  if (set < k_num_reg_sets)
519
    return &g_reg_sets[set];
520
  return nullptr;
521
}
522

523
const char *RegisterContextMinidump_ARM::GetRegisterName(unsigned reg) {
524
  if (reg < k_num_reg_infos)
525
    return g_reg_infos[reg].name;
526
  return nullptr;
527
}
528

529
bool RegisterContextMinidump_ARM::ReadRegister(const RegisterInfo *reg_info,
530
                                               RegisterValue &reg_value) {
531
  Status error;
532
  reg_value.SetFromMemoryData(
533
      *reg_info, (const uint8_t *)&m_regs + reg_info->byte_offset,
534
      reg_info->byte_size, lldb::eByteOrderLittle, error);
535
  return error.Success();
536
}
537

538
bool RegisterContextMinidump_ARM::WriteRegister(const RegisterInfo *,
539
                                                const RegisterValue &) {
540
  return false;
541
}
542

543
uint32_t RegisterContextMinidump_ARM::ConvertRegisterKindToRegisterNumber(
544
    lldb::RegisterKind kind, uint32_t num) {
545
  for (size_t i = 0; i < k_num_regs; ++i) {
546
    if (g_reg_infos[i].kinds[kind] == num)
547
      return i;
548
  }
549
  return LLDB_INVALID_REGNUM;
550
}
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