Path: blob/main/contrib/llvm-project/lldb/source/Utility/ARM64_ehframe_Registers.h
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//===-- ARM64_ehframe_Registers.h -------------------------------------*- C++1//-*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//89#ifndef LLDB_SOURCE_UTILITY_ARM64_EHFRAME_REGISTERS_H10#define LLDB_SOURCE_UTILITY_ARM64_EHFRAME_REGISTERS_H1112// The register numbers used in the eh_frame unwind information.13// Should be the same as DWARF register numbers.1415namespace arm64_ehframe {1617enum {18x0 = 0,19x1,20x2,21x3,22x4,23x5,24x6,25x7,26x8,27x9,28x10,29x11,30x12,31x13,32x14,33x15,34x16,35x17,36x18,37x19,38x20,39x21,40x22,41x23,42x24,43x25,44x26,45x27,46x28,47fp, // aka x2948lr, // aka x3049sp, // aka x31 aka wzr50pc, // value is 3251cpsr,52// 34-45 reserved5354// 64-bit SVE Vector granule pseudo register55vg = 46,5657// VG ́8-bit SVE first fault register58ffr = 47,5960// VG x ́8-bit SVE predicate registers61p0 = 48,62p1,63p2,64p3,65p4,66p5,67p6,68p7,69p8,70p9,71p10,72p11,73p12,74p13,75p14,76p15,7778// V0-V31 (128 bit vector registers)79v0 = 64,80v1,81v2,82v3,83v4,84v5,85v6,86v7,87v8,88v9,89v10,90v11,91v12,92v13,93v14,94v15,95v16,96v17,97v18,98v19,99v20,100v21,101v22,102v23,103v24,104v25,105v26,106v27,107v28,108v29,109v30,110v31,111112// VG ́64-bit SVE vector registers113z0 = 96,114z1,115z2,116z3,117z4,118z5,119z6,120z7,121z8,122z9,123z10,124z11,125z12,126z13,127z14,128z15,129z16,130z17,131z18,132z19,133z20,134z21,135z22,136z23,137z24,138z25,139z26,140z27,141z28,142z29,143z30,144z31145};146}147148#endif // LLDB_SOURCE_UTILITY_ARM64_EHFRAME_REGISTERS_H149150151