Path: blob/main/contrib/llvm-project/llvm/lib/CodeGen/CalcSpillWeights.cpp
35233 views
//===- CalcSpillWeights.cpp -----------------------------------------------===//1//2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3// See https://llvm.org/LICENSE.txt for license information.4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5//6//===----------------------------------------------------------------------===//78#include "llvm/CodeGen/CalcSpillWeights.h"9#include "llvm/ADT/SmallPtrSet.h"10#include "llvm/ADT/SmallSet.h"11#include "llvm/CodeGen/LiveInterval.h"12#include "llvm/CodeGen/LiveIntervals.h"13#include "llvm/CodeGen/MachineFunction.h"14#include "llvm/CodeGen/MachineInstr.h"15#include "llvm/CodeGen/MachineLoopInfo.h"16#include "llvm/CodeGen/MachineOperand.h"17#include "llvm/CodeGen/MachineRegisterInfo.h"18#include "llvm/CodeGen/StackMaps.h"19#include "llvm/CodeGen/TargetInstrInfo.h"20#include "llvm/CodeGen/TargetRegisterInfo.h"21#include "llvm/CodeGen/TargetSubtargetInfo.h"22#include "llvm/CodeGen/VirtRegMap.h"23#include "llvm/Support/Debug.h"24#include "llvm/Support/MathExtras.h"25#include "llvm/Support/raw_ostream.h"26#include <cassert>27#include <tuple>2829using namespace llvm;3031#define DEBUG_TYPE "calcspillweights"3233void VirtRegAuxInfo::calculateSpillWeightsAndHints() {34LLVM_DEBUG(dbgs() << "********** Compute Spill Weights **********\n"35<< "********** Function: " << MF.getName() << '\n');3637MachineRegisterInfo &MRI = MF.getRegInfo();38for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {39Register Reg = Register::index2VirtReg(I);40if (MRI.reg_nodbg_empty(Reg))41continue;42calculateSpillWeightAndHint(LIS.getInterval(Reg));43}44}4546// Return the preferred allocation register for reg, given a COPY instruction.47Register VirtRegAuxInfo::copyHint(const MachineInstr *MI, unsigned Reg,48const TargetRegisterInfo &TRI,49const MachineRegisterInfo &MRI) {50unsigned Sub, HSub;51Register HReg;52if (MI->getOperand(0).getReg() == Reg) {53Sub = MI->getOperand(0).getSubReg();54HReg = MI->getOperand(1).getReg();55HSub = MI->getOperand(1).getSubReg();56} else {57Sub = MI->getOperand(1).getSubReg();58HReg = MI->getOperand(0).getReg();59HSub = MI->getOperand(0).getSubReg();60}6162if (!HReg)63return 0;6465if (HReg.isVirtual())66return Sub == HSub ? HReg : Register();6768const TargetRegisterClass *RC = MRI.getRegClass(Reg);69MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg();70if (RC->contains(CopiedPReg))71return CopiedPReg;7273// Check if reg:sub matches so that a super register could be hinted.74if (Sub)75return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC);7677return 0;78}7980// Check if all values in LI are rematerializable81bool VirtRegAuxInfo::isRematerializable(const LiveInterval &LI,82const LiveIntervals &LIS,83const VirtRegMap &VRM,84const TargetInstrInfo &TII) {85Register Reg = LI.reg();86Register Original = VRM.getOriginal(Reg);87for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();88I != E; ++I) {89const VNInfo *VNI = *I;90if (VNI->isUnused())91continue;92if (VNI->isPHIDef())93return false;9495MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);96assert(MI && "Dead valno in interval");9798// Trace copies introduced by live range splitting. The inline99// spiller can rematerialize through these copies, so the spill100// weight must reflect this.101while (TII.isFullCopyInstr(*MI)) {102// The copy destination must match the interval register.103if (MI->getOperand(0).getReg() != Reg)104return false;105106// Get the source register.107Reg = MI->getOperand(1).getReg();108109// If the original (pre-splitting) registers match this110// copy came from a split.111if (!Reg.isVirtual() || VRM.getOriginal(Reg) != Original)112return false;113114// Follow the copy live-in value.115const LiveInterval &SrcLI = LIS.getInterval(Reg);116LiveQueryResult SrcQ = SrcLI.Query(VNI->def);117VNI = SrcQ.valueIn();118assert(VNI && "Copy from non-existing value");119if (VNI->isPHIDef())120return false;121MI = LIS.getInstructionFromIndex(VNI->def);122assert(MI && "Dead valno in interval");123}124125if (!TII.isTriviallyReMaterializable(*MI))126return false;127}128return true;129}130131bool VirtRegAuxInfo::isLiveAtStatepointVarArg(LiveInterval &LI) {132return any_of(VRM.getRegInfo().reg_operands(LI.reg()),133[](MachineOperand &MO) {134MachineInstr *MI = MO.getParent();135if (MI->getOpcode() != TargetOpcode::STATEPOINT)136return false;137return StatepointOpers(MI).getVarIdx() <= MO.getOperandNo();138});139}140141void VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &LI) {142float Weight = weightCalcHelper(LI);143// Check if unspillable.144if (Weight < 0)145return;146LI.setWeight(Weight);147}148149static bool canMemFoldInlineAsm(LiveInterval &LI,150const MachineRegisterInfo &MRI) {151for (const MachineOperand &MO : MRI.reg_operands(LI.reg())) {152const MachineInstr *MI = MO.getParent();153if (MI->isInlineAsm() && MI->mayFoldInlineAsmRegOp(MI->getOperandNo(&MO)))154return true;155}156157return false;158}159160float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,161SlotIndex *End) {162MachineRegisterInfo &MRI = MF.getRegInfo();163const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();164const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();165MachineBasicBlock *MBB = nullptr;166float TotalWeight = 0;167unsigned NumInstr = 0; // Number of instructions using LI168SmallPtrSet<MachineInstr *, 8> Visited;169170std::pair<unsigned, Register> TargetHint = MRI.getRegAllocationHint(LI.reg());171172if (LI.isSpillable()) {173Register Reg = LI.reg();174Register Original = VRM.getOriginal(Reg);175const LiveInterval &OrigInt = LIS.getInterval(Original);176// li comes from a split of OrigInt. If OrigInt was marked177// as not spillable, make sure the new interval is marked178// as not spillable as well.179if (!OrigInt.isSpillable())180LI.markNotSpillable();181}182183// Don't recompute spill weight for an unspillable register.184bool IsSpillable = LI.isSpillable();185186bool IsLocalSplitArtifact = Start && End;187188// Do not update future local split artifacts.189bool ShouldUpdateLI = !IsLocalSplitArtifact;190191if (IsLocalSplitArtifact) {192MachineBasicBlock *LocalMBB = LIS.getMBBFromIndex(*End);193assert(LocalMBB == LIS.getMBBFromIndex(*Start) &&194"start and end are expected to be in the same basic block");195196// Local split artifact will have 2 additional copy instructions and they197// will be in the same BB.198// localLI = COPY other199// ...200// other = COPY localLI201TotalWeight += LiveIntervals::getSpillWeight(true, false, &MBFI, LocalMBB);202TotalWeight += LiveIntervals::getSpillWeight(false, true, &MBFI, LocalMBB);203204NumInstr += 2;205}206207// CopyHint is a sortable hint derived from a COPY instruction.208struct CopyHint {209const Register Reg;210const float Weight;211CopyHint(Register R, float W) : Reg(R), Weight(W) {}212bool operator<(const CopyHint &Rhs) const {213// Always prefer any physreg hint.214if (Reg.isPhysical() != Rhs.Reg.isPhysical())215return Reg.isPhysical();216if (Weight != Rhs.Weight)217return (Weight > Rhs.Weight);218return Reg.id() < Rhs.Reg.id(); // Tie-breaker.219}220};221222bool IsExiting = false;223std::set<CopyHint> CopyHints;224DenseMap<unsigned, float> Hint;225for (MachineRegisterInfo::reg_instr_nodbg_iterator226I = MRI.reg_instr_nodbg_begin(LI.reg()),227E = MRI.reg_instr_nodbg_end();228I != E;) {229MachineInstr *MI = &*(I++);230231// For local split artifacts, we are interested only in instructions between232// the expected start and end of the range.233SlotIndex SI = LIS.getInstructionIndex(*MI);234if (IsLocalSplitArtifact && ((SI < *Start) || (SI > *End)))235continue;236237NumInstr++;238bool identityCopy = false;239auto DestSrc = TII.isCopyInstr(*MI);240if (DestSrc) {241const MachineOperand *DestRegOp = DestSrc->Destination;242const MachineOperand *SrcRegOp = DestSrc->Source;243identityCopy = DestRegOp->getReg() == SrcRegOp->getReg() &&244DestRegOp->getSubReg() == SrcRegOp->getSubReg();245}246247if (identityCopy || MI->isImplicitDef())248continue;249if (!Visited.insert(MI).second)250continue;251252// For terminators that produce values, ask the backend if the register is253// not spillable.254if (TII.isUnspillableTerminator(MI) &&255MI->definesRegister(LI.reg(), /*TRI=*/nullptr)) {256LI.markNotSpillable();257return -1.0f;258}259260// Force Weight onto the stack so that x86 doesn't add hidden precision,261// similar to HWeight below.262stack_float_t Weight = 1.0f;263if (IsSpillable) {264// Get loop info for mi.265if (MI->getParent() != MBB) {266MBB = MI->getParent();267const MachineLoop *Loop = Loops.getLoopFor(MBB);268IsExiting = Loop ? Loop->isLoopExiting(MBB) : false;269}270271// Calculate instr weight.272bool Reads, Writes;273std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg());274Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI);275276// Give extra weight to what looks like a loop induction variable update.277if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB))278Weight *= 3;279280TotalWeight += Weight;281}282283// Get allocation hints from copies.284if (!TII.isCopyInstr(*MI))285continue;286Register HintReg = copyHint(MI, LI.reg(), TRI, MRI);287if (!HintReg)288continue;289// Force HWeight onto the stack so that x86 doesn't add hidden precision,290// making the comparison incorrectly pass (i.e., 1 > 1 == true??).291stack_float_t HWeight = Hint[HintReg] += Weight;292if (HintReg.isVirtual() || MRI.isAllocatable(HintReg))293CopyHints.insert(CopyHint(HintReg, HWeight));294}295296// Pass all the sorted copy hints to mri.297if (ShouldUpdateLI && CopyHints.size()) {298// Remove a generic hint if previously added by target.299if (TargetHint.first == 0 && TargetHint.second)300MRI.clearSimpleHint(LI.reg());301302SmallSet<Register, 4> HintedRegs;303for (const auto &Hint : CopyHints) {304if (!HintedRegs.insert(Hint.Reg).second ||305(TargetHint.first != 0 && Hint.Reg == TargetHint.second))306// Don't add the same reg twice or the target-type hint again.307continue;308MRI.addRegAllocationHint(LI.reg(), Hint.Reg);309}310311// Weakly boost the spill weight of hinted registers.312TotalWeight *= 1.01F;313}314315// If the live interval was already unspillable, leave it that way.316if (!IsSpillable)317return -1.0;318319// Mark li as unspillable if all live ranges are tiny and the interval320// is not live at any reg mask. If the interval is live at a reg mask321// spilling may be required. If li is live as use in statepoint instruction322// spilling may be required due to if we mark interval with use in statepoint323// as not spillable we are risky to end up with no register to allocate.324// At the same time STATEPOINT instruction is perfectly fine to have this325// operand on stack, so spilling such interval and folding its load from stack326// into instruction itself makes perfect sense.327if (ShouldUpdateLI && LI.isZeroLength(LIS.getSlotIndexes()) &&328!LI.isLiveAtIndexes(LIS.getRegMaskSlots()) &&329!isLiveAtStatepointVarArg(LI) && !canMemFoldInlineAsm(LI, MRI)) {330LI.markNotSpillable();331return -1.0;332}333334// If all of the definitions of the interval are re-materializable,335// it is a preferred candidate for spilling.336// FIXME: this gets much more complicated once we support non-trivial337// re-materialization.338if (isRematerializable(LI, LIS, VRM, *MF.getSubtarget().getInstrInfo()))339TotalWeight *= 0.5F;340341if (IsLocalSplitArtifact)342return normalize(TotalWeight, Start->distance(*End), NumInstr);343return normalize(TotalWeight, LI.getSize(), NumInstr);344}345346347