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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/contrib/llvm-project/llvm/lib/Target/ARM/ARMFeatures.h
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//===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//

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//

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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

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// See https://llvm.org/LICENSE.txt for license information.

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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

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//

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//===----------------------------------------------------------------------===//

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//

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// This file contains the code shared between ARM CodeGen and ARM MC

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//

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//===----------------------------------------------------------------------===//

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#ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H

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#define LLVM_LIB_TARGET_ARM_ARMFEATURES_H

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#include "MCTargetDesc/ARMMCTargetDesc.h"

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namespace llvm {

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template<typename InstrType> // could be MachineInstr or MCInst

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bool IsCPSRDead(const InstrType *Instr);

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template<typename InstrType> // could be MachineInstr or MCInst

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inline bool isV8EligibleForIT(const InstrType *Instr) {

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  switch (Instr->getOpcode()) {

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  default:

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    return false;

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  case ARM::tADC:

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  case ARM::tADDi3:

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  case ARM::tADDi8:

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  case ARM::tADDrr:

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  case ARM::tAND:

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  case ARM::tASRri:

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  case ARM::tASRrr:

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  case ARM::tBIC:

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  case ARM::tEOR:

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  case ARM::tLSLri:

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  case ARM::tLSLrr:

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  case ARM::tLSRri:

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  case ARM::tLSRrr:

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  case ARM::tMOVi8:

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  case ARM::tMUL:

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  case ARM::tMVN:

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  case ARM::tORR:

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  case ARM::tROR:

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  case ARM::tRSB:

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  case ARM::tSBC:

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  case ARM::tSUBi3:

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  case ARM::tSUBi8:

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  case ARM::tSUBrr:

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    // Outside of an IT block, these set CPSR.

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    return IsCPSRDead(Instr);

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  case ARM::tADDrSPi:

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  case ARM::tCMNz:

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  case ARM::tCMPi8:

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  case ARM::tCMPr:

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  case ARM::tLDRBi:

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  case ARM::tLDRBr:

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  case ARM::tLDRHi:

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  case ARM::tLDRHr:

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  case ARM::tLDRSB:

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  case ARM::tLDRSH:

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  case ARM::tLDRi:

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  case ARM::tLDRr:

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  case ARM::tLDRspi:

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  case ARM::tSTRBi:

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  case ARM::tSTRBr:

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  case ARM::tSTRHi:

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  case ARM::tSTRHr:

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  case ARM::tSTRi:

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  case ARM::tSTRr:

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  case ARM::tSTRspi:

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  case ARM::tTST:

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    return true;

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// there are some "conditionally deprecated" opcodes

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  case ARM::tADDspr:

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  case ARM::tBLXr:

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  case ARM::tBLXr_noip:

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    return Instr->getOperand(2).getReg() != ARM::PC;

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  // ADD PC, SP and BLX PC were always unpredictable,

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  // now on top of it they're deprecated

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  case ARM::tADDrSP:

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  case ARM::tBX:

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    return Instr->getOperand(0).getReg() != ARM::PC;

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  case ARM::tADDhirr:

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    return Instr->getOperand(0).getReg() != ARM::PC &&

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           Instr->getOperand(2).getReg() != ARM::PC;

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  case ARM::tCMPhir:

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  case ARM::tMOVr:

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    return Instr->getOperand(0).getReg() != ARM::PC &&

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           Instr->getOperand(1).getReg() != ARM::PC;

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  }

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}

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}

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#endif

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