Path: blob/main/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h
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//===-- AVRFixupKinds.h - AVR Specific Fixup Entries ------------*- C++ -*-===//1//2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3// See https://llvm.org/LICENSE.txt for license information.4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5//6//===----------------------------------------------------------------------===//78#ifndef LLVM_AVR_FIXUP_KINDS_H9#define LLVM_AVR_FIXUP_KINDS_H1011#include "llvm/MC/MCFixup.h"1213namespace llvm {14namespace AVR {1516/// The set of supported fixups.17///18/// Although most of the current fixup types reflect a unique relocation19/// one can have multiple fixup types for a given relocation and thus need20/// to be uniquely named.21///22/// \note This table *must* be in the same order of23/// MCFixupKindInfo Infos[AVR::NumTargetFixupKinds]24/// in `AVRAsmBackend.cpp`.25enum Fixups {26/// A 32-bit AVR fixup.27fixup_32 = FirstTargetFixupKind,2829/// A 7-bit PC-relative fixup for the family of conditional30/// branches which take 7-bit targets (BRNE,BRGT,etc).31fixup_7_pcrel,32/// A 12-bit PC-relative fixup for the family of branches33/// which take 12-bit targets (RJMP,RCALL,etc).34/// \note Although the fixup is labelled as 13 bits, it35/// is actually only encoded in 12. The reason for36/// The nonmenclature is that AVR branch targets are37/// rightshifted by 1, because instructions are always38/// aligned to 2 bytes, so the 0'th bit is always 0.39/// This way there is 13-bits of precision.40fixup_13_pcrel,4142/// A 16-bit address.43fixup_16,44/// A 16-bit program memory address.45fixup_16_pm,4647/// Replaces the 8-bit immediate with another value.48fixup_ldi,4950/// Replaces the immediate operand of a 16-bit `Rd, K` instruction51/// with the lower 8 bits of a 16-bit value (bits 0-7).52fixup_lo8_ldi,53/// Replaces the immediate operand of a 16-bit `Rd, K` instruction54/// with the upper 8 bits of a 16-bit value (bits 8-15).55fixup_hi8_ldi,56/// Replaces the immediate operand of a 16-bit `Rd, K` instruction57/// with the upper 8 bits of a 24-bit value (bits 16-23).58fixup_hh8_ldi,59/// Replaces the immediate operand of a 16-bit `Rd, K` instruction60/// with the upper 8 bits of a 32-bit value (bits 24-31).61fixup_ms8_ldi,6263/// Replaces the immediate operand of a 16-bit `Rd, K` instruction64/// with the lower 8 bits of a negated 16-bit value (bits 0-7).65fixup_lo8_ldi_neg,66/// Replaces the immediate operand of a 16-bit `Rd, K` instruction67/// with the upper 8 bits of a negated 16-bit value (bits 8-15).68fixup_hi8_ldi_neg,69/// Replaces the immediate operand of a 16-bit `Rd, K` instruction70/// with the upper 8 bits of a negated 24-bit value (bits 16-23).71fixup_hh8_ldi_neg,72/// Replaces the immediate operand of a 16-bit `Rd, K` instruction73/// with the upper 8 bits of a negated 32-bit value (bits 24-31).74fixup_ms8_ldi_neg,7576/// Replaces the immediate operand of a 16-bit `Rd, K` instruction77/// with the lower 8 bits of a 16-bit program memory address value (bits 0-7).78fixup_lo8_ldi_pm,79/// Replaces the immediate operand of a 16-bit `Rd, K` instruction80/// with the upper 8 bits of a 16-bit program memory address value (bits81/// 8-15).82fixup_hi8_ldi_pm,83/// Replaces the immediate operand of a 16-bit `Rd, K` instruction84/// with the upper 8 bits of a 24-bit program memory address value (bits85/// 16-23).86fixup_hh8_ldi_pm,8788/// Replaces the immediate operand of a 16-bit `Rd, K` instruction89/// with the lower 8 bits of a negated 16-bit program memory address value90/// (bits 0-7).91fixup_lo8_ldi_pm_neg,92/// Replaces the immediate operand of a 16-bit `Rd, K` instruction93/// with the upper 8 bits of a negated 16-bit program memory address value94/// (bits 8-15).95fixup_hi8_ldi_pm_neg,96/// Replaces the immediate operand of a 16-bit `Rd, K` instruction97/// with the upper 8 bits of a negated 24-bit program memory address value98/// (bits 16-23).99fixup_hh8_ldi_pm_neg,100101/// A 22-bit fixup for the target of a `CALL k` or `JMP k` instruction.102fixup_call,103104fixup_6,105/// A symbol+addr fixup for the `LDD <x>+<n>, <r>" family of instructions.106fixup_6_adiw,107108fixup_lo8_ldi_gs,109fixup_hi8_ldi_gs,110111fixup_8,112fixup_8_lo8,113fixup_8_hi8,114fixup_8_hlo8,115116fixup_diff8,117fixup_diff16,118fixup_diff32,119120fixup_lds_sts_16,121122/// A 6-bit port address.123fixup_port6,124/// A 5-bit port address.125fixup_port5,126127// Marker128LastTargetFixupKind,129NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind130};131132namespace fixups {133134/// Adjusts the value of a branch target.135/// All branch targets in AVR are rightshifted by 1 to take advantage136/// of the fact that all instructions are aligned to addresses of size137/// 2, so bit 0 of an address is always 0. This gives us another bit138/// of precision.139/// \param [in,out] val The target to adjust.140template <typename T> inline void adjustBranchTarget(T &val) { val >>= 1; }141142} // end of namespace fixups143} // namespace AVR144} // namespace llvm145146#endif // LLVM_AVR_FIXUP_KINDS_H147148149