CoCalc -- HexagonDisassembler.cpp

GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
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//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCChecker.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "TargetInfo/HexagonTargetInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <memory>
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#define DEBUG_TYPE "hexagon-disassembler"
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using namespace llvm;
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using namespace Hexagon;
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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/// Hexagon disassembler for all Hexagon platforms.
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class HexagonDisassembler : public MCDisassembler {
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public:
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  std::unique_ptr<MCInstrInfo const> const MCII;
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  std::unique_ptr<MCInst *> CurrentBundle;
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  mutable MCInst const *CurrentExtender;
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  HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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                      MCInstrInfo const *MCII)
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      : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
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        CurrentExtender(nullptr) {}
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  DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
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                                    ArrayRef<uint8_t> Bytes, uint64_t Address,
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                                    raw_ostream &CStream, bool &Complete) const;
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  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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                              ArrayRef<uint8_t> Bytes, uint64_t Address,
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                              raw_ostream &CStream) const override;
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  void remapInstruction(MCInst &Instr) const;
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};
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static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
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                          int64_t Value) {
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  MCInstrInfo MCII = *Disassembler.MCII;
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  if (!Disassembler.CurrentExtender ||
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      MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
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    return Value;
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  unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
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  uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
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  int64_t Bits;
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  bool Success =
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      Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
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          Bits);
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  assert(Success);
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  (void)Success;
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  uint64_t Upper26 = static_cast<uint64_t>(Bits);
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  uint64_t Operand = Upper26 | Lower6;
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  return Operand;
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}
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static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
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  return *static_cast<HexagonDisassembler const *>(Decoder);
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}
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template <size_t T>
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static void signedDecoder(MCInst &MI, unsigned tmp,
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                          const MCDisassembler *Decoder) {
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  HexagonDisassembler const &Disassembler = disassembler(Decoder);
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  int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
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  int64_t Extended = SignExtend64<32>(FullValue);
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  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
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}
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}
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// Forward declare these because the auto-generated code will reference them.
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// Definitions are further down.
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                               uint64_t Address,
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                                               const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                  uint64_t Address,
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                                  const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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                               const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
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                                             uint64_t Address,
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                                             const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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                              const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                         uint64_t Address,
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                                         const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
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                                             uint64_t Address,
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                                             const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
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                                              uint64_t Address,
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                                              const MCDisassembler *Decoder);
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static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                                uint64_t Address,
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                                                const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
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                                             uint64_t Address,
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                                             const MCDisassembler *Decoder);
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static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                               uint64_t Address,
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                                               const MCDisassembler *Decoder);
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static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                                 uint64_t Address,
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                                                 const MCDisassembler *Decoder);
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static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                               uint64_t Address,
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                                               const MCDisassembler *Decoder);
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static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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                                               uint64_t Address,
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                                               const MCDisassembler *Decoder);
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static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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                                                 uint64_t Address,
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                                                 const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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                               const MCDisassembler *Decoder);
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static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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                                                 uint64_t Address,
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                                                 const MCDisassembler *Decoder);
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static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
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                                       uint64_t Address,
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                                       const MCDisassembler *Decoder);
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static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
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                                    uint64_t /*Address*/,
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                                    const MCDisassembler *Decoder);
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static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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                                    const MCDisassembler *Decoder);
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#include "HexagonDepDecoders.inc"
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#include "HexagonGenDisassemblerTables.inc"
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static MCDisassembler *createHexagonDisassembler(const Target &T,
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                                                 const MCSubtargetInfo &STI,
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                                                 MCContext &Ctx) {
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  return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler() {
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  TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
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                                         createHexagonDisassembler);
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}
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DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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                                                 ArrayRef<uint8_t> Bytes,
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                                                 uint64_t Address,
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                                                 raw_ostream &cs) const {
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  DecodeStatus Result = DecodeStatus::Success;
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  bool Complete = false;
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  Size = 0;
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  *CurrentBundle = &MI;
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  MI.setOpcode(Hexagon::BUNDLE);
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  MI.addOperand(MCOperand::createImm(0));
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  while (Result == Success && !Complete) {
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    if (Bytes.size() < HEXAGON_INSTR_SIZE)
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      return MCDisassembler::Fail;
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    MCInst *Inst = getContext().createMCInst();
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    Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete);
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    MI.addOperand(MCOperand::createInst(Inst));
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    Size += HEXAGON_INSTR_SIZE;
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    Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
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  }
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  if (Result == MCDisassembler::Fail)
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    return Result;
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  if (Size > HEXAGON_MAX_PACKET_SIZE)
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    return MCDisassembler::Fail;
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  const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
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  const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
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  HexagonMCChecker Checker(getContext(), *MCII, STI_, MI,
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                           *getContext().getRegisterInfo(), false);
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  if (!Checker.check())
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    return MCDisassembler::Fail;
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  remapInstruction(MI);
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  return MCDisassembler::Success;
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}
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void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
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  for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
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    auto &MI = const_cast<MCInst &>(*I.getInst());
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    switch (MI.getOpcode()) {
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    case Hexagon::S2_allocframe:
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      if (MI.getOperand(0).getReg() == Hexagon::R29) {
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        MI.setOpcode(Hexagon::S6_allocframe_to_raw);
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        MI.erase(MI.begin () + 1);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L2_deallocframe:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(1).getReg() == Hexagon::R30) {
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        MI.setOpcode(L6_deallocframe_map_to_raw);
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        MI.erase(MI.begin () + 1);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(1).getReg() == Hexagon::R30) {
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        MI.setOpcode(L6_return_map_to_raw);
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        MI.erase(MI.begin () + 1);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return_t:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(2).getReg() == Hexagon::R30) {
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        MI.setOpcode(L4_return_map_to_raw_t);
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        MI.erase(MI.begin () + 2);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return_f:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(2).getReg() == Hexagon::R30) {
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        MI.setOpcode(L4_return_map_to_raw_f);
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        MI.erase(MI.begin () + 2);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return_tnew_pt:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(2).getReg() == Hexagon::R30) {
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        MI.setOpcode(L4_return_map_to_raw_tnew_pt);
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        MI.erase(MI.begin () + 2);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return_fnew_pt:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(2).getReg() == Hexagon::R30) {
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        MI.setOpcode(L4_return_map_to_raw_fnew_pt);
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        MI.erase(MI.begin () + 2);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return_tnew_pnt:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(2).getReg() == Hexagon::R30) {
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        MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
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        MI.erase(MI.begin () + 2);
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        MI.erase(MI.begin ());
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      }
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      break;
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    case Hexagon::L4_return_fnew_pnt:
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      if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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          MI.getOperand(2).getReg() == Hexagon::R30) {
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        MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
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        MI.erase(MI.begin () + 2);
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        MI.erase(MI.begin ());
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      }
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      break;
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    }
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  }
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}
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static void adjustDuplex(MCInst &MI, MCContext &Context) {
288
  switch (MI.getOpcode()) {
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  case Hexagon::SA1_setin1:
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    MI.insert(MI.begin() + 1,
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              MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
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    break;
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  case Hexagon::SA1_dec:
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    MI.insert(MI.begin() + 2,
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              MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
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    break;
297
  default:
298
    break;
299
  }
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}
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DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
303
                                                       ArrayRef<uint8_t> Bytes,
304
                                                       uint64_t Address,
305
                                                       raw_ostream &cs,
306
                                                       bool &Complete) const {
307
  assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
308

309
  uint32_t Instruction = support::endian::read32le(Bytes.data());
310

311
  auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
312
  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
313
      HexagonII::INST_PARSE_LOOP_END) {
314
    if (BundleSize == 0)
315
      HexagonMCInstrInfo::setInnerLoop(MCB);
316
    else if (BundleSize == 1)
317
      HexagonMCInstrInfo::setOuterLoop(MCB);
318
    else
319
      return DecodeStatus::Fail;
320
  }
321

322
  CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
323
      MCB, HexagonMCInstrInfo::bundleSize(MCB));
324

325
  DecodeStatus Result = DecodeStatus::Fail;
326
  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
327
      HexagonII::INST_PARSE_DUPLEX) {
328
    unsigned duplexIClass;
329
    uint8_t const *DecodeLow, *DecodeHigh;
330
    duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
331
    switch (duplexIClass) {
332
    default:
333
      return MCDisassembler::Fail;
334
    case 0:
335
      DecodeLow = DecoderTableSUBINSN_L132;
336
      DecodeHigh = DecoderTableSUBINSN_L132;
337
      break;
338
    case 1:
339
      DecodeLow = DecoderTableSUBINSN_L232;
340
      DecodeHigh = DecoderTableSUBINSN_L132;
341
      break;
342
    case 2:
343
      DecodeLow = DecoderTableSUBINSN_L232;
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      DecodeHigh = DecoderTableSUBINSN_L232;
345
      break;
346
    case 3:
347
      DecodeLow = DecoderTableSUBINSN_A32;
348
      DecodeHigh = DecoderTableSUBINSN_A32;
349
      break;
350
    case 4:
351
      DecodeLow = DecoderTableSUBINSN_L132;
352
      DecodeHigh = DecoderTableSUBINSN_A32;
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      break;
354
    case 5:
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      DecodeLow = DecoderTableSUBINSN_L232;
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      DecodeHigh = DecoderTableSUBINSN_A32;
357
      break;
358
    case 6:
359
      DecodeLow = DecoderTableSUBINSN_S132;
360
      DecodeHigh = DecoderTableSUBINSN_A32;
361
      break;
362
    case 7:
363
      DecodeLow = DecoderTableSUBINSN_S232;
364
      DecodeHigh = DecoderTableSUBINSN_A32;
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      break;
366
    case 8:
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      DecodeLow = DecoderTableSUBINSN_S132;
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      DecodeHigh = DecoderTableSUBINSN_L132;
369
      break;
370
    case 9:
371
      DecodeLow = DecoderTableSUBINSN_S132;
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      DecodeHigh = DecoderTableSUBINSN_L232;
373
      break;
374
    case 10:
375
      DecodeLow = DecoderTableSUBINSN_S132;
376
      DecodeHigh = DecoderTableSUBINSN_S132;
377
      break;
378
    case 11:
379
      DecodeLow = DecoderTableSUBINSN_S232;
380
      DecodeHigh = DecoderTableSUBINSN_S132;
381
      break;
382
    case 12:
383
      DecodeLow = DecoderTableSUBINSN_S232;
384
      DecodeHigh = DecoderTableSUBINSN_L132;
385
      break;
386
    case 13:
387
      DecodeLow = DecoderTableSUBINSN_S232;
388
      DecodeHigh = DecoderTableSUBINSN_L232;
389
      break;
390
    case 14:
391
      DecodeLow = DecoderTableSUBINSN_S232;
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      DecodeHigh = DecoderTableSUBINSN_S232;
393
      break;
394
    }
395
    MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
396
    MCInst *MILow = getContext().createMCInst();
397
    MCInst *MIHigh = getContext().createMCInst();
398
    auto TmpExtender = CurrentExtender;
399
    CurrentExtender =
400
        nullptr; // constant extenders in duplex must always be in slot 1
401
    Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
402
                               this, STI);
403
    CurrentExtender = TmpExtender;
404
    if (Result != DecodeStatus::Success)
405
      return DecodeStatus::Fail;
406
    adjustDuplex(*MILow, getContext());
407
    Result = decodeInstruction(
408
        DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
409
    if (Result != DecodeStatus::Success)
410
      return DecodeStatus::Fail;
411
    adjustDuplex(*MIHigh, getContext());
412
    MCOperand OPLow = MCOperand::createInst(MILow);
413
    MCOperand OPHigh = MCOperand::createInst(MIHigh);
414
    MI.addOperand(OPLow);
415
    MI.addOperand(OPHigh);
416
    Complete = true;
417
  } else {
418
    if ((Instruction & HexagonII::INST_PARSE_MASK) ==
419
        HexagonII::INST_PARSE_PACKET_END)
420
      Complete = true;
421

422
    if (CurrentExtender != nullptr)
423
      Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
424
                                 Address, this, STI);
425

426
    if (Result != MCDisassembler::Success)
427
      Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
428
                                 STI);
429

430
    if (Result != MCDisassembler::Success &&
431
        STI.hasFeature(Hexagon::ExtensionHVX))
432
      Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
433
                                 Address, this, STI);
434

435
  }
436

437
  switch (MI.getOpcode()) {
438
  case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
439
  case Hexagon::J4_cmpeqn1_f_jumpnv_t:
440
  case Hexagon::J4_cmpeqn1_fp0_jump_nt:
441
  case Hexagon::J4_cmpeqn1_fp0_jump_t:
442
  case Hexagon::J4_cmpeqn1_fp1_jump_nt:
443
  case Hexagon::J4_cmpeqn1_fp1_jump_t:
444
  case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
445
  case Hexagon::J4_cmpeqn1_t_jumpnv_t:
446
  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
447
  case Hexagon::J4_cmpeqn1_tp0_jump_t:
448
  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
449
  case Hexagon::J4_cmpeqn1_tp1_jump_t:
450
  case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
451
  case Hexagon::J4_cmpgtn1_f_jumpnv_t:
452
  case Hexagon::J4_cmpgtn1_fp0_jump_nt:
453
  case Hexagon::J4_cmpgtn1_fp0_jump_t:
454
  case Hexagon::J4_cmpgtn1_fp1_jump_nt:
455
  case Hexagon::J4_cmpgtn1_fp1_jump_t:
456
  case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
457
  case Hexagon::J4_cmpgtn1_t_jumpnv_t:
458
  case Hexagon::J4_cmpgtn1_tp0_jump_nt:
459
  case Hexagon::J4_cmpgtn1_tp0_jump_t:
460
  case Hexagon::J4_cmpgtn1_tp1_jump_nt:
461
  case Hexagon::J4_cmpgtn1_tp1_jump_t:
462
    MI.insert(MI.begin() + 1,
463
              MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
464
    break;
465
  default:
466
    break;
467
  }
468

469
  if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
470
    unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
471
    MCOperand &MCO = MI.getOperand(OpIndex);
472
    assert(MCO.isReg() && "New value consumers must be registers");
473
    unsigned Register =
474
        getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
475
    if ((Register & 0x6) == 0)
476
      // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
477
      return MCDisassembler::Fail;
478
    unsigned Lookback = (Register & 0x6) >> 1;
479
    unsigned Offset = 1;
480
    bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
481
    bool PrevVector = false;
482
    auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
483
    auto i = Instructions.end() - 1;
484
    for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
485
      if (i == n)
486
        // Couldn't find producer
487
        return MCDisassembler::Fail;
488
      bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
489
      if (Vector && !CurrentVector)
490
        // Skip scalars when calculating distances for vectors
491
        ++Lookback;
492
      if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
493
        ++Lookback;
494
      PrevVector = CurrentVector;
495
      if (Offset == Lookback)
496
        break;
497
    }
498
    auto const &Inst = *i->getInst();
499
    bool SubregBit = (Register & 0x1) != 0;
500
    if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
501
      // If subreg bit is set we're selecting the second produced newvalue
502
      unsigned Producer = SubregBit ?
503
          HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
504
          HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
505
      assert(Producer != Hexagon::NoRegister);
506
      MCO.setReg(Producer);
507
    } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
508
      unsigned Producer =
509
          HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
510

511
      if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
512
        const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
513
        const unsigned ProdPairIndex =
514
            Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
515
        if (Rev)
516
          SubregBit = !SubregBit;
517
        Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
518
      } else if (SubregBit)
519
        // Hexagon PRM 10.11 New-value operands
520
        // Nt[0] is reserved and should always be encoded as zero.
521
        return MCDisassembler::Fail;
522
      assert(Producer != Hexagon::NoRegister);
523
      MCO.setReg(Producer);
524
    } else
525
      return MCDisassembler::Fail;
526
  }
527

528
  if (CurrentExtender != nullptr) {
529
    MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
530
                             ? *MI.getOperand(1).getInst()
531
                             : MI;
532
    if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
533
        !HexagonMCInstrInfo::isExtended(*MCII, Inst))
534
      return MCDisassembler::Fail;
535
  }
536
  return Result;
537
}
538

539
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
540
                                        ArrayRef<MCPhysReg> Table) {
541
  if (RegNo < Table.size()) {
542
    Inst.addOperand(MCOperand::createReg(Table[RegNo]));
543
    return MCDisassembler::Success;
544
  }
545

546
  return MCDisassembler::Fail;
547
}
548

549
static DecodeStatus
550
DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
551
                               const MCDisassembler *Decoder) {
552
  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
553
}
554

555
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
556
                                               uint64_t Address,
557
                                               const MCDisassembler *Decoder) {
558
  static const MCPhysReg IntRegDecoderTable[] = {
559
      Hexagon::R0,  Hexagon::R1,  Hexagon::R2,  Hexagon::R3,  Hexagon::R4,
560
      Hexagon::R5,  Hexagon::R6,  Hexagon::R7,  Hexagon::R8,  Hexagon::R9,
561
      Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
562
      Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
563
      Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
564
      Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
565
      Hexagon::R30, Hexagon::R31};
566

567
  return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
568
}
569

570
static DecodeStatus
571
DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
572
                                  uint64_t Address,
573
                                  const MCDisassembler *Decoder) {
574
  static const MCPhysReg GeneralSubRegDecoderTable[] = {
575
      Hexagon::R0,  Hexagon::R1,  Hexagon::R2,  Hexagon::R3,
576
      Hexagon::R4,  Hexagon::R5,  Hexagon::R6,  Hexagon::R7,
577
      Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
578
      Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
579
  };
580

581
  return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
582
}
583

584
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
585
                                             uint64_t /*Address*/,
586
                                             const MCDisassembler *Decoder) {
587
  static const MCPhysReg HvxVRDecoderTable[] = {
588
      Hexagon::V0,  Hexagon::V1,  Hexagon::V2,  Hexagon::V3,  Hexagon::V4,
589
      Hexagon::V5,  Hexagon::V6,  Hexagon::V7,  Hexagon::V8,  Hexagon::V9,
590
      Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
591
      Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
592
      Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
593
      Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
594
      Hexagon::V30, Hexagon::V31};
595

596
  return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
597
}
598

599
static DecodeStatus
600
DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
601
                              uint64_t /*Address*/,
602
                              const MCDisassembler *Decoder) {
603
  static const MCPhysReg DoubleRegDecoderTable[] = {
604
      Hexagon::D0,  Hexagon::D1,  Hexagon::D2,  Hexagon::D3,
605
      Hexagon::D4,  Hexagon::D5,  Hexagon::D6,  Hexagon::D7,
606
      Hexagon::D8,  Hexagon::D9,  Hexagon::D10, Hexagon::D11,
607
      Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
608

609
  return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
610
}
611

612
static DecodeStatus
613
DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
614
                                         uint64_t /*Address*/,
615
                                         const MCDisassembler *Decoder) {
616
  static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
617
      Hexagon::D0, Hexagon::D1, Hexagon::D2,  Hexagon::D3,
618
      Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
619

620
  return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
621
}
622

623
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
624
                                             uint64_t /*Address*/,
625
                                             const MCDisassembler *Decoder) {
626
  static const MCPhysReg HvxWRDecoderTable[] = {
627
      Hexagon::W0,   Hexagon::WR0,  Hexagon::W1,   Hexagon::WR1,  Hexagon::W2,
628
      Hexagon::WR2,  Hexagon::W3,   Hexagon::WR3,  Hexagon::W4,   Hexagon::WR4,
629
      Hexagon::W5,   Hexagon::WR5,  Hexagon::W6,   Hexagon::WR6,  Hexagon::W7,
630
      Hexagon::WR7,  Hexagon::W8,   Hexagon::WR8,  Hexagon::W9,   Hexagon::WR9,
631
      Hexagon::W10,  Hexagon::WR10, Hexagon::W11,  Hexagon::WR11, Hexagon::W12,
632
      Hexagon::WR12, Hexagon::W13,  Hexagon::WR13, Hexagon::W14,  Hexagon::WR14,
633
      Hexagon::W15,  Hexagon::WR15,
634
  };
635

636
  return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
637
}
638

639
LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
640
    static DecodeStatus
641
    DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
642
                              uint64_t /*Address*/,
643
                              const MCDisassembler *Decoder) {
644
  static const MCPhysReg HvxVQRDecoderTable[] = {
645
      Hexagon::VQ0,  Hexagon::VQ1,  Hexagon::VQ2,  Hexagon::VQ3,
646
      Hexagon::VQ4,  Hexagon::VQ5,  Hexagon::VQ6,  Hexagon::VQ7};
647

648
  return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
649
}
650

651
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
652
                                                uint64_t /*Address*/,
653
                                                const MCDisassembler *Decoder) {
654
  static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
655
                                                  Hexagon::P2, Hexagon::P3};
656

657
  return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
658
}
659

660
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
661
                                             uint64_t /*Address*/,
662
                                             const MCDisassembler *Decoder) {
663
  static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
664
                                                Hexagon::Q2, Hexagon::Q3};
665

666
  return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
667
}
668

669
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
670
                                               uint64_t /*Address*/,
671
                                               const MCDisassembler *Decoder) {
672
  using namespace Hexagon;
673

674
  static const MCPhysReg CtrlRegDecoderTable[] = {
675
    /*  0 */  SA0,        LC0,        SA1,        LC1,
676
    /*  4 */  P3_0,       C5,         M0,         M1,
677
    /*  8 */  USR,        PC,         UGP,        GP,
678
    /* 12 */  CS0,        CS1,        UPCYCLELO,  UPCYCLEHI,
679
    /* 16 */  FRAMELIMIT, FRAMEKEY,   PKTCOUNTLO, PKTCOUNTHI,
680
    /* 20 */  0,          0,          0,          0,
681
    /* 24 */  0,          0,          0,          0,
682
    /* 28 */  0,          0,          UTIMERLO,   UTIMERHI
683
  };
684

685
  if (RegNo >= std::size(CtrlRegDecoderTable))
686
    return MCDisassembler::Fail;
687

688
  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
689
  if (CtrlRegDecoderTable[RegNo] == NoRegister)
690
    return MCDisassembler::Fail;
691

692
  unsigned Register = CtrlRegDecoderTable[RegNo];
693
  Inst.addOperand(MCOperand::createReg(Register));
694
  return MCDisassembler::Success;
695
}
696

697
static DecodeStatus
698
DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
699
                             const MCDisassembler *Decoder) {
700
  using namespace Hexagon;
701

702
  static const MCPhysReg CtrlReg64DecoderTable[] = {
703
    /*  0 */  C1_0,       0,          C3_2,       0,
704
    /*  4 */  C5_4,       0,          C7_6,       0,
705
    /*  8 */  C9_8,       0,          C11_10,     0,
706
    /* 12 */  CS,         0,          UPCYCLE,    0,
707
    /* 16 */  C17_16,     0,          PKTCOUNT,   0,
708
    /* 20 */  0,          0,          0,          0,
709
    /* 24 */  0,          0,          0,          0,
710
    /* 28 */  0,          0,          UTIMER,     0
711
  };
712

713
  if (RegNo >= std::size(CtrlReg64DecoderTable))
714
    return MCDisassembler::Fail;
715

716
  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
717
  if (CtrlReg64DecoderTable[RegNo] == NoRegister)
718
    return MCDisassembler::Fail;
719

720
  unsigned Register = CtrlReg64DecoderTable[RegNo];
721
  Inst.addOperand(MCOperand::createReg(Register));
722
  return MCDisassembler::Success;
723
}
724

725
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
726
                                               uint64_t /*Address*/,
727
                                               const MCDisassembler *Decoder) {
728
  unsigned Register = 0;
729
  switch (RegNo) {
730
  case 0:
731
    Register = Hexagon::M0;
732
    break;
733
  case 1:
734
    Register = Hexagon::M1;
735
    break;
736
  default:
737
    return MCDisassembler::Fail;
738
  }
739
  Inst.addOperand(MCOperand::createReg(Register));
740
  return MCDisassembler::Success;
741
}
742

743
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
744
                                       uint64_t /*Address*/,
745
                                       const MCDisassembler *Decoder) {
746
  HexagonDisassembler const &Disassembler = disassembler(Decoder);
747
  int64_t FullValue = fullValue(Disassembler, MI, tmp);
748
  assert(FullValue >= 0 && "Negative in unsigned decoder");
749
  HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
750
  return MCDisassembler::Success;
751
}
752

753
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
754
                                    uint64_t /*Address*/,
755
                                    const MCDisassembler *Decoder) {
756
  HexagonDisassembler const &Disassembler = disassembler(Decoder);
757
  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
758
  tmp = SignExtend64(tmp, Bits);
759
  signedDecoder<32>(MI, tmp, Decoder);
760
  return MCDisassembler::Success;
761
}
762

763
// custom decoder for various jump/call immediates
764
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
765
                                    const MCDisassembler *Decoder) {
766
  HexagonDisassembler const &Disassembler = disassembler(Decoder);
767
  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
768
  // r13_2 is not extendable, so if there are no extent bits, it's r13_2
769
  if (Bits == 0)
770
    Bits = 15;
771
  uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
772
  uint32_t Extended = FullValue + Address;
773
  if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
774
                                             4))
775
    HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
776
  return MCDisassembler::Success;
777
}
778

779
static const uint16_t SysRegDecoderTable[] = {
780
    Hexagon::SGP0,       Hexagon::SGP1,      Hexagon::STID,
781
    Hexagon::ELR,        Hexagon::BADVA0,    Hexagon::BADVA1,
782
    Hexagon::SSR,        Hexagon::CCR,       Hexagon::HTID,
783
    Hexagon::BADVA,      Hexagon::IMASK,     Hexagon::S11,
784
    Hexagon::S12,        Hexagon::S13,       Hexagon::S14,
785
    Hexagon::S15,        Hexagon::EVB,       Hexagon::MODECTL,
786
    Hexagon::SYSCFG,     Hexagon::S19,       Hexagon::S20,
787
    Hexagon::VID,        Hexagon::S22,       Hexagon::S23,
788
    Hexagon::S24,        Hexagon::S25,       Hexagon::S26,
789
    Hexagon::CFGBASE,    Hexagon::DIAG,      Hexagon::REV,
790
    Hexagon::PCYCLELO,   Hexagon::PCYCLEHI,  Hexagon::ISDBST,
791
    Hexagon::ISDBCFG0,   Hexagon::ISDBCFG1,  Hexagon::S35,
792
    Hexagon::BRKPTPC0,   Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
793
    Hexagon::BRKPTCFG1,  Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
794
    Hexagon::ISDBEN,     Hexagon::ISDBGPR,   Hexagon::S44,
795
    Hexagon::S45,        Hexagon::S46,       Hexagon::S47,
796
    Hexagon::PMUCNT0,    Hexagon::PMUCNT1,   Hexagon::PMUCNT2,
797
    Hexagon::PMUCNT3,    Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
798
    Hexagon::S54,        Hexagon::S55,       Hexagon::S56,
799
    Hexagon::S57,        Hexagon::S58,       Hexagon::S59,
800
    Hexagon::S60,        Hexagon::S61,       Hexagon::S62,
801
    Hexagon::S63,        Hexagon::S64,       Hexagon::S65,
802
    Hexagon::S66,        Hexagon::S67,       Hexagon::S68,
803
    Hexagon::S69,        Hexagon::S70,       Hexagon::S71,
804
    Hexagon::S72,        Hexagon::S73,       Hexagon::S74,
805
    Hexagon::S75,        Hexagon::S76,       Hexagon::S77,
806
    Hexagon::S78,        Hexagon::S79,       Hexagon::S80,
807
};
808

809
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
810
                                               uint64_t /*Address*/,
811
                                               const MCDisassembler *Decoder) {
812
  if (RegNo >= std::size(SysRegDecoderTable))
813
    return MCDisassembler::Fail;
814

815
  if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
816
    return MCDisassembler::Fail;
817

818
  unsigned Register = SysRegDecoderTable[RegNo];
819
  Inst.addOperand(MCOperand::createReg(Register));
820
  return MCDisassembler::Success;
821
}
822

823
static const uint16_t SysReg64DecoderTable[] = {
824
    Hexagon::SGP1_0, Hexagon::S3_2,   Hexagon::S5_4,   Hexagon::S7_6,
825
    Hexagon::S9_8,   Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
826
    Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
827
    Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
828
    Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
829
    Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
830
    Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
831
    Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
832
    Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
833
    Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
834
};
835

836
static DecodeStatus
837
DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
838
                             const MCDisassembler *Decoder) {
839
  RegNo = RegNo >> 1;
840
  if (RegNo >= std::size(SysReg64DecoderTable))
841
    return MCDisassembler::Fail;
842

843
  if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
844
    return MCDisassembler::Fail;
845

846
  unsigned Register = SysReg64DecoderTable[RegNo];
847
  Inst.addOperand(MCOperand::createReg(Register));
848
  return MCDisassembler::Success;
849
}
850

851
static DecodeStatus
852
DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
853
                             const MCDisassembler *Decoder) {
854
  using namespace Hexagon;
855

856
  static const MCPhysReg GuestRegDecoderTable[] = {
857
    /*  0 */ GELR,      GSR,        GOSP,       G3,
858
    /*  4 */ G4,        G5,         G6,         G7,
859
    /*  8 */ G8,        G9,         G10,        G11,
860
    /* 12 */ G12,       G13,        G14,        G15,
861
    /* 16 */ GPMUCNT4,  GPMUCNT5,   GPMUCNT6,   GPMUCNT7,
862
    /* 20 */ G20,       G21,        G22,        G23,
863
    /* 24 */ GPCYCLELO, GPCYCLEHI,  GPMUCNT0,   GPMUCNT1,
864
    /* 28 */ GPMUCNT2,  GPMUCNT3,   G30,        G31
865
  };
866

867
  if (RegNo >= std::size(GuestRegDecoderTable))
868
    return MCDisassembler::Fail;
869
  if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
870
    return MCDisassembler::Fail;
871

872
  unsigned Register = GuestRegDecoderTable[RegNo];
873
  Inst.addOperand(MCOperand::createReg(Register));
874
  return MCDisassembler::Success;
875
}
876

877
static DecodeStatus
878
DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
879
                               uint64_t /*Address*/,
880
                               const MCDisassembler *Decoder) {
881
  using namespace Hexagon;
882

883
  static const MCPhysReg GuestReg64DecoderTable[] = {
884
    /*  0 */ G1_0,      0,          G3_2,       0,
885
    /*  4 */ G5_4,      0,          G7_6,       0,
886
    /*  8 */ G9_8,      0,          G11_10,     0,
887
    /* 12 */ G13_12,    0,          G15_14,     0,
888
    /* 16 */ G17_16,    0,          G19_18,     0,
889
    /* 20 */ G21_20,    0,          G23_22,     0,
890
    /* 24 */ G25_24,    0,          G27_26,     0,
891
    /* 28 */ G29_28,    0,          G31_30,     0
892
  };
893

894
  if (RegNo >= std::size(GuestReg64DecoderTable))
895
    return MCDisassembler::Fail;
896
  if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
897
    return MCDisassembler::Fail;
898

899
  unsigned Register = GuestReg64DecoderTable[RegNo];
900
  Inst.addOperand(MCOperand::createReg(Register));
901
  return MCDisassembler::Success;
902
}
903

904
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