Path: blob/main/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
35294 views
//===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//1//2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3// See https://llvm.org/LICENSE.txt for license information.4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5//6//===----------------------------------------------------------------------===//7//8// This file provides RISC-V specific target descriptions.9//10//===----------------------------------------------------------------------===//1112#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H13#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H1415#include "llvm/MC/MCTargetOptions.h"16#include "llvm/Support/DataTypes.h"17#include <memory>1819namespace llvm {20class MCAsmBackend;21class MCCodeEmitter;22class MCContext;23class MCInstrInfo;24class MCObjectTargetWriter;25class MCRegisterInfo;26class MCSubtargetInfo;27class Target;2829MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,30MCContext &Ctx);3132MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,33const MCRegisterInfo &MRI,34const MCTargetOptions &Options);3536std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,37bool Is64Bit);3839namespace RISCVVInversePseudosTable {4041struct PseudoInfo {42uint16_t Pseudo;43uint16_t BaseInstr;44uint8_t VLMul;45uint8_t SEW;46};4748#define GET_RISCVVInversePseudosTable_DECL49#include "RISCVGenSearchableTables.inc"5051} // namespace RISCVVInversePseudosTable52} // namespace llvm5354// Defines symbolic names for RISC-V registers.55#define GET_REGINFO_ENUM56#include "RISCVGenRegisterInfo.inc"5758// Defines symbolic names for RISC-V instructions.59#define GET_INSTRINFO_ENUM60#define GET_INSTRINFO_MC_HELPER_DECLS61#include "RISCVGenInstrInfo.inc"6263#define GET_SUBTARGETINFO_ENUM64#include "RISCVGenSubtargetInfo.inc"6566#endif676869