Path: blob/main/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
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//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//1//2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3// See https://llvm.org/LICENSE.txt for license information.4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5//6//===----------------------------------------------------------------------===//7//8// This file is part of the X86 Disassembler.9// It contains the public interface of the instruction decoder.10// Documentation for the disassembler can be found in X86Disassembler.h.11//12//===----------------------------------------------------------------------===//1314#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H15#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H1617#include "llvm/ADT/ArrayRef.h"18#include "llvm/Support/X86DisassemblerDecoderCommon.h"1920namespace llvm {21namespace X86Disassembler {22// Helper macros23#define bitFromOffset0(val) ((val) & 0x1)24#define bitFromOffset1(val) (((val) >> 1) & 0x1)25#define bitFromOffset2(val) (((val) >> 2) & 0x1)26#define bitFromOffset3(val) (((val) >> 3) & 0x1)27#define bitFromOffset4(val) (((val) >> 4) & 0x1)28#define bitFromOffset5(val) (((val) >> 5) & 0x1)29#define bitFromOffset6(val) (((val) >> 6) & 0x1)30#define bitFromOffset7(val) (((val) >> 7) & 0x1)31#define twoBitsFromOffset0(val) ((val) & 0x3)32#define twoBitsFromOffset6(val) (((val) >> 6) & 0x3)33#define threeBitsFromOffset0(val) ((val) & 0x7)34#define threeBitsFromOffset3(val) (((val) >> 3) & 0x7)35#define fourBitsFromOffset0(val) ((val) & 0xf)36#define fourBitsFromOffset3(val) (((val) >> 3) & 0xf)37#define fiveBitsFromOffset0(val) ((val) & 0x1f)38#define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1)39#define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1)40#define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1)41#define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1)42#define invertedBitFromOffset6(val) (((~(val)) >> 6) & 0x1)43#define invertedBitFromOffset7(val) (((~(val)) >> 7) & 0x1)44#define invertedFourBitsFromOffset3(val) (((~(val)) >> 3) & 0xf)45// MOD/RM46#define modFromModRM(modRM) twoBitsFromOffset6(modRM)47#define regFromModRM(modRM) threeBitsFromOffset3(modRM)48#define rmFromModRM(modRM) threeBitsFromOffset0(modRM)49// SIB50#define scaleFromSIB(sib) twoBitsFromOffset6(sib)51#define indexFromSIB(sib) threeBitsFromOffset3(sib)52#define baseFromSIB(sib) threeBitsFromOffset0(sib)53// REX54#define wFromREX(rex) bitFromOffset3(rex)55#define rFromREX(rex) bitFromOffset2(rex)56#define xFromREX(rex) bitFromOffset1(rex)57#define bFromREX(rex) bitFromOffset0(rex)58// REX259#define mFromREX2(rex2) bitFromOffset7(rex2)60#define r2FromREX2(rex2) bitFromOffset6(rex2)61#define x2FromREX2(rex2) bitFromOffset5(rex2)62#define b2FromREX2(rex2) bitFromOffset4(rex2)63#define wFromREX2(rex2) bitFromOffset3(rex2)64#define rFromREX2(rex2) bitFromOffset2(rex2)65#define xFromREX2(rex2) bitFromOffset1(rex2)66#define bFromREX2(rex2) bitFromOffset0(rex2)67// XOP68#define rFromXOP2of3(xop) invertedBitFromOffset7(xop)69#define xFromXOP2of3(xop) invertedBitFromOffset6(xop)70#define bFromXOP2of3(xop) invertedBitFromOffset5(xop)71#define mmmmmFromXOP2of3(xop) fiveBitsFromOffset0(xop)72#define wFromXOP3of3(xop) bitFromOffset7(xop)73#define vvvvFromXOP3of3(xop) invertedFourBitsFromOffset3(xop)74#define lFromXOP3of3(xop) bitFromOffset2(xop)75#define ppFromXOP3of3(xop) twoBitsFromOffset0(xop)76// VEX277#define rFromVEX2of2(vex) invertedBitFromOffset7(vex)78#define vvvvFromVEX2of2(vex) invertedFourBitsFromOffset3(vex)79#define lFromVEX2of2(vex) bitFromOffset2(vex)80#define ppFromVEX2of2(vex) twoBitsFromOffset0(vex)81// VEX382#define rFromVEX2of3(vex) invertedBitFromOffset7(vex)83#define xFromVEX2of3(vex) invertedBitFromOffset6(vex)84#define bFromVEX2of3(vex) invertedBitFromOffset5(vex)85#define mmmmmFromVEX2of3(vex) fiveBitsFromOffset0(vex)86#define wFromVEX3of3(vex) bitFromOffset7(vex)87#define vvvvFromVEX3of3(vex) invertedFourBitsFromOffset3(vex)88#define lFromVEX3of3(vex) bitFromOffset2(vex)89#define ppFromVEX3of3(vex) twoBitsFromOffset0(vex)90// EVEX91#define rFromEVEX2of4(evex) invertedBitFromOffset7(evex)92#define xFromEVEX2of4(evex) invertedBitFromOffset6(evex)93#define bFromEVEX2of4(evex) invertedBitFromOffset5(evex)94#define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex)95#define b2FromEVEX2of4(evex) bitFromOffset3(evex)96#define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex)97#define wFromEVEX3of4(evex) bitFromOffset7(evex)98#define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex)99#define x2FromEVEX3of4(evex) invertedBitFromOffset2(evex)100#define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex)101#define oszcFromEVEX3of4(evex) fourBitsFromOffset3(evex)102#define zFromEVEX4of4(evex) bitFromOffset7(evex)103#define l2FromEVEX4of4(evex) bitFromOffset6(evex)104#define lFromEVEX4of4(evex) bitFromOffset5(evex)105#define bFromEVEX4of4(evex) bitFromOffset4(evex)106#define v2FromEVEX4of4(evex) invertedBitFromOffset3(evex)107#define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex)108#define nfFromEVEX4of4(evex) bitFromOffset2(evex)109#define scFromEVEX4of4(evex) fourBitsFromOffset0(evex)110111// These enums represent Intel registers for use by the decoder.112#define REGS_8BIT \113ENTRY(AL) \114ENTRY(CL) \115ENTRY(DL) \116ENTRY(BL) \117ENTRY(AH) \118ENTRY(CH) \119ENTRY(DH) \120ENTRY(BH) \121ENTRY(R8B) \122ENTRY(R9B) \123ENTRY(R10B) \124ENTRY(R11B) \125ENTRY(R12B) \126ENTRY(R13B) \127ENTRY(R14B) \128ENTRY(R15B) \129ENTRY(R16B) \130ENTRY(R17B) \131ENTRY(R18B) \132ENTRY(R19B) \133ENTRY(R20B) \134ENTRY(R21B) \135ENTRY(R22B) \136ENTRY(R23B) \137ENTRY(R24B) \138ENTRY(R25B) \139ENTRY(R26B) \140ENTRY(R27B) \141ENTRY(R28B) \142ENTRY(R29B) \143ENTRY(R30B) \144ENTRY(R31B) \145ENTRY(SPL) \146ENTRY(BPL) \147ENTRY(SIL) \148ENTRY(DIL)149150#define EA_BASES_16BIT \151ENTRY(BX_SI) \152ENTRY(BX_DI) \153ENTRY(BP_SI) \154ENTRY(BP_DI) \155ENTRY(SI) \156ENTRY(DI) \157ENTRY(BP) \158ENTRY(BX) \159ENTRY(R8W) \160ENTRY(R9W) \161ENTRY(R10W) \162ENTRY(R11W) \163ENTRY(R12W) \164ENTRY(R13W) \165ENTRY(R14W) \166ENTRY(R15W) \167ENTRY(R16W) \168ENTRY(R17W) \169ENTRY(R18W) \170ENTRY(R19W) \171ENTRY(R20W) \172ENTRY(R21W) \173ENTRY(R22W) \174ENTRY(R23W) \175ENTRY(R24W) \176ENTRY(R25W) \177ENTRY(R26W) \178ENTRY(R27W) \179ENTRY(R28W) \180ENTRY(R29W) \181ENTRY(R30W) \182ENTRY(R31W)183184#define REGS_16BIT \185ENTRY(AX) \186ENTRY(CX) \187ENTRY(DX) \188ENTRY(BX) \189ENTRY(SP) \190ENTRY(BP) \191ENTRY(SI) \192ENTRY(DI) \193ENTRY(R8W) \194ENTRY(R9W) \195ENTRY(R10W) \196ENTRY(R11W) \197ENTRY(R12W) \198ENTRY(R13W) \199ENTRY(R14W) \200ENTRY(R15W) \201ENTRY(R16W) \202ENTRY(R17W) \203ENTRY(R18W) \204ENTRY(R19W) \205ENTRY(R20W) \206ENTRY(R21W) \207ENTRY(R22W) \208ENTRY(R23W) \209ENTRY(R24W) \210ENTRY(R25W) \211ENTRY(R26W) \212ENTRY(R27W) \213ENTRY(R28W) \214ENTRY(R29W) \215ENTRY(R30W) \216ENTRY(R31W)217218#define EA_BASES_32BIT \219ENTRY(EAX) \220ENTRY(ECX) \221ENTRY(EDX) \222ENTRY(EBX) \223ENTRY(sib) \224ENTRY(EBP) \225ENTRY(ESI) \226ENTRY(EDI) \227ENTRY(R8D) \228ENTRY(R9D) \229ENTRY(R10D) \230ENTRY(R11D) \231ENTRY(R12D) \232ENTRY(R13D) \233ENTRY(R14D) \234ENTRY(R15D) \235ENTRY(R16D) \236ENTRY(R17D) \237ENTRY(R18D) \238ENTRY(R19D) \239ENTRY(R20D) \240ENTRY(R21D) \241ENTRY(R22D) \242ENTRY(R23D) \243ENTRY(R24D) \244ENTRY(R25D) \245ENTRY(R26D) \246ENTRY(R27D) \247ENTRY(R28D) \248ENTRY(R29D) \249ENTRY(R30D) \250ENTRY(R31D)251252#define REGS_32BIT \253ENTRY(EAX) \254ENTRY(ECX) \255ENTRY(EDX) \256ENTRY(EBX) \257ENTRY(ESP) \258ENTRY(EBP) \259ENTRY(ESI) \260ENTRY(EDI) \261ENTRY(R8D) \262ENTRY(R9D) \263ENTRY(R10D) \264ENTRY(R11D) \265ENTRY(R12D) \266ENTRY(R13D) \267ENTRY(R14D) \268ENTRY(R15D) \269ENTRY(R16D) \270ENTRY(R17D) \271ENTRY(R18D) \272ENTRY(R19D) \273ENTRY(R20D) \274ENTRY(R21D) \275ENTRY(R22D) \276ENTRY(R23D) \277ENTRY(R24D) \278ENTRY(R25D) \279ENTRY(R26D) \280ENTRY(R27D) \281ENTRY(R28D) \282ENTRY(R29D) \283ENTRY(R30D) \284ENTRY(R31D)285286#define EA_BASES_64BIT \287ENTRY(RAX) \288ENTRY(RCX) \289ENTRY(RDX) \290ENTRY(RBX) \291ENTRY(sib64) \292ENTRY(RBP) \293ENTRY(RSI) \294ENTRY(RDI) \295ENTRY(R8) \296ENTRY(R9) \297ENTRY(R10) \298ENTRY(R11) \299ENTRY(R12) \300ENTRY(R13) \301ENTRY(R14) \302ENTRY(R15) \303ENTRY(R16) \304ENTRY(R17) \305ENTRY(R18) \306ENTRY(R19) \307ENTRY(R20) \308ENTRY(R21) \309ENTRY(R22) \310ENTRY(R23) \311ENTRY(R24) \312ENTRY(R25) \313ENTRY(R26) \314ENTRY(R27) \315ENTRY(R28) \316ENTRY(R29) \317ENTRY(R30) \318ENTRY(R31)319320#define REGS_64BIT \321ENTRY(RAX) \322ENTRY(RCX) \323ENTRY(RDX) \324ENTRY(RBX) \325ENTRY(RSP) \326ENTRY(RBP) \327ENTRY(RSI) \328ENTRY(RDI) \329ENTRY(R8) \330ENTRY(R9) \331ENTRY(R10) \332ENTRY(R11) \333ENTRY(R12) \334ENTRY(R13) \335ENTRY(R14) \336ENTRY(R15) \337ENTRY(R16) \338ENTRY(R17) \339ENTRY(R18) \340ENTRY(R19) \341ENTRY(R20) \342ENTRY(R21) \343ENTRY(R22) \344ENTRY(R23) \345ENTRY(R24) \346ENTRY(R25) \347ENTRY(R26) \348ENTRY(R27) \349ENTRY(R28) \350ENTRY(R29) \351ENTRY(R30) \352ENTRY(R31)353354#define REGS_MMX \355ENTRY(MM0) \356ENTRY(MM1) \357ENTRY(MM2) \358ENTRY(MM3) \359ENTRY(MM4) \360ENTRY(MM5) \361ENTRY(MM6) \362ENTRY(MM7)363364#define REGS_XMM \365ENTRY(XMM0) \366ENTRY(XMM1) \367ENTRY(XMM2) \368ENTRY(XMM3) \369ENTRY(XMM4) \370ENTRY(XMM5) \371ENTRY(XMM6) \372ENTRY(XMM7) \373ENTRY(XMM8) \374ENTRY(XMM9) \375ENTRY(XMM10) \376ENTRY(XMM11) \377ENTRY(XMM12) \378ENTRY(XMM13) \379ENTRY(XMM14) \380ENTRY(XMM15) \381ENTRY(XMM16) \382ENTRY(XMM17) \383ENTRY(XMM18) \384ENTRY(XMM19) \385ENTRY(XMM20) \386ENTRY(XMM21) \387ENTRY(XMM22) \388ENTRY(XMM23) \389ENTRY(XMM24) \390ENTRY(XMM25) \391ENTRY(XMM26) \392ENTRY(XMM27) \393ENTRY(XMM28) \394ENTRY(XMM29) \395ENTRY(XMM30) \396ENTRY(XMM31)397398#define REGS_YMM \399ENTRY(YMM0) \400ENTRY(YMM1) \401ENTRY(YMM2) \402ENTRY(YMM3) \403ENTRY(YMM4) \404ENTRY(YMM5) \405ENTRY(YMM6) \406ENTRY(YMM7) \407ENTRY(YMM8) \408ENTRY(YMM9) \409ENTRY(YMM10) \410ENTRY(YMM11) \411ENTRY(YMM12) \412ENTRY(YMM13) \413ENTRY(YMM14) \414ENTRY(YMM15) \415ENTRY(YMM16) \416ENTRY(YMM17) \417ENTRY(YMM18) \418ENTRY(YMM19) \419ENTRY(YMM20) \420ENTRY(YMM21) \421ENTRY(YMM22) \422ENTRY(YMM23) \423ENTRY(YMM24) \424ENTRY(YMM25) \425ENTRY(YMM26) \426ENTRY(YMM27) \427ENTRY(YMM28) \428ENTRY(YMM29) \429ENTRY(YMM30) \430ENTRY(YMM31)431432#define REGS_ZMM \433ENTRY(ZMM0) \434ENTRY(ZMM1) \435ENTRY(ZMM2) \436ENTRY(ZMM3) \437ENTRY(ZMM4) \438ENTRY(ZMM5) \439ENTRY(ZMM6) \440ENTRY(ZMM7) \441ENTRY(ZMM8) \442ENTRY(ZMM9) \443ENTRY(ZMM10) \444ENTRY(ZMM11) \445ENTRY(ZMM12) \446ENTRY(ZMM13) \447ENTRY(ZMM14) \448ENTRY(ZMM15) \449ENTRY(ZMM16) \450ENTRY(ZMM17) \451ENTRY(ZMM18) \452ENTRY(ZMM19) \453ENTRY(ZMM20) \454ENTRY(ZMM21) \455ENTRY(ZMM22) \456ENTRY(ZMM23) \457ENTRY(ZMM24) \458ENTRY(ZMM25) \459ENTRY(ZMM26) \460ENTRY(ZMM27) \461ENTRY(ZMM28) \462ENTRY(ZMM29) \463ENTRY(ZMM30) \464ENTRY(ZMM31)465466#define REGS_MASKS \467ENTRY(K0) \468ENTRY(K1) \469ENTRY(K2) \470ENTRY(K3) \471ENTRY(K4) \472ENTRY(K5) \473ENTRY(K6) \474ENTRY(K7)475476#define REGS_MASK_PAIRS \477ENTRY(K0_K1) \478ENTRY(K2_K3) \479ENTRY(K4_K5) \480ENTRY(K6_K7)481482#define REGS_SEGMENT \483ENTRY(ES) \484ENTRY(CS) \485ENTRY(SS) \486ENTRY(DS) \487ENTRY(FS) \488ENTRY(GS)489490#define REGS_DEBUG \491ENTRY(DR0) \492ENTRY(DR1) \493ENTRY(DR2) \494ENTRY(DR3) \495ENTRY(DR4) \496ENTRY(DR5) \497ENTRY(DR6) \498ENTRY(DR7) \499ENTRY(DR8) \500ENTRY(DR9) \501ENTRY(DR10) \502ENTRY(DR11) \503ENTRY(DR12) \504ENTRY(DR13) \505ENTRY(DR14) \506ENTRY(DR15)507508#define REGS_CONTROL \509ENTRY(CR0) \510ENTRY(CR1) \511ENTRY(CR2) \512ENTRY(CR3) \513ENTRY(CR4) \514ENTRY(CR5) \515ENTRY(CR6) \516ENTRY(CR7) \517ENTRY(CR8) \518ENTRY(CR9) \519ENTRY(CR10) \520ENTRY(CR11) \521ENTRY(CR12) \522ENTRY(CR13) \523ENTRY(CR14) \524ENTRY(CR15)525526#undef REGS_TMM527#define REGS_TMM \528ENTRY(TMM0) \529ENTRY(TMM1) \530ENTRY(TMM2) \531ENTRY(TMM3) \532ENTRY(TMM4) \533ENTRY(TMM5) \534ENTRY(TMM6) \535ENTRY(TMM7)536537#define ALL_EA_BASES \538EA_BASES_16BIT \539EA_BASES_32BIT \540EA_BASES_64BIT541542#define ALL_SIB_BASES \543REGS_32BIT \544REGS_64BIT545546#define ALL_REGS \547REGS_8BIT \548REGS_16BIT \549REGS_32BIT \550REGS_64BIT \551REGS_MMX \552REGS_XMM \553REGS_YMM \554REGS_ZMM \555REGS_MASKS \556REGS_MASK_PAIRS \557REGS_SEGMENT \558REGS_DEBUG \559REGS_CONTROL \560REGS_TMM \561ENTRY(RIP)562563/// All possible values of the base field for effective-address564/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.565/// We distinguish between bases (EA_BASE_*) and registers that just happen566/// to be referred to when Mod == 0b11 (EA_REG_*).567enum EABase {568// clang-format off569EA_BASE_NONE,570#define ENTRY(x) EA_BASE_##x,571ALL_EA_BASES572#undef ENTRY573#define ENTRY(x) EA_REG_##x,574ALL_REGS575#undef ENTRY576EA_max577// clang-format on578};579580/// All possible values of the SIB index field.581/// borrows entries from ALL_EA_BASES with the special case that582/// sib is synonymous with NONE.583/// Vector SIB: index can be XMM or YMM.584enum SIBIndex {585// clang-format off586SIB_INDEX_NONE,587#define ENTRY(x) SIB_INDEX_##x,588ALL_EA_BASES589REGS_XMM590REGS_YMM591REGS_ZMM592#undef ENTRY593SIB_INDEX_max594// clang-format on595};596597/// All possible values of the SIB base field.598enum SIBBase {599// clang-format off600SIB_BASE_NONE,601#define ENTRY(x) SIB_BASE_##x,602ALL_SIB_BASES603#undef ENTRY604SIB_BASE_max605// clang-format on606};607608/// Possible displacement types for effective-address computations.609enum EADisplacement { EA_DISP_NONE, EA_DISP_8, EA_DISP_16, EA_DISP_32 };610611/// All possible values of the reg field in the ModR/M byte.612// clang-format off613enum Reg {614#define ENTRY(x) MODRM_REG_##x,615ALL_REGS616#undef ENTRY617MODRM_REG_max618};619// clang-format on620621/// All possible segment overrides.622enum SegmentOverride {623SEG_OVERRIDE_NONE,624SEG_OVERRIDE_CS,625SEG_OVERRIDE_SS,626SEG_OVERRIDE_DS,627SEG_OVERRIDE_ES,628SEG_OVERRIDE_FS,629SEG_OVERRIDE_GS,630SEG_OVERRIDE_max631};632633/// Possible values for the VEX.m-mmmm field634enum VEXLeadingOpcodeByte {635VEX_LOB_0F = 0x1,636VEX_LOB_0F38 = 0x2,637VEX_LOB_0F3A = 0x3,638VEX_LOB_MAP4 = 0x4,639VEX_LOB_MAP5 = 0x5,640VEX_LOB_MAP6 = 0x6,641VEX_LOB_MAP7 = 0x7642};643644enum XOPMapSelect {645XOP_MAP_SELECT_8 = 0x8,646XOP_MAP_SELECT_9 = 0x9,647XOP_MAP_SELECT_A = 0xA648};649650/// Possible values for the VEX.pp/EVEX.pp field651enum VEXPrefixCode {652VEX_PREFIX_NONE = 0x0,653VEX_PREFIX_66 = 0x1,654VEX_PREFIX_F3 = 0x2,655VEX_PREFIX_F2 = 0x3656};657658enum VectorExtensionType {659TYPE_NO_VEX_XOP = 0x0,660TYPE_VEX_2B = 0x1,661TYPE_VEX_3B = 0x2,662TYPE_EVEX = 0x3,663TYPE_XOP = 0x4664};665666/// The specification for how to extract and interpret a full instruction and667/// its operands.668struct InstructionSpecifier {669uint16_t operands;670};671672/// The x86 internal instruction, which is produced by the decoder.673struct InternalInstruction {674// Opaque value passed to the reader675llvm::ArrayRef<uint8_t> bytes;676// The address of the next byte to read via the reader677uint64_t readerCursor;678679// General instruction information680681// The mode to disassemble for (64-bit, protected, real)682DisassemblerMode mode;683// The start of the instruction, usable with the reader684uint64_t startLocation;685// The length of the instruction, in bytes686size_t length;687688// Prefix state689690// The possible mandatory prefix691uint8_t mandatoryPrefix;692// The value of the vector extension prefix(EVEX/VEX/XOP), if present693uint8_t vectorExtensionPrefix[4];694// The type of the vector extension prefix695VectorExtensionType vectorExtensionType;696// The value of the REX2 prefix, if present697uint8_t rex2ExtensionPrefix[2];698// The value of the REX prefix, if present699uint8_t rexPrefix;700// The segment override type701SegmentOverride segmentOverride;702// 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease703bool xAcquireRelease;704705// Address-size override706bool hasAdSize;707// Operand-size override708bool hasOpSize;709// Lock prefix710bool hasLockPrefix;711// The repeat prefix if any712uint8_t repeatPrefix;713714// Sizes of various critical pieces of data, in bytes715uint8_t registerSize;716uint8_t addressSize;717uint8_t displacementSize;718uint8_t immediateSize;719720// Offsets from the start of the instruction to the pieces of data, which is721// needed to find relocation entries for adding symbolic operands.722uint8_t displacementOffset;723uint8_t immediateOffset;724725// opcode state726727// The last byte of the opcode, not counting any ModR/M extension728uint8_t opcode;729730// decode state731732// The type of opcode, used for indexing into the array of decode tables733OpcodeType opcodeType;734// The instruction ID, extracted from the decode table735uint16_t instructionID;736// The specifier for the instruction, from the instruction info table737const InstructionSpecifier *spec;738739// state for additional bytes, consumed during operand decode. Pattern:740// consumed___ indicates that the byte was already consumed and does not741// need to be consumed again.742743// The VEX.vvvv field, which contains a third register operand for some AVX744// instructions.745Reg vvvv;746747// The writemask for AVX-512 instructions which is contained in EVEX.aaa748Reg writemask;749750// The ModR/M byte, which contains most register operands and some portion of751// all memory operands.752bool consumedModRM;753uint8_t modRM;754755// The SIB byte, used for more complex 32- or 64-bit memory operands756uint8_t sib;757758// The displacement, used for memory operands759int32_t displacement;760761// Immediates. There can be three in some cases762uint8_t numImmediatesConsumed;763uint8_t numImmediatesTranslated;764uint64_t immediates[3];765766// A register or immediate operand encoded into the opcode767Reg opcodeRegister;768769// Portions of the ModR/M byte770771// These fields determine the allowable values for the ModR/M fields, which772// depend on operand and address widths.773EABase eaRegBase;774Reg regBase;775776// The Mod and R/M fields can encode a base for an effective address, or a777// register. These are separated into two fields here.778EABase eaBase;779EADisplacement eaDisplacement;780// The reg field always encodes a register781Reg reg;782783// SIB state784SIBIndex sibIndexBase;785SIBIndex sibIndex;786uint8_t sibScale;787SIBBase sibBase;788789// Embedded rounding control.790uint8_t RC;791792ArrayRef<OperandSpecifier> operands;793};794795} // namespace X86Disassembler796} // namespace llvm797798#endif799800801