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GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
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//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains the public interface of the instruction decoder.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
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#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Support/X86DisassemblerDecoderCommon.h"
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namespace llvm {
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namespace X86Disassembler {
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// Helper macros
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#define bitFromOffset0(val) ((val) & 0x1)
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#define bitFromOffset1(val) (((val) >> 1) & 0x1)
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#define bitFromOffset2(val) (((val) >> 2) & 0x1)
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#define bitFromOffset3(val) (((val) >> 3) & 0x1)
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#define bitFromOffset4(val) (((val) >> 4) & 0x1)
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#define bitFromOffset5(val) (((val) >> 5) & 0x1)
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#define bitFromOffset6(val) (((val) >> 6) & 0x1)
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#define bitFromOffset7(val) (((val) >> 7) & 0x1)
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#define twoBitsFromOffset0(val) ((val) & 0x3)
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#define twoBitsFromOffset6(val) (((val) >> 6) & 0x3)
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#define threeBitsFromOffset0(val) ((val) & 0x7)
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#define threeBitsFromOffset3(val) (((val) >> 3) & 0x7)
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#define fourBitsFromOffset0(val) ((val) & 0xf)
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#define fourBitsFromOffset3(val) (((val) >> 3) & 0xf)
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#define fiveBitsFromOffset0(val) ((val) & 0x1f)
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#define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1)
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#define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1)
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#define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1)
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#define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1)
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#define invertedBitFromOffset6(val) (((~(val)) >> 6) & 0x1)
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#define invertedBitFromOffset7(val) (((~(val)) >> 7) & 0x1)
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#define invertedFourBitsFromOffset3(val) (((~(val)) >> 3) & 0xf)
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// MOD/RM
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#define modFromModRM(modRM) twoBitsFromOffset6(modRM)
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#define regFromModRM(modRM) threeBitsFromOffset3(modRM)
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#define rmFromModRM(modRM) threeBitsFromOffset0(modRM)
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// SIB
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#define scaleFromSIB(sib) twoBitsFromOffset6(sib)
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#define indexFromSIB(sib) threeBitsFromOffset3(sib)
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#define baseFromSIB(sib) threeBitsFromOffset0(sib)
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// REX
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#define wFromREX(rex) bitFromOffset3(rex)
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#define rFromREX(rex) bitFromOffset2(rex)
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#define xFromREX(rex) bitFromOffset1(rex)
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#define bFromREX(rex) bitFromOffset0(rex)
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// REX2
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#define mFromREX2(rex2) bitFromOffset7(rex2)
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#define r2FromREX2(rex2) bitFromOffset6(rex2)
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#define x2FromREX2(rex2) bitFromOffset5(rex2)
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#define b2FromREX2(rex2) bitFromOffset4(rex2)
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#define wFromREX2(rex2) bitFromOffset3(rex2)
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#define rFromREX2(rex2) bitFromOffset2(rex2)
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#define xFromREX2(rex2) bitFromOffset1(rex2)
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#define bFromREX2(rex2) bitFromOffset0(rex2)
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// XOP
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#define rFromXOP2of3(xop) invertedBitFromOffset7(xop)
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#define xFromXOP2of3(xop) invertedBitFromOffset6(xop)
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#define bFromXOP2of3(xop) invertedBitFromOffset5(xop)
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#define mmmmmFromXOP2of3(xop) fiveBitsFromOffset0(xop)
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#define wFromXOP3of3(xop) bitFromOffset7(xop)
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#define vvvvFromXOP3of3(xop) invertedFourBitsFromOffset3(xop)
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#define lFromXOP3of3(xop) bitFromOffset2(xop)
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#define ppFromXOP3of3(xop) twoBitsFromOffset0(xop)
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// VEX2
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#define rFromVEX2of2(vex) invertedBitFromOffset7(vex)
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#define vvvvFromVEX2of2(vex) invertedFourBitsFromOffset3(vex)
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#define lFromVEX2of2(vex) bitFromOffset2(vex)
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#define ppFromVEX2of2(vex) twoBitsFromOffset0(vex)
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// VEX3
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#define rFromVEX2of3(vex) invertedBitFromOffset7(vex)
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#define xFromVEX2of3(vex) invertedBitFromOffset6(vex)
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#define bFromVEX2of3(vex) invertedBitFromOffset5(vex)
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#define mmmmmFromVEX2of3(vex) fiveBitsFromOffset0(vex)
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#define wFromVEX3of3(vex) bitFromOffset7(vex)
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#define vvvvFromVEX3of3(vex) invertedFourBitsFromOffset3(vex)
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#define lFromVEX3of3(vex) bitFromOffset2(vex)
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#define ppFromVEX3of3(vex) twoBitsFromOffset0(vex)
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// EVEX
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#define rFromEVEX2of4(evex) invertedBitFromOffset7(evex)
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#define xFromEVEX2of4(evex) invertedBitFromOffset6(evex)
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#define bFromEVEX2of4(evex) invertedBitFromOffset5(evex)
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#define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex)
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#define b2FromEVEX2of4(evex) bitFromOffset3(evex)
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#define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex)
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#define wFromEVEX3of4(evex) bitFromOffset7(evex)
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#define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex)
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#define x2FromEVEX3of4(evex) invertedBitFromOffset2(evex)
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#define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex)
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#define oszcFromEVEX3of4(evex) fourBitsFromOffset3(evex)
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#define zFromEVEX4of4(evex) bitFromOffset7(evex)
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#define l2FromEVEX4of4(evex) bitFromOffset6(evex)
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#define lFromEVEX4of4(evex) bitFromOffset5(evex)
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#define bFromEVEX4of4(evex) bitFromOffset4(evex)
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#define v2FromEVEX4of4(evex) invertedBitFromOffset3(evex)
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#define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex)
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#define nfFromEVEX4of4(evex) bitFromOffset2(evex)
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#define scFromEVEX4of4(evex) fourBitsFromOffset0(evex)
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// These enums represent Intel registers for use by the decoder.
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#define REGS_8BIT \
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ENTRY(AL) \
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ENTRY(CL) \
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ENTRY(DL) \
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ENTRY(BL) \
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ENTRY(AH) \
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ENTRY(CH) \
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ENTRY(DH) \
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ENTRY(BH) \
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ENTRY(R8B) \
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ENTRY(R9B) \
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ENTRY(R10B) \
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ENTRY(R11B) \
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ENTRY(R12B) \
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ENTRY(R13B) \
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ENTRY(R14B) \
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ENTRY(R15B) \
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ENTRY(R16B) \
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ENTRY(R17B) \
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ENTRY(R18B) \
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ENTRY(R19B) \
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ENTRY(R20B) \
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ENTRY(R21B) \
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ENTRY(R22B) \
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ENTRY(R23B) \
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ENTRY(R24B) \
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ENTRY(R25B) \
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ENTRY(R26B) \
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ENTRY(R27B) \
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ENTRY(R28B) \
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ENTRY(R29B) \
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ENTRY(R30B) \
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ENTRY(R31B) \
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ENTRY(SPL) \
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ENTRY(BPL) \
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ENTRY(SIL) \
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ENTRY(DIL)
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#define EA_BASES_16BIT \
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ENTRY(BX_SI) \
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ENTRY(BX_DI) \
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ENTRY(BP_SI) \
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ENTRY(BP_DI) \
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ENTRY(SI) \
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ENTRY(DI) \
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ENTRY(BP) \
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ENTRY(BX) \
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ENTRY(R8W) \
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ENTRY(R9W) \
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ENTRY(R10W) \
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ENTRY(R11W) \
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ENTRY(R12W) \
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ENTRY(R13W) \
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ENTRY(R14W) \
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ENTRY(R15W) \
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ENTRY(R16W) \
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ENTRY(R17W) \
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ENTRY(R18W) \
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ENTRY(R19W) \
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ENTRY(R20W) \
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ENTRY(R21W) \
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ENTRY(R22W) \
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ENTRY(R23W) \
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ENTRY(R24W) \
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ENTRY(R25W) \
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ENTRY(R26W) \
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ENTRY(R27W) \
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ENTRY(R28W) \
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ENTRY(R29W) \
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ENTRY(R30W) \
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ENTRY(R31W)
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#define REGS_16BIT \
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ENTRY(AX) \
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ENTRY(CX) \
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ENTRY(DX) \
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ENTRY(BX) \
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ENTRY(SP) \
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ENTRY(BP) \
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ENTRY(SI) \
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ENTRY(DI) \
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ENTRY(R8W) \
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ENTRY(R9W) \
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ENTRY(R10W) \
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ENTRY(R11W) \
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ENTRY(R12W) \
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ENTRY(R13W) \
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ENTRY(R14W) \
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ENTRY(R15W) \
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ENTRY(R16W) \
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ENTRY(R17W) \
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ENTRY(R18W) \
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ENTRY(R19W) \
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ENTRY(R20W) \
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ENTRY(R21W) \
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ENTRY(R22W) \
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ENTRY(R23W) \
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ENTRY(R24W) \
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ENTRY(R25W) \
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ENTRY(R26W) \
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ENTRY(R27W) \
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ENTRY(R28W) \
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ENTRY(R29W) \
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ENTRY(R30W) \
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ENTRY(R31W)
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#define EA_BASES_32BIT \
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ENTRY(EAX) \
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ENTRY(ECX) \
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ENTRY(EDX) \
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ENTRY(EBX) \
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ENTRY(sib) \
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ENTRY(EBP) \
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ENTRY(ESI) \
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ENTRY(EDI) \
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ENTRY(R8D) \
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ENTRY(R9D) \
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ENTRY(R10D) \
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ENTRY(R11D) \
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ENTRY(R12D) \
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ENTRY(R13D) \
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ENTRY(R14D) \
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ENTRY(R15D) \
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ENTRY(R16D) \
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ENTRY(R17D) \
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ENTRY(R18D) \
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ENTRY(R19D) \
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ENTRY(R20D) \
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ENTRY(R21D) \
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ENTRY(R22D) \
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ENTRY(R23D) \
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ENTRY(R24D) \
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ENTRY(R25D) \
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ENTRY(R26D) \
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ENTRY(R27D) \
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ENTRY(R28D) \
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ENTRY(R29D) \
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ENTRY(R30D) \
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ENTRY(R31D)
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#define REGS_32BIT \
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ENTRY(EAX) \
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ENTRY(ECX) \
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ENTRY(EDX) \
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ENTRY(EBX) \
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ENTRY(ESP) \
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ENTRY(EBP) \
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ENTRY(ESI) \
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ENTRY(EDI) \
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ENTRY(R8D) \
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ENTRY(R9D) \
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ENTRY(R10D) \
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ENTRY(R11D) \
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ENTRY(R12D) \
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ENTRY(R13D) \
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ENTRY(R14D) \
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ENTRY(R15D) \
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ENTRY(R16D) \
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ENTRY(R17D) \
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ENTRY(R18D) \
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ENTRY(R19D) \
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ENTRY(R20D) \
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ENTRY(R21D) \
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ENTRY(R22D) \
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ENTRY(R23D) \
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ENTRY(R24D) \
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ENTRY(R25D) \
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ENTRY(R26D) \
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ENTRY(R27D) \
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ENTRY(R28D) \
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ENTRY(R29D) \
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ENTRY(R30D) \
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ENTRY(R31D)
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#define EA_BASES_64BIT \
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ENTRY(RAX) \
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ENTRY(RCX) \
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ENTRY(RDX) \
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ENTRY(RBX) \
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ENTRY(sib64) \
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ENTRY(RBP) \
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ENTRY(RSI) \
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ENTRY(RDI) \
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ENTRY(R8) \
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ENTRY(R9) \
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ENTRY(R10) \
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ENTRY(R11) \
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ENTRY(R12) \
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ENTRY(R13) \
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ENTRY(R14) \
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ENTRY(R15) \
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ENTRY(R16) \
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ENTRY(R17) \
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ENTRY(R18) \
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ENTRY(R19) \
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ENTRY(R20) \
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ENTRY(R21) \
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ENTRY(R22) \
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ENTRY(R23) \
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ENTRY(R24) \
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ENTRY(R25) \
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ENTRY(R26) \
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ENTRY(R27) \
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ENTRY(R28) \
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ENTRY(R29) \
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ENTRY(R30) \
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ENTRY(R31)
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#define REGS_64BIT \
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ENTRY(RAX) \
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ENTRY(RCX) \
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ENTRY(RDX) \
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ENTRY(RBX) \
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ENTRY(RSP) \
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ENTRY(RBP) \
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ENTRY(RSI) \
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ENTRY(RDI) \
330
ENTRY(R8) \
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ENTRY(R9) \
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ENTRY(R10) \
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ENTRY(R11) \
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ENTRY(R12) \
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ENTRY(R13) \
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ENTRY(R14) \
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ENTRY(R15) \
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ENTRY(R16) \
339
ENTRY(R17) \
340
ENTRY(R18) \
341
ENTRY(R19) \
342
ENTRY(R20) \
343
ENTRY(R21) \
344
ENTRY(R22) \
345
ENTRY(R23) \
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ENTRY(R24) \
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ENTRY(R25) \
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ENTRY(R26) \
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ENTRY(R27) \
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ENTRY(R28) \
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ENTRY(R29) \
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ENTRY(R30) \
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ENTRY(R31)
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#define REGS_MMX \
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ENTRY(MM0) \
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ENTRY(MM1) \
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ENTRY(MM2) \
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ENTRY(MM3) \
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ENTRY(MM4) \
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ENTRY(MM5) \
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ENTRY(MM6) \
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ENTRY(MM7)
364
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#define REGS_XMM \
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ENTRY(XMM0) \
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ENTRY(XMM1) \
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ENTRY(XMM2) \
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ENTRY(XMM3) \
370
ENTRY(XMM4) \
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ENTRY(XMM5) \
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ENTRY(XMM6) \
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ENTRY(XMM7) \
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ENTRY(XMM8) \
375
ENTRY(XMM9) \
376
ENTRY(XMM10) \
377
ENTRY(XMM11) \
378
ENTRY(XMM12) \
379
ENTRY(XMM13) \
380
ENTRY(XMM14) \
381
ENTRY(XMM15) \
382
ENTRY(XMM16) \
383
ENTRY(XMM17) \
384
ENTRY(XMM18) \
385
ENTRY(XMM19) \
386
ENTRY(XMM20) \
387
ENTRY(XMM21) \
388
ENTRY(XMM22) \
389
ENTRY(XMM23) \
390
ENTRY(XMM24) \
391
ENTRY(XMM25) \
392
ENTRY(XMM26) \
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ENTRY(XMM27) \
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ENTRY(XMM28) \
395
ENTRY(XMM29) \
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ENTRY(XMM30) \
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ENTRY(XMM31)
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#define REGS_YMM \
400
ENTRY(YMM0) \
401
ENTRY(YMM1) \
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ENTRY(YMM2) \
403
ENTRY(YMM3) \
404
ENTRY(YMM4) \
405
ENTRY(YMM5) \
406
ENTRY(YMM6) \
407
ENTRY(YMM7) \
408
ENTRY(YMM8) \
409
ENTRY(YMM9) \
410
ENTRY(YMM10) \
411
ENTRY(YMM11) \
412
ENTRY(YMM12) \
413
ENTRY(YMM13) \
414
ENTRY(YMM14) \
415
ENTRY(YMM15) \
416
ENTRY(YMM16) \
417
ENTRY(YMM17) \
418
ENTRY(YMM18) \
419
ENTRY(YMM19) \
420
ENTRY(YMM20) \
421
ENTRY(YMM21) \
422
ENTRY(YMM22) \
423
ENTRY(YMM23) \
424
ENTRY(YMM24) \
425
ENTRY(YMM25) \
426
ENTRY(YMM26) \
427
ENTRY(YMM27) \
428
ENTRY(YMM28) \
429
ENTRY(YMM29) \
430
ENTRY(YMM30) \
431
ENTRY(YMM31)
432
433
#define REGS_ZMM \
434
ENTRY(ZMM0) \
435
ENTRY(ZMM1) \
436
ENTRY(ZMM2) \
437
ENTRY(ZMM3) \
438
ENTRY(ZMM4) \
439
ENTRY(ZMM5) \
440
ENTRY(ZMM6) \
441
ENTRY(ZMM7) \
442
ENTRY(ZMM8) \
443
ENTRY(ZMM9) \
444
ENTRY(ZMM10) \
445
ENTRY(ZMM11) \
446
ENTRY(ZMM12) \
447
ENTRY(ZMM13) \
448
ENTRY(ZMM14) \
449
ENTRY(ZMM15) \
450
ENTRY(ZMM16) \
451
ENTRY(ZMM17) \
452
ENTRY(ZMM18) \
453
ENTRY(ZMM19) \
454
ENTRY(ZMM20) \
455
ENTRY(ZMM21) \
456
ENTRY(ZMM22) \
457
ENTRY(ZMM23) \
458
ENTRY(ZMM24) \
459
ENTRY(ZMM25) \
460
ENTRY(ZMM26) \
461
ENTRY(ZMM27) \
462
ENTRY(ZMM28) \
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ENTRY(ZMM29) \
464
ENTRY(ZMM30) \
465
ENTRY(ZMM31)
466
467
#define REGS_MASKS \
468
ENTRY(K0) \
469
ENTRY(K1) \
470
ENTRY(K2) \
471
ENTRY(K3) \
472
ENTRY(K4) \
473
ENTRY(K5) \
474
ENTRY(K6) \
475
ENTRY(K7)
476
477
#define REGS_MASK_PAIRS \
478
ENTRY(K0_K1) \
479
ENTRY(K2_K3) \
480
ENTRY(K4_K5) \
481
ENTRY(K6_K7)
482
483
#define REGS_SEGMENT \
484
ENTRY(ES) \
485
ENTRY(CS) \
486
ENTRY(SS) \
487
ENTRY(DS) \
488
ENTRY(FS) \
489
ENTRY(GS)
490
491
#define REGS_DEBUG \
492
ENTRY(DR0) \
493
ENTRY(DR1) \
494
ENTRY(DR2) \
495
ENTRY(DR3) \
496
ENTRY(DR4) \
497
ENTRY(DR5) \
498
ENTRY(DR6) \
499
ENTRY(DR7) \
500
ENTRY(DR8) \
501
ENTRY(DR9) \
502
ENTRY(DR10) \
503
ENTRY(DR11) \
504
ENTRY(DR12) \
505
ENTRY(DR13) \
506
ENTRY(DR14) \
507
ENTRY(DR15)
508
509
#define REGS_CONTROL \
510
ENTRY(CR0) \
511
ENTRY(CR1) \
512
ENTRY(CR2) \
513
ENTRY(CR3) \
514
ENTRY(CR4) \
515
ENTRY(CR5) \
516
ENTRY(CR6) \
517
ENTRY(CR7) \
518
ENTRY(CR8) \
519
ENTRY(CR9) \
520
ENTRY(CR10) \
521
ENTRY(CR11) \
522
ENTRY(CR12) \
523
ENTRY(CR13) \
524
ENTRY(CR14) \
525
ENTRY(CR15)
526
527
#undef REGS_TMM
528
#define REGS_TMM \
529
ENTRY(TMM0) \
530
ENTRY(TMM1) \
531
ENTRY(TMM2) \
532
ENTRY(TMM3) \
533
ENTRY(TMM4) \
534
ENTRY(TMM5) \
535
ENTRY(TMM6) \
536
ENTRY(TMM7)
537
538
#define ALL_EA_BASES \
539
EA_BASES_16BIT \
540
EA_BASES_32BIT \
541
EA_BASES_64BIT
542
543
#define ALL_SIB_BASES \
544
REGS_32BIT \
545
REGS_64BIT
546
547
#define ALL_REGS \
548
REGS_8BIT \
549
REGS_16BIT \
550
REGS_32BIT \
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REGS_64BIT \
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REGS_MMX \
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REGS_XMM \
554
REGS_YMM \
555
REGS_ZMM \
556
REGS_MASKS \
557
REGS_MASK_PAIRS \
558
REGS_SEGMENT \
559
REGS_DEBUG \
560
REGS_CONTROL \
561
REGS_TMM \
562
ENTRY(RIP)
563
564
/// All possible values of the base field for effective-address
565
/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
566
/// We distinguish between bases (EA_BASE_*) and registers that just happen
567
/// to be referred to when Mod == 0b11 (EA_REG_*).
568
enum EABase {
569
// clang-format off
570
EA_BASE_NONE,
571
#define ENTRY(x) EA_BASE_##x,
572
ALL_EA_BASES
573
#undef ENTRY
574
#define ENTRY(x) EA_REG_##x,
575
ALL_REGS
576
#undef ENTRY
577
EA_max
578
// clang-format on
579
};
580
581
/// All possible values of the SIB index field.
582
/// borrows entries from ALL_EA_BASES with the special case that
583
/// sib is synonymous with NONE.
584
/// Vector SIB: index can be XMM or YMM.
585
enum SIBIndex {
586
// clang-format off
587
SIB_INDEX_NONE,
588
#define ENTRY(x) SIB_INDEX_##x,
589
ALL_EA_BASES
590
REGS_XMM
591
REGS_YMM
592
REGS_ZMM
593
#undef ENTRY
594
SIB_INDEX_max
595
// clang-format on
596
};
597
598
/// All possible values of the SIB base field.
599
enum SIBBase {
600
// clang-format off
601
SIB_BASE_NONE,
602
#define ENTRY(x) SIB_BASE_##x,
603
ALL_SIB_BASES
604
#undef ENTRY
605
SIB_BASE_max
606
// clang-format on
607
};
608
609
/// Possible displacement types for effective-address computations.
610
enum EADisplacement { EA_DISP_NONE, EA_DISP_8, EA_DISP_16, EA_DISP_32 };
611
612
/// All possible values of the reg field in the ModR/M byte.
613
// clang-format off
614
enum Reg {
615
#define ENTRY(x) MODRM_REG_##x,
616
ALL_REGS
617
#undef ENTRY
618
MODRM_REG_max
619
};
620
// clang-format on
621
622
/// All possible segment overrides.
623
enum SegmentOverride {
624
SEG_OVERRIDE_NONE,
625
SEG_OVERRIDE_CS,
626
SEG_OVERRIDE_SS,
627
SEG_OVERRIDE_DS,
628
SEG_OVERRIDE_ES,
629
SEG_OVERRIDE_FS,
630
SEG_OVERRIDE_GS,
631
SEG_OVERRIDE_max
632
};
633
634
/// Possible values for the VEX.m-mmmm field
635
enum VEXLeadingOpcodeByte {
636
VEX_LOB_0F = 0x1,
637
VEX_LOB_0F38 = 0x2,
638
VEX_LOB_0F3A = 0x3,
639
VEX_LOB_MAP4 = 0x4,
640
VEX_LOB_MAP5 = 0x5,
641
VEX_LOB_MAP6 = 0x6,
642
VEX_LOB_MAP7 = 0x7
643
};
644
645
enum XOPMapSelect {
646
XOP_MAP_SELECT_8 = 0x8,
647
XOP_MAP_SELECT_9 = 0x9,
648
XOP_MAP_SELECT_A = 0xA
649
};
650
651
/// Possible values for the VEX.pp/EVEX.pp field
652
enum VEXPrefixCode {
653
VEX_PREFIX_NONE = 0x0,
654
VEX_PREFIX_66 = 0x1,
655
VEX_PREFIX_F3 = 0x2,
656
VEX_PREFIX_F2 = 0x3
657
};
658
659
enum VectorExtensionType {
660
TYPE_NO_VEX_XOP = 0x0,
661
TYPE_VEX_2B = 0x1,
662
TYPE_VEX_3B = 0x2,
663
TYPE_EVEX = 0x3,
664
TYPE_XOP = 0x4
665
};
666
667
/// The specification for how to extract and interpret a full instruction and
668
/// its operands.
669
struct InstructionSpecifier {
670
uint16_t operands;
671
};
672
673
/// The x86 internal instruction, which is produced by the decoder.
674
struct InternalInstruction {
675
// Opaque value passed to the reader
676
llvm::ArrayRef<uint8_t> bytes;
677
// The address of the next byte to read via the reader
678
uint64_t readerCursor;
679
680
// General instruction information
681
682
// The mode to disassemble for (64-bit, protected, real)
683
DisassemblerMode mode;
684
// The start of the instruction, usable with the reader
685
uint64_t startLocation;
686
// The length of the instruction, in bytes
687
size_t length;
688
689
// Prefix state
690
691
// The possible mandatory prefix
692
uint8_t mandatoryPrefix;
693
// The value of the vector extension prefix(EVEX/VEX/XOP), if present
694
uint8_t vectorExtensionPrefix[4];
695
// The type of the vector extension prefix
696
VectorExtensionType vectorExtensionType;
697
// The value of the REX2 prefix, if present
698
uint8_t rex2ExtensionPrefix[2];
699
// The value of the REX prefix, if present
700
uint8_t rexPrefix;
701
// The segment override type
702
SegmentOverride segmentOverride;
703
// 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease
704
bool xAcquireRelease;
705
706
// Address-size override
707
bool hasAdSize;
708
// Operand-size override
709
bool hasOpSize;
710
// Lock prefix
711
bool hasLockPrefix;
712
// The repeat prefix if any
713
uint8_t repeatPrefix;
714
715
// Sizes of various critical pieces of data, in bytes
716
uint8_t registerSize;
717
uint8_t addressSize;
718
uint8_t displacementSize;
719
uint8_t immediateSize;
720
721
// Offsets from the start of the instruction to the pieces of data, which is
722
// needed to find relocation entries for adding symbolic operands.
723
uint8_t displacementOffset;
724
uint8_t immediateOffset;
725
726
// opcode state
727
728
// The last byte of the opcode, not counting any ModR/M extension
729
uint8_t opcode;
730
731
// decode state
732
733
// The type of opcode, used for indexing into the array of decode tables
734
OpcodeType opcodeType;
735
// The instruction ID, extracted from the decode table
736
uint16_t instructionID;
737
// The specifier for the instruction, from the instruction info table
738
const InstructionSpecifier *spec;
739
740
// state for additional bytes, consumed during operand decode. Pattern:
741
// consumed___ indicates that the byte was already consumed and does not
742
// need to be consumed again.
743
744
// The VEX.vvvv field, which contains a third register operand for some AVX
745
// instructions.
746
Reg vvvv;
747
748
// The writemask for AVX-512 instructions which is contained in EVEX.aaa
749
Reg writemask;
750
751
// The ModR/M byte, which contains most register operands and some portion of
752
// all memory operands.
753
bool consumedModRM;
754
uint8_t modRM;
755
756
// The SIB byte, used for more complex 32- or 64-bit memory operands
757
uint8_t sib;
758
759
// The displacement, used for memory operands
760
int32_t displacement;
761
762
// Immediates. There can be three in some cases
763
uint8_t numImmediatesConsumed;
764
uint8_t numImmediatesTranslated;
765
uint64_t immediates[3];
766
767
// A register or immediate operand encoded into the opcode
768
Reg opcodeRegister;
769
770
// Portions of the ModR/M byte
771
772
// These fields determine the allowable values for the ModR/M fields, which
773
// depend on operand and address widths.
774
EABase eaRegBase;
775
Reg regBase;
776
777
// The Mod and R/M fields can encode a base for an effective address, or a
778
// register. These are separated into two fields here.
779
EABase eaBase;
780
EADisplacement eaDisplacement;
781
// The reg field always encodes a register
782
Reg reg;
783
784
// SIB state
785
SIBIndex sibIndexBase;
786
SIBIndex sibIndex;
787
uint8_t sibScale;
788
SIBBase sibBase;
789
790
// Embedded rounding control.
791
uint8_t RC;
792
793
ArrayRef<OperandSpecifier> operands;
794
};
795
796
} // namespace X86Disassembler
797
} // namespace llvm
798
799
#endif
800
801