Path: blob/main/contrib/llvm-project/llvm/lib/Target/Xtensa/XtensaISelLowering.h
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//===- XtensaISelLowering.h - Xtensa DAG Lowering Interface -----*- C++ -*-===//1//2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3// See https://llvm.org/LICENSE.txt for license information.4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5//6//===----------------------------------------------------------------------===//7//8// This file defines the interfaces that Xtensa uses to lower LLVM code into a9// selection DAG.10//11//===----------------------------------------------------------------------===//1213#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H14#define LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H1516#include "llvm/CodeGen/CallingConvLower.h"17#include "llvm/CodeGen/SelectionDAG.h"18#include "llvm/CodeGen/TargetLowering.h"1920namespace llvm {2122namespace XtensaISD {23enum {24FIRST_NUMBER = ISD::BUILTIN_OP_END,25BR_JT,2627// Calls a function. Operand 0 is the chain operand and operand 128// is the target address. The arguments start at operand 2.29// There is an optional glue operand at the end.30CALL,3132// Wraps a TargetGlobalAddress that should be loaded using PC-relative33// accesses. Operand 0 is the address.34PCREL_WRAPPER,35RET,3637// Select with condition operator - This selects between a true value and38// a false value (ops #2 and #3) based on the boolean result of comparing39// the lhs and rhs (ops #0 and #1) of a conditional expression with the40// condition code in op #441SELECT_CC,42};43}4445class XtensaSubtarget;4647class XtensaTargetLowering : public TargetLowering {48public:49explicit XtensaTargetLowering(const TargetMachine &TM,50const XtensaSubtarget &STI);5152EVT getSetCCResultType(const DataLayout &, LLVMContext &,53EVT VT) const override {54if (!VT.isVector())55return MVT::i32;56return VT.changeVectorElementTypeToInteger();57}5859bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;6061const char *getTargetNodeName(unsigned Opcode) const override;6263SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;6465SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,66bool isVarArg,67const SmallVectorImpl<ISD::InputArg> &Ins,68const SDLoc &DL, SelectionDAG &DAG,69SmallVectorImpl<SDValue> &InVals) const override;7071SDValue LowerCall(CallLoweringInfo &CLI,72SmallVectorImpl<SDValue> &InVals) const override;7374bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,75bool isVarArg,76const SmallVectorImpl<ISD::OutputArg> &Outs,77LLVMContext &Context) const override;7879SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,80const SmallVectorImpl<ISD::OutputArg> &Outs,81const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,82SelectionDAG &DAG) const override;8384const XtensaSubtarget &getSubtarget() const { return Subtarget; }8586MachineBasicBlock *87EmitInstrWithCustomInserter(MachineInstr &MI,88MachineBasicBlock *BB) const override;8990private:91const XtensaSubtarget &Subtarget;9293SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;9495SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;9697SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;9899SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;100101SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;102103SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;104105SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;106107SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;108109SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;110111SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;112113SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const;114115CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;116117MachineBasicBlock *emitSelectCC(MachineInstr &MI,118MachineBasicBlock *BB) const;119};120121} // end namespace llvm122123#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H */124125126