Path: blob/main/contrib/llvm-project/llvm/tools/llvm-mca/Views/DispatchStatistics.cpp
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//===--------------------- DispatchStatistics.cpp ---------------*- C++ -*-===//1//2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.3// See https://llvm.org/LICENSE.txt for license information.4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception5//6//===----------------------------------------------------------------------===//7/// \file8///9/// This file implements the DispatchStatistics interface.10///11//===----------------------------------------------------------------------===//1213#include "Views/DispatchStatistics.h"14#include "llvm/Support/Format.h"1516namespace llvm {17namespace mca {1819void DispatchStatistics::onEvent(const HWStallEvent &Event) {20if (Event.Type < HWStallEvent::LastGenericEvent)21HWStalls[Event.Type]++;22}2324void DispatchStatistics::onEvent(const HWInstructionEvent &Event) {25if (Event.Type != HWInstructionEvent::Dispatched)26return;2728const auto &DE = static_cast<const HWInstructionDispatchedEvent &>(Event);29NumDispatched += DE.MicroOpcodes;30}3132void DispatchStatistics::printDispatchHistogram(raw_ostream &OS) const {33std::string Buffer;34raw_string_ostream TempStream(Buffer);35TempStream << "\n\nDispatch Logic - "36<< "number of cycles where we saw N micro opcodes dispatched:\n";37TempStream << "[# dispatched], [# cycles]\n";38for (const std::pair<const unsigned, unsigned> &Entry :39DispatchGroupSizePerCycle) {40double Percentage = ((double)Entry.second / NumCycles) * 100.0;41TempStream << " " << Entry.first << ", " << Entry.second42<< " (" << format("%.1f", floor((Percentage * 10) + 0.5) / 10)43<< "%)\n";44}4546TempStream.flush();47OS << Buffer;48}4950static void printStalls(raw_ostream &OS, unsigned NumStalls,51unsigned NumCycles) {52if (!NumStalls) {53OS << NumStalls;54return;55}5657double Percentage = ((double)NumStalls / NumCycles) * 100.0;58OS << NumStalls << " ("59<< format("%.1f", floor((Percentage * 10) + 0.5) / 10) << "%)";60}6162void DispatchStatistics::printDispatchStalls(raw_ostream &OS) const {63std::string Buffer;64raw_string_ostream SS(Buffer);65SS << "\n\nDynamic Dispatch Stall Cycles:\n";66SS << "RAT - Register unavailable: ";67printStalls(SS, HWStalls[HWStallEvent::RegisterFileStall], NumCycles);68SS << "\nRCU - Retire tokens unavailable: ";69printStalls(SS, HWStalls[HWStallEvent::RetireControlUnitStall], NumCycles);70SS << "\nSCHEDQ - Scheduler full: ";71printStalls(SS, HWStalls[HWStallEvent::SchedulerQueueFull], NumCycles);72SS << "\nLQ - Load queue full: ";73printStalls(SS, HWStalls[HWStallEvent::LoadQueueFull], NumCycles);74SS << "\nSQ - Store queue full: ";75printStalls(SS, HWStalls[HWStallEvent::StoreQueueFull], NumCycles);76SS << "\nGROUP - Static restrictions on the dispatch group: ";77printStalls(SS, HWStalls[HWStallEvent::DispatchGroupStall], NumCycles);78SS << "\nUSH - Uncategorised Structural Hazard: ";79printStalls(SS, HWStalls[HWStallEvent::CustomBehaviourStall], NumCycles);80SS << '\n';81SS.flush();82OS << Buffer;83}8485json::Value DispatchStatistics::toJSON() const {86json::Object JO({{"RAT", HWStalls[HWStallEvent::RegisterFileStall]},87{"RCU", HWStalls[HWStallEvent::RetireControlUnitStall]},88{"SCHEDQ", HWStalls[HWStallEvent::SchedulerQueueFull]},89{"LQ", HWStalls[HWStallEvent::LoadQueueFull]},90{"SQ", HWStalls[HWStallEvent::StoreQueueFull]},91{"GROUP", HWStalls[HWStallEvent::DispatchGroupStall]},92{"USH", HWStalls[HWStallEvent::CustomBehaviourStall]}});93return JO;94}9596} // namespace mca97} // namespace llvm9899100