/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2011 NetApp, Inc.4* All rights reserved.5*6* Redistribution and use in source and binary forms, with or without7* modification, are permitted provided that the following conditions8* are met:9* 1. Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer.11* 2. Redistributions in binary form must reproduce the above copyright12* notice, this list of conditions and the following disclaimer in the13* documentation and/or other materials provided with the distribution.14*15* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND16* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE17* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE18* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE19* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL20* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS21* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)22* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT23* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY24* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF25* SUCH DAMAGE.26*/2728#ifndef _VMM_LAPIC_H_29#define _VMM_LAPIC_H_3031struct vcpu;32struct vm;3334bool lapic_msr(u_int num);35int lapic_rdmsr(struct vcpu *vcpu, u_int msr, uint64_t *rval, bool *retu);36int lapic_wrmsr(struct vcpu *vcpu, u_int msr, uint64_t wval, bool *retu);3738int lapic_mmio_read(struct vcpu *vcpu, uint64_t gpa,39uint64_t *rval, int size, void *arg);40int lapic_mmio_write(struct vcpu *vcpu, uint64_t gpa,41uint64_t wval, int size, void *arg);4243/*44* Signals to the LAPIC that an interrupt at 'vector' needs to be generated45* to the 'cpu', the state is recorded in IRR.46*/47int lapic_set_intr(struct vcpu *vcpu, int vector, bool trig);4849#define LAPIC_TRIG_LEVEL true50#define LAPIC_TRIG_EDGE false51static __inline int52lapic_intr_level(struct vcpu *vcpu, int vector)53{5455return (lapic_set_intr(vcpu, vector, LAPIC_TRIG_LEVEL));56}5758static __inline int59lapic_intr_edge(struct vcpu *vcpu, int vector)60{6162return (lapic_set_intr(vcpu, vector, LAPIC_TRIG_EDGE));63}6465/*66* Triggers the LAPIC local interrupt (LVT) 'vector' on 'cpu'. 'cpu' can67* be set to -1 to trigger the interrupt on all CPUs.68*/69int lapic_set_local_intr(struct vm *vm, struct vcpu *vcpu, int vector);7071int lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg);7273#endif747576