Path: blob/main/sys/arm/allwinner/a20/a20_cpu_cfg.h
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2013 Ganbold Tsagaankhuu <[email protected]>4* All rights reserved.5*6* Redistribution and use in source and binary forms, with or without7* modification, are permitted provided that the following conditions8* are met:9* 1. Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer.11* 2. Redistributions in binary form must reproduce the above copyright12* notice, this list of conditions and the following disclaimer in the13* documentation and/or other materials provided with the distribution.14*15* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND16* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE17* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE18* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE19* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL20* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS21* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION22* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT23* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY24* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF25* SUCH DAMAGE.26*/2728#ifndef _A20_CPU_CFG_H_29#define _A20_CPU_CFG_H_3031#define CPU_CFG_BASE 0xe1c25c003233#define CPU0_RST_CTRL 0x004034#define CPU0_CTRL_REG 0x004435#define CPU0_STATUS_REG 0x00483637#define CPU1_RST_CTRL 0x008038#define CPU1_CTRL_REG 0x008439#define CPU1_STATUS_REG 0x00884041#define GENER_CTRL_REG 0x01844243#define EVENT_IN_REG 0x019044#define PRIVATE_REG 0x01a44546#define IDLE_CNT0_LOW_REG 0x020047#define IDLE_CNT0_HIGH_REG 0x020448#define IDLE_CNT0_CTRL_REG 0x02084950#define IDLE_CNT1_LOW_REG 0x021051#define IDLE_CNT1_HIGH_REG 0x021452#define IDLE_CNT1_CTRL_REG 0x02185354#define OSC24M_CNT64_CTRL_REG 0x028055#define OSC24M_CNT64_LOW_REG 0x028456#define OSC24M_CNT64_HIGH_REG 0x02885758#define LOSC_CNT64_CTRL_REG 0x029059#define LOSC_CNT64_LOW_REG 0x029460#define LOSC_CNT64_HIGH_REG 0x02986162#define CNT64_RL_EN 0x02 /* read latch enable */6364uint64_t a20_read_counter64(void);6566#endif /* _A20_CPU_CFG_H_ */676869