/*-1* Copyright 2011 Semihalf2* All rights reserved.3*4* Redistribution and use in source and binary forms, with or without5* modification, are permitted provided that the following conditions6* are met:7* 1. Redistributions of source code must retain the above copyright8* notice, this list of conditions and the following disclaimer.9* 2. Redistributions in binary form must reproduce the above copyright10* notice, this list of conditions and the following disclaimer in the11* documentation and/or other materials provided with the distribution.12*13* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND14* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE15* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE16* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE17* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL18* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS19* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)20* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT21* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY22* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF23* SUCH DAMAGE.24*/2526#include <machine/asm.h>27#include <machine/armreg.h>28.global _C_LABEL(mptramp_pmu_boot)2930ASENTRY_NP(mptramp)31mov r0, #032mcr p15, 0, r0, c7, c7, 03334mrs r3, cpsr35bic r3, r3, #(PSR_MODE)36orr r3, r3, #(PSR_SVC32_MODE)37msr cpsr_fsxc, r33839mrc p15, 0, r0, c0, c0, 540and r0, #0x0f /* Get CPU ID */4142/* Read boot address for CPU */43mov r1, #0x10044mul r2, r0, r145ldr r1, mptramp_pmu_boot46add r0, r2, r147ldr r1, [r0], #0x004849mov pc, r15051_C_LABEL(mptramp_pmu_boot):52.word 0x05354END(mptramp)5556.global _C_LABEL(mptramp_end)57_C_LABEL(mptramp_end):585960