/*-1* Copyright (c) 2016 Michal Meloun <[email protected]>2* All rights reserved.3*4* Redistribution and use in source and binary forms, with or without5* modification, are permitted provided that the following conditions6* are met:7* 1. Redistributions of source code must retain the above copyright8* notice, this list of conditions and the following disclaimer.9* 2. Redistributions in binary form must reproduce the above copyright10* notice, this list of conditions and the following disclaimer in the11* documentation and/or other materials provided with the distribution.12*13* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND14* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE15* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE16* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE17* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL18* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS19* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)20* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT21* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY22* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF23* SUCH DAMAGE.24*/2526#ifndef _TEGRA_EFUSE_H_2728enum tegra_revision {29TEGRA_REVISION_UNKNOWN = 0,30TEGRA_REVISION_A01,31TEGRA_REVISION_A02,32TEGRA_REVISION_A03,33TEGRA_REVISION_A03p,34TEGRA_REVISION_A04,35};3637struct tegra_sku_info {38u_int chip_id;39u_int sku_id;40u_int cpu_process_id;41u_int cpu_speedo_id;42u_int cpu_speedo_value;43u_int cpu_iddq_value;44u_int soc_process_id;45u_int soc_speedo_id;46u_int soc_speedo_value;47u_int soc_iddq_value;48u_int gpu_process_id;49u_int gpu_speedo_id;50u_int gpu_speedo_value;51u_int gpu_iddq_value;52enum tegra_revision revision;53};5455extern struct tegra_sku_info tegra_sku_info;56uint32_t tegra_fuse_read_4(int addr);5758#endif /* _TEGRA_EFUSE_H_ */596061