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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/sys/arm/qualcomm/qcom_cpu_kpssv2_reg.h
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/*-

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 * SPDX-License-Identifier: BSD-2-Clause

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 *

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 * Copyright (c) 2021 Adrian Chadd <[email protected]>

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 *

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 * Redistribution and use in source and binary forms, with or without

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 * modification, are permitted provided that the following conditions

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 * are met:

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 * 1. Redistributions of source code must retain the above copyright

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 *    notice, this list of conditions and the following disclaimer.

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 * 2. Redistributions in binary form must reproduce the above copyright

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 *    notice, this list of conditions and the following disclaimer in the

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 *    documentation and/or other materials provided with the distribution.

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 *

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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND

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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE

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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

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 * SUCH DAMAGE.

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 */

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#ifndef	__QCOM_CPU_KPSSV2_REG_H__

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#define	__QCOM_CPU_KPSSV2_REG_H__

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/*

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 * APCS CPU core regulator registers.

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 */

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#define	QCOM_APCS_CPU_PWR_CTL				0x04

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#define		QCOM_APCS_CPU_PWR_CTL_PLL_CLAMP		(1U << 8)

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#define		QCOM_APCS_CPU_PWR_CTL_CORE_PWRD_UP	(1U << 7)

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#define		QCOM_APCS_CPU_PWR_CTL_COREPOR_RST	(1U << 5)

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#define		QCOM_APCS_CPU_PWR_CTL_CORE_RST		(1U << 4)

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#define		QCOM_APCS_CPU_PWR_CTL_L2DT_SLP		(1U << 3)

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#define		QCOM_APCS_CPU_PWR_CTL_CLAMP		(1U << 0)

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#define	QCOM_APC_PWR_GATE_CTL				0x14

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#define		QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT	24

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#define		QCOM_APC_PWR_GATE_CTL_LDO_PWR_DWN_SHIFT	16

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#define		QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT	8

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#define		QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT	1

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#define		QCOM_APC_PWR_GATE_CTL_BHS_EN		(1U << 0)

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/*

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 * L2 cache regulator registers.

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 */

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#define	QCOM_APCS_SAW2_2_VCTL        0x1c

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#endif	/* __QCOM_CPU_KPSSV2_REG_H__ */

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