Path: blob/main/sys/arm/qualcomm/qcom_scm_legacy_defs.h
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2021 Adrian Chadd <[email protected]>4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8* 1. Redistributions of source code must retain the above copyright9* notice, this list of conditions and the following disclaimer.10* 2. Redistributions in binary form must reproduce the above copyright11* notice, this list of conditions and the following disclaimer in the12* documentation and/or other materials provided with the distribution.13*14* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND15* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE16* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE17* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE18* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL19* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS20* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)21* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT22* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY23* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF24* SUCH DAMAGE.25*/2627#ifndef __QCOM_SCM_LEGACY_DEFS_H__28#define __QCOM_SCM_LEGACY_DEFS_H__2930/*31* These definitions are specific to the 32 bit legacy SCM interface32* used by the IPQ806x and IPQ401x SoCs.33*/3435/*36* Mapping of the SCM service/command fields into the a0 argument37* in an SMC instruction call.38*39* This is particular to the legacy SCM interface, and is not the40* same as the non-legacy 32/64 bit FNID mapping layout.41*/42#define QCOM_SCM_LEGACY_SMC_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))4344/*45* There are two kinds of SCM calls in this legacy path.46*47* The first kind are the normal ones - up to a defined max of arguments,48* a defined max of responses and some identifiers for all of it.49* They can be issues in parallel on different cores, can be interrupted,50* etc.51*52* The second kind are what are termed "atomic" SCM calls -53* up to 5 argument DWORDs, up to 3 response DWORDs, done atomically,54* not interruptable/parallel.55*56* The former use the structures below to represent the request and response57* in memory. The latter use defines and a direct SMC call with the58* arguments in registers.59*/6061struct qcom_scm_legacy_smc_args {62uint32_t args[8];63};6465/*66* Atomic SCM call command/response buffer definitions.67*/68#define QCOM_SCM_LEGACY_ATOMIC_MAX_ARGCOUNT 569#define QCOM_SCM_LEGACY_CLASS_REGISTER (0x2 << 8)70#define QCOM_SCM_LEGACY_MASK_IRQS (1U << 5)7172/*73* Mapping an SCM service/command/argcount into the a0 register74* for an SMC instruction call.75*/76#define QCOM_SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \77((QCOM_SCM_LEGACY_SMC_FNID((svc), cmd) << 12) | \78QCOM_SCM_LEGACY_CLASS_REGISTER | \79QCOM_SCM_LEGACY_MASK_IRQS | \80((n) & 0xf))8182/*83* Legacy command/response buffer definitions.84*85* The legacy path contains up to the defined maximum arguments86* but only a single command/response pair per call.87*88* A command and response buffer is laid out in memory as such:89*90* | command header |91* | (buffer payload) |92* | response header |93* | (response payload) |94*/9596/*97* The command header.98*99* len - the length of the total command and response, including100* the headers.101*102* buf_offset - the offset inside the buffer, starting at the103* beginning of this command header, where the command buffer104* is found. The end is the byte before the response_header_offset.105*106* response_header_offset - the offset inside the buffer where107* the response header is found.108*109* id - the QCOM_SCM_LEGACY_SMC_FNID() - service/command ids110*/111struct qcom_scm_legacy_command_header {112uint32_t len;113uint32_t buf_offset;114uint32_t response_header_offset;115uint32_t id;116};117118/*119* The response header.120*121* This is found immediately after the command header and command122* buffer payload.123*124* len - the total amount of memory available for the response.125* Linux doesn't set this; it always passes in a response126* buffer large enough to store MAX_QCOM_SCM_RETS * DWORD127* bytes.128*129* It's also possible this is set by the firmware.130*131* buf_offset - start of response buffer, relative to the beginning132* of the command header. This also isn't set in Linux before133* calling the SMC instruction, but it is checked afterwards134* to assemble a pointer to the response data. The firmware135* likely sets this.136*137* is_complete - true if complete. Linux loops over DMA sync to138* check if this is complete even after the SMC call returns.139*/140struct qcom_scm_legacy_response_header {141uint32_t len;142uint32_t buf_offset;143uint32_t is_complete;144};145146#endif /* __QCOM_SCM_LEGACY_DEFS_H__ */147148149