Path: blob/main/sys/arm/ti/clk/ti_divider_clock.c
107672 views
/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2020 Oskar Holmlund <[email protected]>4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8* 1. Redistributions of source code must retain the above copyright9* notice, this list of conditions and the following disclaimer.10* 2. Redistributions in binary form must reproduce the above copyright11* notice, this list of conditions and the following disclaimer in the12* documentation and/or other materials provided with the distribution.13*14* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR15* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES16* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.17* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,18* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,19* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;20* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED21* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,22* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY23* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF24* SUCH DAMAGE.25*/2627#include <sys/param.h>28#include <sys/conf.h>29#include <sys/bus.h>30#include <sys/kernel.h>31#include <sys/module.h>32#include <sys/systm.h>33#include <sys/libkern.h>3435#include <machine/bus.h>36#include <dev/fdt/simplebus.h>3738#include <dev/clk/clk_div.h>39#include <dev/ofw/ofw_bus.h>40#include <dev/ofw/ofw_bus_subr.h>4142#include "clock_common.h"4344#if 045#define DPRINTF(dev, msg...) device_printf(dev, msg)46#else47#define DPRINTF(dev, msg...)48#endif4950/*51* Devicetree description52* Documentation/devicetree/bindings/clock/ti/divider.txt53*/5455struct ti_divider_softc {56device_t sc_dev;57bool attach_done;58struct clk_div_def div_def;5960struct clock_cell_info clock_cell;61struct clkdom *clkdom;62};6364static int ti_divider_probe(device_t dev);65static int ti_divider_attach(device_t dev);66static int ti_divider_detach(device_t dev);6768#define TI_DIVIDER_CLOCK 269#define TI_COMPOSITE_DIVIDER_CLOCK 170#define TI_DIVIDER_END 07172static struct ofw_compat_data compat_data[] = {73{ "ti,divider-clock", TI_DIVIDER_CLOCK },74{ "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK },75{ NULL, TI_DIVIDER_END }76};7778static int79register_clk(struct ti_divider_softc *sc) {80int err;8182sc->clkdom = clkdom_create(sc->sc_dev);83if (sc->clkdom == NULL) {84DPRINTF(sc->sc_dev, "Failed to create clkdom\n");85return (ENXIO);86}8788err = clknode_div_register(sc->clkdom, &sc->div_def);89if (err) {90DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err);91return (ENXIO);92}9394err = clkdom_finit(sc->clkdom);95if (err) {96DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err);97return (ENXIO);98}99100return (0);101}102103static int104ti_divider_probe(device_t dev)105{106if (!ofw_bus_status_okay(dev))107return (ENXIO);108109if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)110return (ENXIO);111112device_set_desc(dev, "TI Divider Clock");113114return (BUS_PROBE_DEFAULT);115}116117static int118ti_divider_attach(device_t dev)119{120struct ti_divider_softc *sc;121phandle_t node;122int err;123cell_t value;124uint32_t ti_max_div;125126sc = device_get_softc(dev);127sc->sc_dev = dev;128node = ofw_bus_get_node(dev);129130/* Grab the content of reg properties */131OF_getencprop(node, "reg", &value, sizeof(value));132sc->div_def.offset = value;133134if (OF_hasprop(node, "ti,bit-shift")) {135OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));136sc->div_def.i_shift = value;137}138139if (OF_hasprop(node, "ti,index-starts-at-one")) {140sc->div_def.div_flags = CLK_DIV_ZERO_BASED;141}142143if (OF_hasprop(node, "ti,index-power-of-two")) {144/* FIXME: later */145device_printf(sc->sc_dev, "ti,index-power-of-two - Not implemented\n");146/* remember to update i_width a few lines below */147}148if (OF_hasprop(node, "ti,max-div")) {149OF_getencprop(node, "ti,max-div", &value, sizeof(value));150ti_max_div = value;151}152153if (OF_hasprop(node, "clock-output-names"))154device_printf(sc->sc_dev, "clock-output-names\n");155if (OF_hasprop(node, "ti,dividers"))156device_printf(sc->sc_dev, "ti,dividers\n");157if (OF_hasprop(node, "ti,min-div"))158device_printf(sc->sc_dev, "ti,min-div - Not implemented\n");159160if (OF_hasprop(node, "ti,autoidle-shift"))161device_printf(sc->sc_dev, "ti,autoidle-shift - Not implemented\n");162if (OF_hasprop(node, "ti,set-rate-parent"))163device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n");164if (OF_hasprop(node, "ti,latch-bit"))165device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n");166167/* Figure out the width from ti_max_div */168if (sc->div_def.div_flags)169sc->div_def.i_width = fls(ti_max_div-1);170else171sc->div_def.i_width = fls(ti_max_div);172173DPRINTF(sc->sc_dev, "div_def.i_width %x\n", sc->div_def.i_width);174175read_clock_cells(sc->sc_dev, &sc->clock_cell);176177create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);178179err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);180181if (err) {182/* free_clkdef will be called in ti_divider_new_pass */183DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");184bus_attach_children(sc->sc_dev);185return (0);186}187188err = register_clk(sc);189190if (err) {191/* free_clkdef will be called in ti_divider_new_pass */192DPRINTF(sc->sc_dev, "register_clk failed\n");193bus_attach_children(sc->sc_dev);194return (0);195}196197sc->attach_done = true;198199free_clkdef(&sc->div_def.clkdef);200201bus_attach_children(sc->sc_dev);202return (0);203}204205static int206ti_divider_detach(device_t dev)207{208return (EBUSY);209}210211static void212ti_divider_new_pass(device_t dev)213{214struct ti_divider_softc *sc;215int err;216217sc = device_get_softc(dev);218219if (sc->attach_done) {220return;221}222223err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);224if (err) {225/* free_clkdef will be called in a later call to ti_divider_new_pass */226DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n");227return;228}229230err = register_clk(sc);231if (err) {232/* free_clkdef will be called in a later call to ti_divider_new_pass */233DPRINTF(sc->sc_dev, "new_pass register_clk failed\n");234return;235}236237sc->attach_done = true;238239free_clkdef(&sc->div_def.clkdef);240}241242static device_method_t ti_divider_methods[] = {243/* Device interface */244DEVMETHOD(device_probe, ti_divider_probe),245DEVMETHOD(device_attach, ti_divider_attach),246DEVMETHOD(device_detach, ti_divider_detach),247248/* Bus interface */249DEVMETHOD(bus_new_pass, ti_divider_new_pass),250251DEVMETHOD_END252};253254DEFINE_CLASS_0(ti_divider, ti_divider_driver, ti_divider_methods,255sizeof(struct ti_divider_softc));256257EARLY_DRIVER_MODULE(ti_divider, simplebus, ti_divider_driver, 0, 0,258BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);259MODULE_VERSION(ti_divider, 1);260261262