/*-1* Copyright (c) 20112* Ben Gray <[email protected]>.3* All rights reserved.4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8* 1. Redistributions of source code must retain the above copyright9* notice, this list of conditions and the following disclaimer.10* 2. Redistributions in binary form must reproduce the above copyright11* notice, this list of conditions and the following disclaimer in the12* documentation and/or other materials provided with the distribution.13*14* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND15* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE16* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE17* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE18* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL19* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS20* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)21* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT22* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY23* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF24* SUCH DAMAGE.25*/2627#ifndef TI_GPIO_H28#define TI_GPIO_H2930/* The maximum number of banks for any SoC */31#define MAX_GPIO_BANKS 63233/*34* Maximum GPIOS possible, max of *_MAX_GPIO_BANKS * *_INTR_PER_BANK.35* These are defined in ti_gpio.c36*/37#define MAX_GPIO_INTRS 83839struct ti_gpio_irqsrc {40struct intr_irqsrc tgi_isrc;41u_int tgi_irq;42uint32_t tgi_mask;43uint32_t tgi_mode;44};4546/**47* Structure that stores the driver context.48*49* This structure is allocated during driver attach.50*/51struct ti_gpio_softc {52device_t sc_dev;53device_t sc_busdev;54int sc_bank;55int sc_maxpin;56struct mtx sc_mtx;5758int sc_mem_rid;59struct resource *sc_mem_res;60int sc_irq_rid;61struct resource *sc_irq_res;62struct ti_gpio_irqsrc *sc_isrcs;63/* The handle for the register IRQ handlers. */64void *sc_irq_hdl;65};6667#endif /* TI_GPIO_H */686970