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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/sys/arm/ti/ti_i2c.h
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/*-

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 * SPDX-License-Identifier: BSD-2-Clause

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 *

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 * Copyright (c) 2011

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 *	Ben Gray <[email protected]>.

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 * All rights reserved.

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 *

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 * Redistribution and use in source and binary forms, with or without

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 * modification, are permitted provided that the following conditions

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 * are met:

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 * 1. Redistributions of source code must retain the above copyright

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 *    notice, this list of conditions and the following disclaimer.

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 * 2. Redistributions in binary form must reproduce the above copyright

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 *    notice, this list of conditions and the following disclaimer in the

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 *    documentation and/or other materials provided with the distribution.

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 *

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 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND

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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

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 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE

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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

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 * SUCH DAMAGE.

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 */

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#ifndef _TI_I2C_H_

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#define	_TI_I2C_H_

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/**

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 * Header file for the OMAP I2C driver.

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 *

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 * Simply contains register bit flags.

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 */

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/*

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 * OMAP4 I2C Registers, Summary 1

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 */

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#define	I2C_REG_IE		0x84

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#define		I2C_IE_XDR		(1UL << 14)   /* Transmit draining interrupt */

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#define		I2C_IE_RDR		(1UL << 13)   /* Receive draining interrupt */

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#define		I2C_IE_AAS		(1UL << 9)    /* Addressed as Slave interrupt */

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#define		I2C_IE_BF		(1UL << 8)    /* Bus Free interrupt */

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#define		I2C_IE_AERR		(1UL << 7)    /* Access Error interrupt */

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#define		I2C_IE_STC		(1UL << 6)    /* Start Condition interrupt */

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#define		I2C_IE_GC		(1UL << 5)    /* General Call interrupt */

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#define		I2C_IE_XRDY		(1UL << 4)    /* Transmit Data Ready interrupt */

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#define		I2C_IE_RRDY		(1UL << 3)    /* Receive Data Ready interrupt */

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#define		I2C_IE_ARDY		(1UL << 2)    /* Register Access Ready interrupt */

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#define		I2C_IE_NACK		(1UL << 1)    /* No Acknowledgment interrupt */

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#define		I2C_IE_AL		(1UL << 0)    /* Arbitration Lost interrupt */

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#define	I2C_REG_STAT		0x88

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#define		I2C_STAT_XDR		(1UL << 14)

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#define		I2C_STAT_RDR		(1UL << 13)

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#define		I2C_STAT_BB		(1UL << 12)

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#define		I2C_STAT_ROVR		(1UL << 11)

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#define		I2C_STAT_XUDF		(1UL << 10)

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#define		I2C_STAT_AAS		(1UL << 9)

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#define		I2C_STAT_BF		(1UL << 8)

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#define		I2C_STAT_AERR		(1UL << 7)

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#define		I2C_STAT_STC		(1UL << 6)

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#define		I2C_STAT_GC		(1UL << 5)

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#define		I2C_STAT_XRDY		(1UL << 4)

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#define		I2C_STAT_RRDY		(1UL << 3)

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#define		I2C_STAT_ARDY		(1UL << 2)

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#define		I2C_STAT_NACK		(1UL << 1)

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#define		I2C_STAT_AL		(1UL << 0)

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#define	I2C_REG_SYSS		0x90

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#define		I2C_SYSS_RDONE		(1UL << 0)

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#define	I2C_REG_BUF		0x94

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#define		I2C_BUF_RXFIFO_CLR	(1UL << 14)

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#define		I2C_BUF_TXFIFO_CLR	(1UL << 6)

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#define		I2C_BUF_RXTRSH_SHIFT	8

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#define		I2C_BUF_TRSH_MASK	0x3f

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#define	I2C_REG_CNT		0x98

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#define	I2C_REG_DATA		0x9c

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#define	I2C_REG_CON		0xa4

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#define		I2C_CON_I2C_EN		(1UL << 15)

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#define		I2C_CON_OPMODE_STD	(0UL << 12)

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#define		I2C_CON_OPMODE_HS	(1UL << 12)

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#define		I2C_CON_OPMODE_SCCB	(2UL << 12)

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#define		I2C_CON_OPMODE_MASK	(3UL << 13)

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#define		I2C_CON_I2C_STB		(1UL << 11)

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#define		I2C_CON_MST		(1UL << 10)

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#define		I2C_CON_TRX		(1UL << 9)

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#define		I2C_CON_XSA		(1UL << 8)

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#define		I2C_CON_XOA0		(1UL << 7)

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#define		I2C_CON_XOA1		(1UL << 6)

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#define		I2C_CON_XOA2		(1UL << 5)

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#define		I2C_CON_XOA3		(1UL << 4)

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#define		I2C_CON_STP		(1UL << 1)

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#define		I2C_CON_STT		(1UL << 0)

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#define	I2C_REG_OA0		0xa8

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#define	I2C_REG_SA		0xac

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#define	I2C_REG_PSC		0xb0

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#define		I2C_PSC_MASK		0xff

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#define	I2C_REG_SCLL		0xb4

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#define		I2C_SCLL_MASK		0xff

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#define		I2C_HSSCLL_SHIFT	8

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#define	I2C_REG_SCLH		0xb8

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#define		I2C_SCLH_MASK		0xff

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#define		I2C_HSSCLH_SHIFT	8

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#define	I2C_REG_SYSTEST		0xbc

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#define	I2C_REG_BUFSTAT		0xc0

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#define		I2C_BUFSTAT_FIFODEPTH_MASK	0x3

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#define		I2C_BUFSTAT_FIFODEPTH_SHIFT	14

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#define	I2C_REG_OA1		0xc4

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#define	I2C_REG_OA2		0xc8

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#define	I2C_REG_OA3		0xcc

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#define	I2C_REG_ACTOA		0xd0

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#define	I2C_REG_SBLOCK		0xd4

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/*

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 * OMAP4 I2C Registers, Summary 2 

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 */

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#define	I2C_REG_REVNB_LO	0x00

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#define	I2C_REG_REVNB_HI	0x04

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#define	I2C_REG_SYSC		0x10

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#define		I2C_REG_SYSC_SRST	(1UL << 1)

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#define	I2C_REG_STATUS_RAW	0x24

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#define	I2C_REG_STATUS		0x28

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#define	I2C_REG_IRQENABLE_SET	0x2C

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#define	I2C_REG_IRQENABLE_CLR	0x30

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#define	I2C_CLK			96000000UL	/* 96MHz */

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#define	I2C_ICLK		12000000UL	/* 12MHz */

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#endif /* _TI_I2C_H_ */

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