Path: blob/main/sys/arm64/cavium/thunder_pcie_fdt.c
39478 views
/*1* Copyright (C) 2016 Cavium Inc.2* All rights reserved.3*4* Developed by Semihalf.5*6* Redistribution and use in source and binary forms, with or without7* modification, are permitted provided that the following conditions8* are met:9* 1. Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer.11* 2. Redistributions in binary form must reproduce the above copyright12* notice, this list of conditions and the following disclaimer in the13* documentation and/or other materials provided with the distribution.14*15* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND16* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE17* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE18* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE19* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL20* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS21* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)22* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT23* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY24* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF25* SUCH DAMAGE.26*/27#include "opt_platform.h"2829#include <sys/param.h>30#include <sys/systm.h>31#include <sys/malloc.h>32#include <sys/types.h>33#include <sys/sysctl.h>34#include <sys/kernel.h>35#include <sys/rman.h>36#include <sys/module.h>37#include <sys/bus.h>38#include <sys/endian.h>39#include <sys/cpuset.h>4041#include <dev/ofw/openfirm.h>42#include <dev/ofw/ofw_bus.h>43#include <dev/ofw/ofw_bus_subr.h>4445#include <dev/pci/pcireg.h>46#include <dev/pci/pcivar.h>47#include <dev/pci/pci_host_generic.h>48#include <dev/pci/pci_host_generic_fdt.h>49#include <dev/pci/pcib_private.h>5051#include "thunder_pcie_common.h"5253#include "pcib_if.h"5455#ifdef THUNDERX_PASS_1_1_ERRATA56static struct resource * thunder_pcie_fdt_alloc_resource(device_t, device_t,57int, int *, rman_res_t, rman_res_t, rman_res_t, u_int);58static int thunder_pcie_fdt_release_resource(device_t, device_t,59struct resource*);60#endif61static int thunder_pcie_fdt_attach(device_t);62static int thunder_pcie_fdt_probe(device_t);63static int thunder_pcie_fdt_get_id(device_t, device_t, enum pci_id_type,64uintptr_t *);6566static const struct ofw_bus_devinfo *thunder_pcie_ofw_get_devinfo(device_t,67device_t);6869/* OFW bus interface */70struct thunder_pcie_ofw_devinfo {71struct ofw_bus_devinfo di_dinfo;72struct resource_list di_rl;73};7475static device_method_t thunder_pcie_fdt_methods[] = {76/* Device interface */77DEVMETHOD(device_probe, thunder_pcie_fdt_probe),78DEVMETHOD(device_attach, thunder_pcie_fdt_attach),79#ifdef THUNDERX_PASS_1_1_ERRATA80DEVMETHOD(bus_alloc_resource, thunder_pcie_fdt_alloc_resource),81DEVMETHOD(bus_release_resource, thunder_pcie_fdt_release_resource),82#endif8384/* pcib interface */85DEVMETHOD(pcib_get_id, thunder_pcie_fdt_get_id),8687/* ofw interface */88DEVMETHOD(ofw_bus_get_devinfo, thunder_pcie_ofw_get_devinfo),89DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),90DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),91DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),92DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),93DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),9495/* End */96DEVMETHOD_END97};9899DEFINE_CLASS_1(pcib, thunder_pcie_fdt_driver, thunder_pcie_fdt_methods,100sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver);101102DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_fdt_driver, 0, 0);103DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_fdt_driver, 0, 0);104105static const struct ofw_bus_devinfo *106thunder_pcie_ofw_get_devinfo(device_t bus __unused, device_t child)107{108struct thunder_pcie_ofw_devinfo *di;109110di = device_get_ivars(child);111return (&di->di_dinfo);112}113114static void115get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells)116{117118*addr_cells = 2;119/* Find address cells if present */120OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells));121122*size_cells = 2;123/* Find size cells if present */124OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells));125}126127static int128thunder_pcie_ofw_bus_attach(device_t dev)129{130struct thunder_pcie_ofw_devinfo *di;131device_t child;132phandle_t parent, node;133pcell_t addr_cells, size_cells;134135parent = ofw_bus_get_node(dev);136if (parent > 0) {137get_addr_size_cells(parent, &addr_cells, &size_cells);138/* Iterate through all bus subordinates */139for (node = OF_child(parent); node > 0; node = OF_peer(node)) {140/* Allocate and populate devinfo. */141di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);142if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {143free(di, M_DEVBUF);144continue;145}146147/* Initialize and populate resource list. */148resource_list_init(&di->di_rl);149ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells,150&di->di_rl);151ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL);152153/* Add newbus device for this FDT node */154child = device_add_child(dev, NULL, DEVICE_UNIT_ANY);155if (child == NULL) {156resource_list_free(&di->di_rl);157ofw_bus_gen_destroy_devinfo(&di->di_dinfo);158free(di, M_DEVBUF);159continue;160}161162device_set_ivars(child, di);163}164}165166return (0);167}168169static int170thunder_pcie_fdt_probe(device_t dev)171{172173/* Check if we're running on Cavium ThunderX */174if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,175CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0))176return (ENXIO);177178if (!ofw_bus_status_okay(dev))179return (ENXIO);180181if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic") ||182ofw_bus_is_compatible(dev, "cavium,thunder-pcie") ||183ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) {184device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller");185return (BUS_PROBE_DEFAULT);186}187188return (ENXIO);189}190191static int192thunder_pcie_fdt_attach(device_t dev)193{194struct generic_pcie_fdt_softc *sc;195196sc = device_get_softc(dev);197thunder_pcie_identify_ecam(dev, &sc->base.ecam);198sc->base.coherent = 1;199200/* Attach OFW bus */201if (thunder_pcie_ofw_bus_attach(dev) != 0)202return (ENXIO);203204return (pci_host_generic_fdt_attach(dev));205}206207static int208thunder_pcie_fdt_get_id(device_t pci, device_t child, enum pci_id_type type,209uintptr_t *id)210{211phandle_t node;212int bsf;213214if (type != PCI_ID_MSI)215return (pcib_get_id(pci, child, type, id));216217node = ofw_bus_get_node(pci);218if (OF_hasprop(node, "msi-map"))219return (generic_pcie_get_id(pci, child, type, id));220221bsf = pci_get_rid(child);222*id = (pci_get_domain(child) << PCI_RID_DOMAIN_SHIFT) | bsf;223224return (0);225}226227#ifdef THUNDERX_PASS_1_1_ERRATA228struct resource *229thunder_pcie_fdt_alloc_resource(device_t dev, device_t child, int type,230int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)231{232struct generic_pcie_fdt_softc *sc;233struct thunder_pcie_ofw_devinfo *di;234struct resource_list_entry *rle;235int i;236237/*238* For PCIe devices that do not have FDT nodes pass239* the request to the core driver.240*/241if ((int)ofw_bus_get_node(child) <= 0)242return (thunder_pcie_alloc_resource(dev, child, type,243rid, start, end, count, flags));244245/* For other devices use OFW method */246sc = device_get_softc(dev);247248if (RMAN_IS_DEFAULT_RANGE(start, end)) {249if ((di = device_get_ivars(child)) == NULL)250return (NULL);251if (type == SYS_RES_IOPORT)252type = SYS_RES_MEMORY;253254/* Find defaults for this rid */255rle = resource_list_find(&di->di_rl, type, *rid);256if (rle == NULL)257return (NULL);258259start = rle->start;260end = rle->end;261count = rle->count;262}263264if (type == SYS_RES_MEMORY) {265/* Remap through ranges property */266for (i = 0; i < MAX_RANGES_TUPLES; i++) {267if (start >= sc->base.ranges[i].phys_base &&268end < (sc->base.ranges[i].pci_base +269sc->base.ranges[i].size)) {270start -= sc->base.ranges[i].phys_base;271start += sc->base.ranges[i].pci_base;272end -= sc->base.ranges[i].phys_base;273end += sc->base.ranges[i].pci_base;274break;275}276}277278if (i == MAX_RANGES_TUPLES) {279device_printf(dev, "Could not map resource "280"%#jx-%#jx\n", start, end);281return (NULL);282}283}284285return (bus_generic_alloc_resource(dev, child, type, rid, start,286end, count, flags));287}288289static int290thunder_pcie_fdt_release_resource(device_t dev, device_t child,291struct resource *res)292{293294if ((int)ofw_bus_get_node(child) <= 0)295return (pci_host_generic_core_release_resource(dev, child,296res));297298return (bus_generic_release_resource(dev, child, res));299}300#endif301302303