Path: blob/main/sys/arm64/freescale/imx/imx_ccm.h
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2020 Oleksandr Tymoshenko <[email protected]>4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8* 1. Redistributions of source code must retain the above copyright9* notice, this list of conditions and the following disclaimer.10* 2. Redistributions in binary form must reproduce the above copyright11* notice, this list of conditions and the following disclaimer in the12* documentation and/or other materials provided with the distribution.13*14* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND15* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE16* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE17* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE18* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL19* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS20* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)21* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT22* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY23* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF24* SUCH DAMAGE.25*/2627#ifndef IMX8_CCM_H28#define IMX8_CCM_H2930#include <dev/clk/clk.h>31#include <dev/clk/clk_div.h>32#include <dev/clk/clk_fixed.h>33#include <dev/clk/clk_gate.h>34#include <dev/clk/clk_link.h>3536int imx_ccm_attach(device_t);37int imx_ccm_detach(device_t);3839struct imx_ccm_softc {40device_t dev;41struct resource *mem_res;42struct clkdom *clkdom;43struct mtx mtx;44struct imx_clk *clks;45int nclks;46};4748DECLARE_CLASS(imx_ccm_driver);4950enum imx_clk_type {51IMX_CLK_UNDEFINED = 0,52IMX_CLK_FIXED,53IMX_CLK_LINK,54IMX_CLK_MUX,55IMX_CLK_GATE,56IMX_CLK_COMPOSITE,57IMX_CLK_SSCG_PLL,58IMX_CLK_FRAC_PLL,59IMX_CLK_DIV,60};6162struct imx_clk {63enum imx_clk_type type;64union {65struct clk_fixed_def *fixed;66struct clk_link_def *link;67struct imx_clk_mux_def *mux;68struct imx_clk_gate_def *gate;69struct imx_clk_composite_def *composite;70struct imx_clk_sscg_pll_def *sscg_pll;71struct imx_clk_frac_pll_def *frac_pll;72struct clk_div_def *div;73} clk;74};7576/* Linked clock. */77#define LINK(_id, _name) \78{ \79.type = IMX_CLK_LINK, \80.clk.link = &(struct clk_link_def) { \81.clkdef.id = _id, \82.clkdef.name = _name, \83.clkdef.parent_names = NULL, \84.clkdef.parent_cnt = 0, \85.clkdef.flags = CLK_NODE_STATIC_STRINGS, \86}, \87}8889/* Complex clock without divider (multiplexer only). */90#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \91{ \92.type = IMX_CLK_MUX, \93.clk.mux = &(struct imx_clk_mux_def) { \94.clkdef.id = _id, \95.clkdef.name = _name, \96.clkdef.parent_names = _pn, \97.clkdef.parent_cnt = nitems(_pn), \98.clkdef.flags = CLK_NODE_STATIC_STRINGS, \99.offset = _mo, \100.shift = _ms, \101.width = _mw, \102.mux_flags = _f, \103}, \104}105106/* Fixed frequency clock */107#define FIXED(_id, _name, _freq) \108{ \109.type = IMX_CLK_FIXED, \110.clk.fixed = &(struct clk_fixed_def) { \111.clkdef.id = _id, \112.clkdef.name = _name, \113.clkdef.flags = CLK_NODE_STATIC_STRINGS, \114.freq = _freq, \115}, \116}117118/* Fixed factor multipier/divider. */119#define FFACT(_id, _name, _pname, _mult, _div) \120{ \121.type = IMX_CLK_FIXED, \122.clk.fixed = &(struct clk_fixed_def) { \123.clkdef.id = _id, \124.clkdef.name = _name, \125.clkdef.parent_names = (const char *[]){_pname}, \126.clkdef.parent_cnt = 1, \127.clkdef.flags = CLK_NODE_STATIC_STRINGS, \128.mult = _mult, \129.div = _div, \130}, \131}132133/* Clock gate */134#define GATE(_id, _name, _pname, _o, _shift) \135{ \136.type = IMX_CLK_GATE, \137.clk.gate = &(struct imx_clk_gate_def) { \138.clkdef.id = _id, \139.clkdef.name = _name, \140.clkdef.parent_names = (const char *[]){_pname}, \141.clkdef.parent_cnt = 1, \142.clkdef.flags = CLK_NODE_STATIC_STRINGS, \143.offset = _o, \144.shift = _shift, \145.mask = 1, \146}, \147}148149/* Root clock gate */150#define ROOT_GATE(_id, _name, _pname, _reg) \151{ \152.type = IMX_CLK_GATE, \153.clk.gate = &(struct imx_clk_gate_def) { \154.clkdef.id = _id, \155.clkdef.name = _name, \156.clkdef.parent_names = (const char *[]){_pname}, \157.clkdef.parent_cnt = 1, \158.clkdef.flags = CLK_NODE_STATIC_STRINGS, \159.offset = _reg, \160.shift = 0, \161.mask = 3, \162}, \163}164165/* Composite clock with GATE, MUX, PRE_DIV, and POST_DIV */166#define COMPOSITE(_id, _name, _pn, _o, _flags) \167{ \168.type = IMX_CLK_COMPOSITE, \169.clk.composite = &(struct imx_clk_composite_def) { \170.clkdef.id = _id, \171.clkdef.name = _name, \172.clkdef.parent_names = _pn, \173.clkdef.parent_cnt = nitems(_pn), \174.clkdef.flags = CLK_NODE_STATIC_STRINGS, \175.offset = _o, \176.flags = _flags, \177}, \178}179180/* SSCG PLL */181#define SSCG_PLL(_id, _name, _pn, _o) \182{ \183.type = IMX_CLK_SSCG_PLL, \184.clk.composite = &(struct imx_clk_composite_def) { \185.clkdef.id = _id, \186.clkdef.name = _name, \187.clkdef.parent_names = _pn, \188.clkdef.parent_cnt = nitems(_pn), \189.clkdef.flags = CLK_NODE_STATIC_STRINGS, \190.offset = _o, \191}, \192}193194/* Fractional PLL */195#define FRAC_PLL(_id, _name, _pname, _o) \196{ \197.type = IMX_CLK_FRAC_PLL, \198.clk.frac_pll = &(struct imx_clk_frac_pll_def) { \199.clkdef.id = _id, \200.clkdef.name = _name, \201.clkdef.parent_names = (const char *[]){_pname}, \202.clkdef.parent_cnt = 1, \203.clkdef.flags = CLK_NODE_STATIC_STRINGS, \204.offset = _o, \205}, \206}207208#define DIV(_id, _name, _pname, _o, _shift, _width) \209{ \210.type = IMX_CLK_DIV, \211.clk.div = &(struct clk_div_def) { \212.clkdef.id = _id, \213.clkdef.name = _name, \214.clkdef.parent_names = (const char *[]){_pname}, \215.clkdef.parent_cnt = 1, \216.clkdef.flags = CLK_NODE_STATIC_STRINGS, \217.offset = _o, \218.i_shift = _shift, \219.i_width = _width, \220}, \221}222223#endif /* IMX8_CCM_H */224225226