CoCalc -- vgic_v3

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/arm64/vmm/io/vgic_v3_reg.h
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/*-
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 * SPDX-License-Identifier: BSD-2-Clause
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 *
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 * Copyright (C) 2018 The FreeBSD Foundation
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 *
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 * This software was developed by Alexandru Elisei under sponsorship
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 * from the FreeBSD Foundation.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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#ifndef _VGIC_V3_REG_H_
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#define _VGIC_V3_REG_H_
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/* Interrupt Controller End of Interrupt Status Register */
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#define ICH_EISR_EL2_STATUS_MASK	0xffff
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#define ICH_EISR_EL2_EOI_NOT_HANDLED(lr)	((1 << lr) & ICH_EISR_EL2_STATUS_MASK)
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/* Interrupt Controller Empty List Register Status Register */
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#define ICH_ELSR_EL2_STATUS_MASK	0xffff
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#define ICH_ELSR_EL2_LR_EMPTY(x)	((1 << x) & ICH_ELSR_EL2_STATUS_MASK)
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/* Interrupt Controller Hyp Control Register */
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#define ICH_HCR_EL2_EOICOUNT_SHIFT	27
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#define ICH_HCR_EL2_EOICOUNT_MASK	(0x1f << ICH_HCR_EL2_EOICOUNT_SHIFT)
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#define ICH_HCR_EL2_TDIR		(1 << 14)	/* Trap non-secure EL1 writes to IC{C, V}_DIR_EL1 */
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#define ICH_HCR_EL2_TSEI		(1 << 14) 	/* Trap System Error Interupts (SEI) to EL2 */
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#define ICH_HCR_EL2_TALL1		(1 << 12) 	/* Trap non-secure EL1 accesses to IC{C, V}_* for Group 1 interrupts */
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#define ICH_HCR_EL2_TALL0		(1 << 11) 	/* Trap non-secure EL1 accesses to IC{C, V}_* for Group 0 interrupts */
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#define ICH_HCR_EL2_TC			(1 << 10) 	/* Trap non-secure EL1 accesses to common IC{C, V}_* registers */
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#define ICH_HCR_EL2_VGRP1DIE		(1 << 7) 	/* VM Group 1 Disabled Interrupt Enable */
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#define ICH_HCR_EL2_VGRP1EIE		(1 << 6)	/* VM Group 1 Enabled Interrupt Enable */
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#define ICH_HCR_EL2_VGRP0DIE		(1 << 5) 	/* VM Group 0 Disabled Interrupt Enable */
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#define ICH_HCR_EL2_VGRP0EIE		(1 << 4)	/* VM Group 0 Enabled Interrupt Enable */
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#define ICH_HCR_EL2_NPIE		(1 << 3)	/* No Pending Interrupt Enable */
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#define ICH_HCR_EL2_LRENPIE		(1 << 2)	/* List Register Entry Not Present Interrupt Enable */
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#define ICH_HCR_EL2_UIE			(1 << 1)	/* Underflow Interrupt Enable */
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#define ICH_HCR_EL2_En			(1 << 0)	/* Global enable for the virtual CPU interface */
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/* Interrupt Controller List Registers */
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#define ICH_LR_EL2_VINTID_MASK		0xffffffff
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#define	ICH_LR_EL2_VINTID(x)		((x) & ICH_LR_EL2_VINTID_MASK)
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#define ICH_LR_EL2_PINTID_SHIFT		32
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#define ICH_LR_EL2_PINTID_MASK		(0x3fUL << ICH_LR_EL2_PINTID_SHIFT)
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/* Raise a maintanance IRQ when deactivated (only non-HW virqs) */
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#define	ICH_LR_EL2_EOI			(1UL << 41)
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#define ICH_LR_EL2_PRIO_SHIFT		48
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#define ICH_LR_EL2_PRIO_MASK		(0xffUL << ICH_LR_EL2_PRIO_SHIFT)
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#define	ICH_LR_EL2_GROUP_SHIFT		60
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#define	ICH_LR_EL2_GROUP1		(1UL << ICH_LR_EL2_GROUP_SHIFT)
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#define ICH_LR_EL2_HW			(1UL << 61)
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#define ICH_LR_EL2_STATE_SHIFT		62
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#define ICH_LR_EL2_STATE_MASK		(0x3UL << ICH_LR_EL2_STATE_SHIFT)
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#define	ICH_LR_EL2_STATE(x)		((x) & ICH_LR_EL2_STATE_MASK)
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#define ICH_LR_EL2_STATE_INACTIVE	(0x0UL << ICH_LR_EL2_STATE_SHIFT)
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#define ICH_LR_EL2_STATE_PENDING	(0x1UL << ICH_LR_EL2_STATE_SHIFT)
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#define ICH_LR_EL2_STATE_ACTIVE		(0x2UL << ICH_LR_EL2_STATE_SHIFT)
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#define ICH_LR_EL2_STATE_PENDING_ACTIVE	(0x3UL << ICH_LR_EL2_STATE_SHIFT)
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/* Interrupt Controller Maintenance Interrupt State Register */
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#define ICH_MISR_EL2_VGRP1D		(1 << 7)	/* vPE Group 1 Disabled */
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#define ICH_MISR_EL2_VGRP1E		(1 << 6)	/* vPE Group 1 Enabled */
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#define ICH_MISR_EL2_VGRP0D		(1 << 5)	/* vPE Group 0 Disabled */
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#define ICH_MISR_EL2_VGRP0E		(1 << 4)	/* vPE Group 0 Enabled */
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#define ICH_MISR_EL2_NP			(1 << 3)	/* No Pending */
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#define ICH_MISR_EL2_LRENP		(1 << 2)	/* List Register Entry Not Present */
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#define ICH_MISR_EL2_U			(1 << 1)	/* Underflow */
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#define ICH_MISR_EL2_EOI		(1 << 0)	/* End Of Interrupt */
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/* Interrupt Controller Virtual Machine Control Register */
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#define ICH_VMCR_EL2_VPMR_SHIFT		24
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#define ICH_VMCR_EL2_VPMR_MASK		(0xff << ICH_VMCR_EL2_VPMR_SHIFT)
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#define  ICH_VMCR_EL2_VPMR_PRIO_LOWEST	(0xff << ICH_VMCR_EL2_VPMR_SHIFT)
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#define  ICH_VMCR_EL2_VPMR_PRIO_HIGHEST	(0x00 << ICH_VMCR_EL2_VPMR_SHIFT)
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#define ICH_VMCR_EL2_VBPR0_SHIFT	21
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#define ICH_VMCR_EL2_VBPR0_MASK		(0x7 << ICH_VMCR_EL2_VBPR0_SHIFT)
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#define  ICH_VMCR_EL2_VBPR0_NO_PREEMPTION \
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    (0x7 << ICH_VMCR_EL2_VBPR0_SHIFT)
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#define ICH_VMCR_EL2_VBPR1_SHIFT	18
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#define ICH_VMCR_EL2_VBPR1_MASK		(0x7 << ICH_VMCR_EL2_VBPR1_SHIFT)
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#define  ICH_VMCR_EL2_VBPR1_NO_PREEMPTION \
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    (0x7 << ICH_VMCR_EL2_VBPR1_SHIFT)
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#define ICH_VMCR_EL2_VEOIM		(1 << 9)	/* Virtual EOI mode */
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#define ICH_VMCR_EL2_VCBPR		(1 << 4)	/* Virtual Common binary Point Register */
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#define ICH_VMCR_EL2_VFIQEN		(1 << 3)	/* Virtual FIQ enable */
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#define ICH_VMCR_EL2_VACKCTL		(1 << 2)	/* Virtual AckCtl */
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#define ICH_VMCR_EL2_VENG1		(1 << 1)	/* Virtual Group 1 Interrupt Enable */
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#define ICH_VMCR_EL2_VENG0		(1 << 0)	/* Virtual Group 0 Interrupt Enable */
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/* Interrupt Controller VGIC Type Register */
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#define ICH_VTR_EL2_PRIBITS_SHIFT	29
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#define ICH_VTR_EL2_PRIBITS_MASK	(0x7 << ICH_VTR_EL2_PRIBITS_SHIFT)
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#define	ICH_VTR_EL2_PRIBITS(x)		\
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    ((((x) & ICH_VTR_EL2_PRIBITS_MASK) >> ICH_VTR_EL2_PRIBITS_SHIFT) + 1)
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#define ICH_VTR_EL2_PREBITS_SHIFT	26
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#define ICH_VTR_EL2_PREBITS_MASK	(0x7 << ICH_VTR_EL2_PREBITS_SHIFT)
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#define	ICH_VTR_EL2_PREBITS(x)		\
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    (((x) & ICH_VTR_EL2_PREBITS_MASK) >> ICH_VTR_EL2_PREBITS_SHIFT)
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#define ICH_VTR_EL2_SEIS		(1 << 22)	/* System Error Interrupt (SEI) Support */
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#define ICH_VTR_EL2_A3V			(1 << 21)	/* Affinity 3 Valid */
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#define ICH_VTR_EL2_NV4			(1 << 20)	/* Direct injection of virtual interrupts. RES1 for GICv3 */
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#define ICH_VTR_EL2_TDS			(1 << 19)	/* Implementation supports ICH_HCR_EL2.TDIR */
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#define ICH_VTR_EL2_LISTREGS_MASK	0x1f
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/*
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 * ICH_VTR_EL2.ListRegs holds the number of list registers, minus one. Add one
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 * to get the actual number of list registers.
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 */
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#define	ICH_VTR_EL2_LISTREGS(x)		(((x) & ICH_VTR_EL2_LISTREGS_MASK) + 1)
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#endif /* !_VGIC_V3_REG_H_ */
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