CoCalc -- ar9300reg.h

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h
⁴⁸⁵²⁵ views
1
/*
2
 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3
 *
4
 * Permission to use, copy, modify, and/or distribute this software for any
5
 * purpose with or without fee is hereby granted, provided that the above
6
 * copyright notice and this permission notice appear in all copies.
7
 *
8
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9
 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10
 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11
 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12
 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13
 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14
 * PERFORMANCE OF THIS SOFTWARE.
15
 */
16

17
#ifndef _DEV_ATH_AR9300REG_H
18
#define _DEV_ATH_AR9300REG_H
19

20
#include "osprey_reg_map.h"
21
#include "wasp_reg_map.h"
22

23
/******************************************************************************
24
 * MAC Register Map
25
******************************************************************************/
26
#define AR_MAC_DMA_OFFSET(_x)   offsetof(struct mac_dma_reg, _x)
27

28
/*
29
 * MAC DMA Registers
30
 */
31

32
/* MAC Control Register - only write values of 1 have effect */
33
#define AR_CR                AR_MAC_DMA_OFFSET(MAC_DMA_CR)
34
#define AR_CR_LP_RXE         0x00000004 // Receive LPQ enable
35
#define AR_CR_HP_RXE         0x00000008 // Receive HPQ enable
36
#define AR_CR_RXD            0x00000020 // Receive disable
37
#define AR_CR_SWI            0x00000040 // One-shot software interrupt
38
#define AR_CR_RXE            (AR_CR_LP_RXE|AR_CR_HP_RXE)
39

40
/* MAC configuration and status register */
41
#define AR_CFG               AR_MAC_DMA_OFFSET(MAC_DMA_CFG)
42
#define AR_CFG_SWTD          0x00000001 // byteswap tx descriptor words
43
#define AR_CFG_SWTB          0x00000002 // byteswap tx data buffer words
44
#define AR_CFG_SWRD          0x00000004 // byteswap rx descriptor words
45
#define AR_CFG_SWRB          0x00000008 // byteswap rx data buffer words
46
#define AR_CFG_SWRG          0x00000010 // byteswap register access data words
47
#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
48
#define AR_CFG_PHOK          0x00000100 // PHY OK status
49
#define AR_CFG_CLK_GATE_DIS  0x00000400 // Clock gating disable
50
#define AR_CFG_EEBS          0x00000200 // EEPROM busy
51
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH          0x00060000 // Mask of PCI core master request queue full threshold
52
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S        17         // Shift for PCI core master request queue full threshold
53
#define AR_CFG_MISSING_TX_INTR_FIX_ENABLE       0x00080000 // See EV 61133 for details.
54

55
/* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
56
#define AR_RXBP_THRESH          AR_MAC_DMA_OFFSET(MAC_DMA_RXBUFPTR_THRESH)
57
#define AR_RXBP_THRESH_HP       0x0000000f
58
#define AR_RXBP_THRESH_HP_S     0
59
#define AR_RXBP_THRESH_LP       0x00003f00
60
#define AR_RXBP_THRESH_LP_S     8
61

62
/* Tx DMA Descriptor Pointer Threshold register */
63
#define AR_TXDP_THRESH       AR_MAC_DMA_OFFSET(MAC_DMA_TXDPPTR_THRESH)
64

65
/* Mac Interrupt rate threshold register */
66
#define AR_MIRT              AR_MAC_DMA_OFFSET(MAC_DMA_MIRT)
67
#define AR_MIRT_VAL          0x0000ffff // in uS
68
#define AR_MIRT_VAL_S        16
69

70
/* MAC Global Interrupt enable register */
71
#define AR_IER               AR_MAC_DMA_OFFSET(MAC_DMA_GLOBAL_IER)
72
#define AR_IER_ENABLE        0x00000001 // Global interrupt enable
73
#define AR_IER_DISABLE       0x00000000 // Global interrupt disable
74

75
/* Mac Tx Interrupt mitigation threshold */
76
#define AR_TIMT              AR_MAC_DMA_OFFSET(MAC_DMA_TIMT)
77
#define AR_TIMT_LAST         0x0000ffff // Last packet threshold
78
#define AR_TIMT_LAST_S       0
79
#define AR_TIMT_FIRST        0xffff0000 // First packet threshold
80
#define AR_TIMT_FIRST_S      16
81

82
/* Mac Rx Interrupt mitigation threshold */
83
#define AR_RIMT              AR_MAC_DMA_OFFSET(MAC_DMA_RIMT)
84
#define AR_RIMT_LAST         0x0000ffff // Last packet threshold
85
#define AR_RIMT_LAST_S       0
86
#define AR_RIMT_FIRST        0xffff0000 // First packet threshold
87
#define AR_RIMT_FIRST_S      16
88

89
#define AR_DMASIZE_4B        0x00000000 // DMA size 4 bytes (TXCFG + RXCFG)
90
#define AR_DMASIZE_8B        0x00000001 // DMA size 8 bytes
91
#define AR_DMASIZE_16B       0x00000002 // DMA size 16 bytes
92
#define AR_DMASIZE_32B       0x00000003 // DMA size 32 bytes
93
#define AR_DMASIZE_64B       0x00000004 // DMA size 64 bytes
94
#define AR_DMASIZE_128B      0x00000005 // DMA size 128 bytes
95
#define AR_DMASIZE_256B      0x00000006 // DMA size 256 bytes
96
#define AR_DMASIZE_512B      0x00000007 // DMA size 512 bytes
97

98
/* MAC Tx DMA size config register */
99
#define AR_TXCFG             AR_MAC_DMA_OFFSET(MAC_DMA_TXCFG)
100
#define AR_TXCFG_DMASZ_MASK  0x00000007
101
#define AR_TXCFG_DMASZ_4B    0
102
#define AR_TXCFG_DMASZ_8B    1
103
#define AR_TXCFG_DMASZ_16B   2
104
#define AR_TXCFG_DMASZ_32B   3
105
#define AR_TXCFG_DMASZ_64B   4
106
#define AR_TXCFG_DMASZ_128B  5
107
#define AR_TXCFG_DMASZ_256B  6
108
#define AR_TXCFG_DMASZ_512B  7
109
#define AR_FTRIG             0x000003F0 // Mask for Frame trigger level
110
#define AR_FTRIG_S           4          // Shift for Frame trigger level
111
#define AR_FTRIG_IMMED       0x00000000 // bytes in PCU TX FIFO before air
112
#define AR_FTRIG_64B         0x00000010 // default
113
#define AR_FTRIG_128B        0x00000020
114
#define AR_FTRIG_192B        0x00000030
115
#define AR_FTRIG_256B        0x00000040 // 5 bits total
116
#define AR_FTRIG_512B        0x00000080 // 5 bits total
117
#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
118
#define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES     0x00080000
119
#define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES_S   19
120

121
/* MAC Rx DMA size config register */
122
#define AR_RXCFG             AR_MAC_DMA_OFFSET(MAC_DMA_RXCFG)
123
#define AR_RXCFG_CHIRP       0x00000008 // Only double chirps
124
#define AR_RXCFG_ZLFDMA      0x00000010 // Enable DMA of zero-length frame
125
#define AR_RXCFG_DMASZ_MASK  0x00000007
126
#define AR_RXCFG_DMASZ_4B    0
127
#define AR_RXCFG_DMASZ_8B    1
128
#define AR_RXCFG_DMASZ_16B   2
129
#define AR_RXCFG_DMASZ_32B   3
130
#define AR_RXCFG_DMASZ_64B   4
131
#define AR_RXCFG_DMASZ_128B  5
132
#define AR_RXCFG_DMASZ_256B  6
133
#define AR_RXCFG_DMASZ_512B  7
134

135
/* MAC Rx jumbo descriptor last address register */
136
#define AR_RXJLA             AR_MAC_DMA_OFFSET(MAC_DMA_RXJLA)
137

138

139
/* MAC MIB control register */
140
#define AR_MIBC              AR_MAC_DMA_OFFSET(MAC_DMA_MIBC)
141
#define AR_MIBC_COW          0x00000001 // counter overflow warning
142
#define AR_MIBC_FMC          0x00000002 // freeze MIB counters
143
#define AR_MIBC_CMC          0x00000004 // clear MIB counters
144
#define AR_MIBC_MCS          0x00000008 // MIB counter strobe increment all
145

146
/* MAC timeout prescale count */
147
#define AR_TOPS              AR_MAC_DMA_OFFSET(MAC_DMA_TOPS)
148
#define AR_TOPS_MASK         0x0000FFFF // Mask for timeout prescale
149

150
/* MAC no frame received timeout */
151
#define AR_RXNPTO            AR_MAC_DMA_OFFSET(MAC_DMA_RXNPTO)
152
#define AR_RXNPTO_MASK       0x000003FF // Mask for no frame received timeout
153

154
/* MAC no frame trasmitted timeout */
155
#define AR_TXNPTO            AR_MAC_DMA_OFFSET(MAC_DMA_TXNPTO)
156
#define AR_TXNPTO_MASK       0x000003FF // Mask for no frame transmitted timeout
157
#define AR_TXNPTO_QCU_MASK   0x000FFC00 // Mask indicating the set of QCUs
158
                                        // for which frame completions will cause
159
                                        // a reset of the no frame transmitted timeout
160

161
/* MAC receive frame gap timeout */
162
#define AR_RPGTO             AR_MAC_DMA_OFFSET(MAC_DMA_RPGTO)
163
#define AR_RPGTO_MASK        0x000003FF // Mask for receive frame gap timeout
164

165
/* MAC miscellaneous control/status register */
166
#define AR_MACMISC           AR_MAC_DMA_OFFSET(MAC_DMA_MACMISC)
167
#define AR_MACMISC_PCI_EXT_FORCE        0x00000010 //force msb to 10 to ahb
168
#define AR_MACMISC_DMA_OBS              0x000001E0 // Mask for DMA observation bus mux select
169
#define AR_MACMISC_DMA_OBS_S            5          // Shift for DMA observation bus mux select
170
#define AR_MACMISC_DMA_OBS_LINE_0       0          // Observation DMA line 0
171
#define AR_MACMISC_DMA_OBS_LINE_1       1          // Observation DMA line 1
172
#define AR_MACMISC_DMA_OBS_LINE_2       2          // Observation DMA line 2
173
#define AR_MACMISC_DMA_OBS_LINE_3       3          // Observation DMA line 3
174
#define AR_MACMISC_DMA_OBS_LINE_4       4          // Observation DMA line 4
175
#define AR_MACMISC_DMA_OBS_LINE_5       5          // Observation DMA line 5
176
#define AR_MACMISC_DMA_OBS_LINE_6       6          // Observation DMA line 6
177
#define AR_MACMISC_DMA_OBS_LINE_7       7          // Observation DMA line 7
178
#define AR_MACMISC_DMA_OBS_LINE_8       8          // Observation DMA line 8
179
#define AR_MACMISC_MISC_OBS             0x00000E00 // Mask for MISC observation bus mux select
180
#define AR_MACMISC_MISC_OBS_S           9          // Shift for MISC observation bus mux select
181
#define AR_MACMISC_MISC_OBS_BUS_LSB     0x00007000 // Mask for MAC observation bus mux select (lsb)
182
#define AR_MACMISC_MISC_OBS_BUS_LSB_S   12         // Shift for MAC observation bus mux select (lsb)
183
#define AR_MACMISC_MISC_OBS_BUS_MSB     0x00038000 // Mask for MAC observation bus mux select (msb)
184
#define AR_MACMISC_MISC_OBS_BUS_MSB_S   15         // Shift for MAC observation bus mux select (msb)
185
#define AR_MACMISC_MISC_OBS_BUS_1       1          // MAC observation bus mux select
186

187
/* MAC Interrupt Config register */
188
#define AR_INTCFG             AR_MAC_DMA_OFFSET(MAC_DMA_INTER)
189
#define AR_INTCFG_REQ         0x00000001    // Interrupt request flag
190
                                            // Indicates whether the DMA engine should generate
191
                                            // an interrupt upon completion of the frame
192
#define AR_INTCFG_MSI_RXOK    0x00000000    // Rx interrupt for MSI logic is RXOK
193
#define AR_INTCFG_MSI_RXINTM  0x00000004    // Rx interrupt for MSI logic is RXINTM
194
#define AR_INTCFG_MSI_RXMINTR 0x00000006    // Rx interrupt for MSI logic is RXMINTR
195
#define AR_INTCFG_MSI_TXOK    0x00000000    // Rx interrupt for MSI logic is TXOK
196
#define AR_INTCFG_MSI_TXINTM  0x00000010    // Rx interrupt for MSI logic is TXINTM
197
#define AR_INTCFG_MSI_TXMINTR 0x00000018    // Rx interrupt for MSI logic is TXMINTR
198

199
/* MAC DMA Data Buffer length, in bytes */
200
#define AR_DATABUF            AR_MAC_DMA_OFFSET(MAC_DMA_DATABUF)
201
#define AR_DATABUF_MASK       0x00000FFF
202

203
/* MAC global transmit timeout */
204
#define AR_GTXTO                    AR_MAC_DMA_OFFSET(MAC_DMA_GTT)
205
#define AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
206
#define AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in TUs)
207
#define AR_GTXTO_TIMEOUT_LIMIT_S    16          // Shift for timeout limit
208

209
/* MAC global transmit timeout mode */
210
#define AR_GTTM               AR_MAC_DMA_OFFSET(MAC_DMA_GTTM)
211
#define AR_GTTM_USEC          0x00000001 // usec strobe
212
#define AR_GTTM_IGNORE_IDLE   0x00000002 // ignore channel idle
213
#define AR_GTTM_RESET_IDLE    0x00000004 // reset counter on channel idle low
214
#define AR_GTTM_CST_USEC      0x00000008 // CST usec strobe
215

216
/* MAC carrier sense timeout */
217
#define AR_CST                    AR_MAC_DMA_OFFSET(MAC_DMA_CST)
218
#define AR_CST_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
219
#define AR_CST_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
220
#define AR_CST_TIMEOUT_LIMIT_S    16          // Shift for timeout limit
221

222
/* MAC Indicates the size of High and Low priority rx_dp FIFOs */
223
#define AR_RXDP_SIZE          AR_MAC_DMA_OFFSET(MAC_DMA_RXDP_SIZE)
224
#define AR_RXDP_LP_SZ_MASK    0x0000007f
225
#define AR_RXDP_LP_SZ_S       0
226
#define AR_RXDP_HP_SZ_MASK    0x00001f00
227
#define AR_RXDP_HP_SZ_S       8
228

229
/* MAC Rx High Priority Queue RXDP Pointer (lower 32 bits) */
230
#define AR_HP_RXDP            AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_HP_RXDP)
231

232
/* MAC Rx Low Priority Queue RXDP Pointer (lower 32 bits) */
233
#define AR_LP_RXDP            AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_LP_RXDP)
234

235

236
/* Primary Interrupt Status Register */
237
#define AR_ISR               AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P)
238
#define AR_ISR_HP_RXOK       0x00000001 // At least one frame rx on high-priority queue sans errors
239
#define AR_ISR_LP_RXOK       0x00000002 // At least one frame rx on low-priority queue sans errors
240
#define AR_ISR_RXERR         0x00000004 // Receive error interrupt
241
#define AR_ISR_RXNOPKT       0x00000008 // No frame received within timeout clock
242
#define AR_ISR_RXEOL         0x00000010 // Received descriptor empty interrupt
243
#define AR_ISR_RXORN         0x00000020 // Receive FIFO overrun interrupt
244
#define AR_ISR_TXOK          0x00000040 // Transmit okay interrupt
245
#define AR_ISR_TXERR         0x00000100 // Transmit error interrupt
246
#define AR_ISR_TXNOPKT       0x00000200 // No frame transmitted interrupt
247
#define AR_ISR_TXEOL         0x00000400 // Transmit descriptor empty interrupt
248
#define AR_ISR_TXURN         0x00000800 // Transmit FIFO underrun interrupt
249
#define AR_ISR_MIB           0x00001000 // MIB interrupt - see MIBC
250
#define AR_ISR_SWI           0x00002000 // Software interrupt
251
#define AR_ISR_RXPHY         0x00004000 // PHY receive error interrupt
252
#define AR_ISR_RXKCM         0x00008000 // Key-cache miss interrupt
253
#define AR_ISR_SWBA          0x00010000 // Software beacon alert interrupt
254
#define AR_ISR_BRSSI         0x00020000 // Beacon threshold interrupt
255
#define AR_ISR_BMISS         0x00040000 // Beacon missed interrupt
256
#define AR_ISR_TXMINTR       0x00080000 // Maximum interrupt transmit rate
257
#define AR_ISR_BNR           0x00100000 // Beacon not ready interrupt
258
#define AR_ISR_RXCHIRP       0x00200000 // Phy received a 'chirp'
259
#define AR_ISR_HCFPOLL       0x00400000 // Received directed HCF poll
260
#define AR_ISR_BCNMISC       0x00800000 // CST, GTT, TIM, CABEND, DTIMSYNC, BCNTO, CABTO,
261
                                        // TSFOOR, DTIM, and TBTT_TIME bits bits from ISR_S2
262
#define AR_ISR_TIM           0x00800000 // TIM interrupt
263
#define AR_ISR_RXMINTR       0x01000000 // Maximum interrupt receive rate
264
#define AR_ISR_QCBROVF       0x02000000 // QCU CBR overflow interrupt
265
#define AR_ISR_QCBRURN       0x04000000 // QCU CBR underrun interrupt
266
#define AR_ISR_QTRIG         0x08000000 // QCU scheduling trigger interrupt
267
#define AR_ISR_GENTMR        0x10000000 // OR of generic timer bits in ISR 5
268
#define AR_ISR_HCFTO         0x20000000 // HCF poll timeout
269
#define AR_ISR_TXINTM        0x40000000 // Tx interrupt after mitigation
270
#define AR_ISR_RXINTM        0x80000000 // Rx interrupt after mitigation
271

272
/* MAC Secondary interrupt status register 0 */
273
#define AR_ISR_S0               AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0)
274
#define AR_ISR_S0_QCU_TXOK      0x000003FF // Mask for TXOK (QCU 0-9)
275
#define AR_ISR_S0_QCU_TXOK_S    0          // Shift for TXOK (QCU 0-9)
276

277
/* MAC Secondary interrupt status register 1 */
278
#define AR_ISR_S1              AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1)
279
#define AR_ISR_S1_QCU_TXERR    0x000003FF // Mask for TXERR (QCU 0-9)
280
#define AR_ISR_S1_QCU_TXERR_S  0          // Shift for TXERR (QCU 0-9)
281
#define AR_ISR_S1_QCU_TXEOL    0x03FF0000 // Mask for TXEOL (QCU 0-9)
282
#define AR_ISR_S1_QCU_TXEOL_S  16         // Shift for TXEOL (QCU 0-9)
283

284
/* MAC Secondary interrupt status register 2 */
285
#define AR_ISR_S2              AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2)
286
#define AR_ISR_S2_QCU_TXURN    0x000003FF // Mask for TXURN (QCU 0-9)
287
#define AR_ISR_S2_BBPANIC      0x00010000 // Panic watchdog IRQ from BB
288
#define AR_ISR_S2_CST          0x00400000 // Carrier sense timeout
289
#define AR_ISR_S2_GTT          0x00800000 // Global transmit timeout
290
#define AR_ISR_S2_TIM          0x01000000 // TIM
291
#define AR_ISR_S2_CABEND       0x02000000 // CABEND
292
#define AR_ISR_S2_DTIMSYNC     0x04000000 // DTIMSYNC
293
#define AR_ISR_S2_BCNTO        0x08000000 // BCNTO
294
#define AR_ISR_S2_CABTO        0x10000000 // CABTO
295
#define AR_ISR_S2_DTIM         0x20000000 // DTIM
296
#define AR_ISR_S2_TSFOOR       0x40000000 // Rx TSF out of range
297
#define AR_ISR_S2_TBTT_TIME    0x80000000 // TBTT-referenced timer
298

299
/* MAC Secondary interrupt status register 3 */
300
#define AR_ISR_S3                AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3)
301
#define AR_ISR_S3_QCU_QCBROVF    0x000003FF // Mask for QCBROVF (QCU 0-9)
302
#define AR_ISR_S3_QCU_QCBRURN    0x03FF0000 // Mask for QCBRURN (QCU 0-9)
303

304
/* MAC Secondary interrupt status register 4 */
305
#define AR_ISR_S4              AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4)
306
#define AR_ISR_S4_QCU_QTRIG    0x000003FF // Mask for QTRIG (QCU 0-9)
307
#define AR_ISR_S4_RESV0        0xFFFFFC00 // Reserved
308

309
/* MAC Secondary interrupt status register 5 */
310
#define AR_ISR_S5                   AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5)
311
#define AR_ISR_S5_TIMER_TRIG        0x000000FF // Mask for timer trigger (0-7)
312
#define AR_ISR_S5_TIMER_THRESH      0x0007FE00 // Mask for timer threshold(0-7)
313
#define AR_ISR_S5_TIM_TIMER         0x00000010 // TIM Timer ISR
314
#define AR_ISR_S5_DTIM_TIMER        0x00000020 // DTIM Timer ISR
315
#define AR_ISR_S5_GENTIMER_TRIG     0x0000FF80 // ISR for generic timer trigger 7
316
#define AR_ISR_S5_GENTIMER_TRIG_S   0
317
#define AR_ISR_S5_GENTIMER_THRESH   0xFF800000 // ISR for generic timer threshold 7
318
#define AR_ISR_S5_GENTIMER_THRESH_S 16
319

320
/* Primary Interrupt Mask Register */
321
#define AR_IMR               AR_MAC_DMA_OFFSET(MAC_DMA_IMR_P)
322
#define AR_IMR_RXOK_HP       0x00000001 // Receive high-priority interrupt enable mask
323
#define AR_IMR_RXOK_LP       0x00000002 // Receive low-priority interrupt enable mask
324
#define AR_IMR_RXERR         0x00000004 // Receive error interrupt
325
#define AR_IMR_RXNOPKT       0x00000008 // No frame received within timeout clock
326
#define AR_IMR_RXEOL         0x00000010 // Received descriptor empty interrupt
327
#define AR_IMR_RXORN         0x00000020 // Receive FIFO overrun interrupt
328
#define AR_IMR_TXOK          0x00000040 // Transmit okay interrupt
329
#define AR_IMR_TXERR         0x00000100 // Transmit error interrupt
330
#define AR_IMR_TXNOPKT       0x00000200 // No frame transmitted interrupt
331
#define AR_IMR_TXEOL         0x00000400 // Transmit descriptor empty interrupt
332
#define AR_IMR_TXURN         0x00000800 // Transmit FIFO underrun interrupt
333
#define AR_IMR_MIB           0x00001000 // MIB interrupt - see MIBC
334
#define AR_IMR_SWI           0x00002000 // Software interrupt
335
#define AR_IMR_RXPHY         0x00004000 // PHY receive error interrupt
336
#define AR_IMR_RXKCM         0x00008000 // Key-cache miss interrupt
337
#define AR_IMR_SWBA          0x00010000 // Software beacon alert interrupt
338
#define AR_IMR_BRSSI         0x00020000 // Beacon threshold interrupt
339
#define AR_IMR_BMISS         0x00040000 // Beacon missed interrupt
340
#define AR_IMR_TXMINTR       0x00080000 // Maximum interrupt transmit rate
341
#define AR_IMR_BNR           0x00100000 // BNR interrupt
342
#define AR_IMR_RXCHIRP       0x00200000 // RXCHIRP interrupt
343
#define AR_IMR_BCNMISC       0x00800000 // Venice: BCNMISC
344
#define AR_IMR_TIM           0x00800000 // TIM interrupt
345
#define AR_IMR_RXMINTR       0x01000000 // Maximum interrupt receive rate
346
#define AR_IMR_QCBROVF       0x02000000 // QCU CBR overflow interrupt
347
#define AR_IMR_QCBRURN       0x04000000 // QCU CBR underrun interrupt
348
#define AR_IMR_QTRIG         0x08000000 // QCU scheduling trigger interrupt
349
#define AR_IMR_GENTMR        0x10000000 // Generic timer interrupt
350
#define AR_IMR_TXINTM        0x40000000 // Tx interrupt after mitigation
351
#define AR_IMR_RXINTM        0x80000000 // Rx interrupt after mitigation
352

353
/* MAC Secondary interrupt mask register 0 */
354
#define AR_IMR_S0               AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S0)
355
#define AR_IMR_S0_QCU_TXOK      0x000003FF // Mask for TXOK (QCU 0-9)
356
#define AR_IMR_S0_QCU_TXOK_S    0          // Shift for TXOK (QCU 0-9)
357

358
/* MAC Secondary interrupt mask register 1 */
359
#define AR_IMR_S1              AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S1)
360
#define AR_IMR_S1_QCU_TXERR    0x000003FF // Mask for TXERR (QCU 0-9)
361
#define AR_IMR_S1_QCU_TXERR_S  0          // Shift for TXERR (QCU 0-9)
362
#define AR_IMR_S1_QCU_TXEOL    0x03FF0000 // Mask for TXEOL (QCU 0-9)
363
#define AR_IMR_S1_QCU_TXEOL_S  16         // Shift for TXEOL (QCU 0-9)
364

365
/* MAC Secondary interrupt mask register 2 */
366
#define AR_IMR_S2              AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S2)
367
#define AR_IMR_S2_QCU_TXURN    0x000003FF // Mask for TXURN (QCU 0-9)
368
#define AR_IMR_S2_QCU_TXURN_S  0          // Shift for TXURN (QCU 0-9)
369
#define AR_IMR_S2_BBPANIC      0x00010000 // Panic watchdog IRQ from BB
370
#define AR_IMR_S2_CST          0x00400000 // Carrier sense timeout
371
#define AR_IMR_S2_GTT          0x00800000 // Global transmit timeout
372
#define AR_IMR_S2_TIM          0x01000000 // TIM
373
#define AR_IMR_S2_CABEND       0x02000000 // CABEND
374
#define AR_IMR_S2_DTIMSYNC     0x04000000 // DTIMSYNC
375
#define AR_IMR_S2_BCNTO        0x08000000 // BCNTO
376
#define AR_IMR_S2_CABTO        0x10000000 // CABTO
377
#define AR_IMR_S2_DTIM         0x20000000 // DTIM
378
#define AR_IMR_S2_TSFOOR       0x40000000 // TSF out of range
379

380
/* MAC Secondary interrupt mask register 3 */
381
#define AR_IMR_S3                AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S3)
382
#define AR_IMR_S3_QCU_QCBROVF    0x000003FF // Mask for QCBROVF (QCU 0-9)
383
#define AR_IMR_S3_QCU_QCBRURN    0x03FF0000 // Mask for QCBRURN (QCU 0-9)
384
#define AR_IMR_S3_QCU_QCBRURN_S  16         // Shift for QCBRURN (QCU 0-9)
385

386
/* MAC Secondary interrupt mask register 4 */
387
#define AR_IMR_S4              AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S4)
388
#define AR_IMR_S4_QCU_QTRIG    0x000003FF // Mask for QTRIG (QCU 0-9)
389
#define AR_IMR_S4_RESV0        0xFFFFFC00 // Reserved
390

391
/* MAC Secondary interrupt mask register 5 */
392
#define AR_IMR_S5                   AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S5)
393
#define AR_IMR_S5_TIMER_TRIG        0x000000FF // Mask for timer trigger (0-7)
394
#define AR_IMR_S5_TIMER_THRESH      0x0000FF00 // Mask for timer threshold(0-7)
395
#define AR_IMR_S5_TIM_TIMER         0x00000010 // TIM Timer Mask
396
#define AR_IMR_S5_DTIM_TIMER        0x00000020 // DTIM Timer Mask
397
#define AR_IMR_S5_GENTIMER7         0x00000080 // Mask for timer 7 trigger
398
#define AR_IMR_S5_GENTIMER_TRIG     0x0000FF80 // Mask for generic timer trigger 7-15
399
#define AR_IMR_S5_GENTIMER_TRIG_S   0
400
#define AR_IMR_S5_GENTIMER_THRESH   0xFF800000 // Mask for generic timer threshold 7-15
401
#define AR_IMR_S5_GENTIMER_THRESH_S 16
402

403

404
/* Interrupt status registers (read-and-clear access secondary shadow copies) */
405

406
/* MAC Primary interrupt status register read-and-clear access */
407
#define AR_ISR_RAC      AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P_RAC)
408
/* MAC Secondary interrupt status register 0 - shadow copy */
409
#define AR_ISR_S0_S     AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0_S)
410
#define AR_ISR_S0_QCU_TXOK      0x000003FF // Mask for TXOK (QCU 0-9)
411
#define AR_ISR_S0_QCU_TXOK_S    0          // Shift for TXOK (QCU 0-9)
412

413
/* MAC Secondary interrupt status register 1 - shadow copy */
414
#define AR_ISR_S1_S            AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1_S)
415
#define AR_ISR_S1_QCU_TXERR    0x000003FF // Mask for TXERR (QCU 0-9)
416
#define AR_ISR_S1_QCU_TXERR_S  0          // Shift for TXERR (QCU 0-9)
417
#define AR_ISR_S1_QCU_TXEOL    0x03FF0000 // Mask for TXEOL (QCU 0-9)
418
#define AR_ISR_S1_QCU_TXEOL_S  16         // Shift for TXEOL (QCU 0-9)
419

420
/* MAC Secondary interrupt status register 2 - shadow copy */
421
#define AR_ISR_S2_S           AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2_S)
422
/* MAC Secondary interrupt status register 3 - shadow copy */
423
#define AR_ISR_S3_S           AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3_S)
424
/* MAC Secondary interrupt status register 4 - shadow copy */
425
#define AR_ISR_S4_S           AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4_S)
426
/* MAC Secondary interrupt status register 5 - shadow copy */
427
#define AR_ISR_S5_S           AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5_S)
428

429
/* MAC DMA Debug Registers */
430
#define AR_DMADBG_0           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_0)
431
#define AR_DMADBG_1           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_1)
432
#define AR_DMADBG_2           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_2)
433
#define AR_DMADBG_3           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_3)
434
#define AR_DMADBG_4           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_4)
435
#define AR_DMADBG_5           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_5)
436
#define AR_DMADBG_6           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_6)
437
#define AR_DMADBG_7           AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_7)
438
#define AR_DMATXDP_QCU_7_0    AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0)
439
#define AR_DMATXDP_QCU_9_8    AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8)
440

441
#define AR_DMADBG_RX_STATE    0x00000F00 // Mask for Rx DMA State machine
442

443

444
/*
445
 * MAC QCU Registers
446
 */
447
#define AR_MAC_QCU_OFFSET(_x)   offsetof(struct mac_qcu_reg, _x)
448

449
#define AR_NUM_QCU      10     // Only use QCU 0-9 for forward QCU compatibility
450
#define AR_QCU_0        0x0001
451
#define AR_QCU_1        0x0002
452
#define AR_QCU_2        0x0004
453
#define AR_QCU_3        0x0008
454
#define AR_QCU_4        0x0010
455
#define AR_QCU_5        0x0020
456
#define AR_QCU_6        0x0040
457
#define AR_QCU_7        0x0080
458
#define AR_QCU_8        0x0100
459
#define AR_QCU_9        0x0200
460

461
/* MAC Transmit Queue descriptor pointer */
462
#define AR_Q0_TXDP      AR_MAC_QCU_OFFSET(MAC_QCU_TXDP)
463
#define AR_QTXDP(_i)    (AR_Q0_TXDP + ((_i)<<2))
464

465
/* MAC Transmit Status Ring Start Address */
466
#define AR_Q_STATUS_RING_START    AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_START)
467
/* MAC Transmit Status Ring End Address */
468
#define AR_Q_STATUS_RING_END      AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_END)
469
/* Current Address in the Transmit Status Ring pointed to by the MAC */
470
#define AR_Q_STATUS_RING_CURRENT  AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_CURRENT)
471

472
/* MAC Transmit Queue enable */
473
#define AR_Q_TXE             AR_MAC_QCU_OFFSET(MAC_QCU_TXE)
474
#define AR_Q_TXE_M           0x000003FF // Mask for TXE (QCU 0-9)
475

476
/* MAC Transmit Queue disable */
477
#define AR_Q_TXD             AR_MAC_QCU_OFFSET(MAC_QCU_TXD)
478
#define AR_Q_TXD_M           0x000003FF // Mask for TXD (QCU 0-9)
479

480
/* MAC CBR configuration */
481
#define AR_Q0_CBRCFG         AR_MAC_QCU_OFFSET(MAC_QCU_CBR)
482
#define AR_QCBRCFG(_i)      (AR_Q0_CBRCFG + ((_i)<<2))
483
#define AR_Q_CBRCFG_INTERVAL     0x00FFFFFF // Mask for CBR interval (us)
484
#define AR_Q_CBRCFG_INTERVAL_S   0          // Shift for CBR interval (us)
485
#define AR_Q_CBRCFG_OVF_THRESH   0xFF000000 // Mask for CBR overflow threshold
486
#define AR_Q_CBRCFG_OVF_THRESH_S 24         // Shift for CBR overflow threshold
487

488
/* MAC ready_time configuration */
489
#define AR_Q0_RDYTIMECFG         AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME)
490
#define AR_QRDYTIMECFG(_i)       (AR_Q0_RDYTIMECFG + ((_i)<<2))
491
#define AR_Q_RDYTIMECFG_DURATION   0x00FFFFFF // Mask for ready_time duration (us)
492
#define AR_Q_RDYTIMECFG_DURATION_S 0          // Shift for ready_time duration (us)
493
#define AR_Q_RDYTIMECFG_EN         0x01000000 // ready_time enable
494

495
/* MAC OneShotArm set control */
496
#define AR_Q_ONESHOTARM_SC       AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_SC)
497
#define AR_Q_ONESHOTARM_SC_M     0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9)
498
#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved
499

500
/* MAC OneShotArm clear control */
501
#define AR_Q_ONESHOTARM_CC       AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_CC)
502
#define AR_Q_ONESHOTARM_CC_M     0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9)
503
#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved
504

505
/* MAC Miscellaneous QCU settings */
506
#define AR_Q0_MISC                        AR_MAC_QCU_OFFSET(MAC_QCU_MISC)
507
#define AR_QMISC(_i)                      (AR_Q0_MISC + ((_i)<<2))
508
#define AR_Q_MISC_FSP                     0x0000000F // Mask for Frame Scheduling Policy
509
#define AR_Q_MISC_FSP_S                   0
510
#define AR_Q_MISC_FSP_ASAP                0          // ASAP
511
#define AR_Q_MISC_FSP_CBR                 1          // CBR
512
#define AR_Q_MISC_FSP_DBA_GATED           2          // DMA Beacon Alert gated
513
#define AR_Q_MISC_FSP_TIM_GATED           3          // TIM gated
514
#define AR_Q_MISC_FSP_BEACON_SENT_GATED   4          // Beacon-sent-gated
515
#define AR_Q_MISC_FSP_BEACON_RCVD_GATED   5          // Beacon-received-gated
516
#define AR_Q_MISC_ONE_SHOT_EN             0x00000010 // OneShot enable
517
#define AR_Q_MISC_CBR_INCR_DIS1           0x00000020 // Disable CBR expired counter incr (empty q)
518
#define AR_Q_MISC_CBR_INCR_DIS0           0x00000040 // Disable CBR expired counter incr (empty beacon q)
519
#define AR_Q_MISC_BEACON_USE              0x00000080 // Beacon use indication
520
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN   0x00000100 // CBR expired counter limit enable
521
#define AR_Q_MISC_RDYTIME_EXP_POLICY      0x00000200 // Enable TXE cleared on ready_time expired or VEOL
522
#define AR_Q_MISC_RESET_CBR_EXP_CTR       0x00000400 // Reset CBR expired counter
523
#define AR_Q_MISC_DCU_EARLY_TERM_REQ      0x00000800 // DCU frame early termination request control
524
#define AR_Q_MISC_RESV0                   0xFFFFF000 // Reserved
525

526
/* MAC Miscellaneous QCU status */
527
#define AR_Q0_STS                     AR_MAC_QCU_OFFSET(MAC_QCU_CNT)
528
#define AR_QSTS(_i)                   (AR_Q0_STS + ((_i)<<2))
529
#define AR_Q_STS_PEND_FR_CNT          0x00000003 // Mask for Pending Frame Count
530
#define AR_Q_STS_RESV0                0x000000FC // Reserved
531
#define AR_Q_STS_CBR_EXP_CNT          0x0000FF00 // Mask for CBR expired counter
532
#define AR_Q_STS_RESV1                0xFFFF0000 // Reserved
533

534
/* MAC ReadyTimeShutdown status */
535
#define AR_Q_RDYTIMESHDN    AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME_SHDN)
536
#define AR_Q_RDYTIMESHDN_M  0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9)
537

538
/* MAC Descriptor CRC check */
539
#define AR_Q_DESC_CRCCHK    AR_MAC_QCU_OFFSET(MAC_QCU_DESC_CRC_CHK)
540
#define AR_Q_DESC_CRCCHK_EN 1 // Enable CRC check on the descriptor fetched from HOST
541

542
#define AR_MAC_QCU_EOL      AR_MAC_QCU_OFFSET(MAC_QCU_EOL)
543
#define AR_MAC_QCU_EOL_DUR_CAL_EN   0x000003FF // Adjusts EOL for frame duration (QCU 0-9) 
544
#define AR_MAC_QCU_EOL_DUR_CAL_EN_S 0
545

546
/*
547
 * MAC DCU Registers
548
 */
549

550
#define AR_MAC_DCU_OFFSET(_x)   offsetof(struct mac_dcu_reg, _x)
551

552
#define AR_NUM_DCU      10     // Only use 10 DCU's for forward QCU/DCU compatibility
553
#define AR_DCU_0        0x0001
554
#define AR_DCU_1        0x0002
555
#define AR_DCU_2        0x0004
556
#define AR_DCU_3        0x0008
557
#define AR_DCU_4        0x0010
558
#define AR_DCU_5        0x0020
559
#define AR_DCU_6        0x0040
560
#define AR_DCU_7        0x0080
561
#define AR_DCU_8        0x0100
562
#define AR_DCU_9        0x0200
563

564
/* MAC QCU Mask */
565
#define AR_D0_QCUMASK     AR_MAC_DCU_OFFSET(MAC_DCU_QCUMASK)
566
#define AR_DQCUMASK(_i)   (AR_D0_QCUMASK + ((_i)<<2))
567
#define AR_D_QCUMASK         0x000003FF // Mask for QCU Mask (QCU 0-9)
568
#define AR_D_QCUMASK_RESV0   0xFFFFFC00 // Reserved
569

570
/* DCU transmit filter cmd (w/only) */
571
#define AR_D_TXBLK_CMD  AR_MAC_DCU_OFFSET(MAC_DCU_TXFILTER_DCU0_31_0)
572
#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) // DCU transmit filter data
573

574

575
/* MAC DCU-global IFS settings: SIFS duration */
576
#define AR_D_GBL_IFS_SIFS         AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SIFS)
577
#define AR_D_GBL_IFS_SIFS_M       0x0000FFFF // Mask for SIFS duration (core clocks)
578
#define AR_D_GBL_IFS_SIFS_RESV0   0xFFFFFFFF // Reserved
579

580
/* MAC DCU-global IFS settings: slot duration */
581
#define AR_D_GBL_IFS_SLOT         AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SLOT)
582
#define AR_D_GBL_IFS_SLOT_M       0x0000FFFF // Mask for Slot duration (core clocks)
583
#define AR_D_GBL_IFS_SLOT_RESV0   0xFFFF0000 // Reserved
584

585
/* MAC Retry limits */
586
#define AR_D0_RETRY_LIMIT     AR_MAC_DCU_OFFSET(MAC_DCU_RETRY_LIMIT)
587
#define AR_DRETRY_LIMIT(_i)   (AR_D0_RETRY_LIMIT + ((_i)<<2))
588
#define AR_D_RETRY_LIMIT_FR_SH       0x0000000F // Mask for frame short retry limit
589
#define AR_D_RETRY_LIMIT_FR_SH_S     0          // Shift for frame short retry limit
590
#define AR_D_RETRY_LIMIT_STA_SH      0x00003F00 // Mask for station short retry limit
591
#define AR_D_RETRY_LIMIT_STA_SH_S    8          // Shift for station short retry limit
592
#define AR_D_RETRY_LIMIT_STA_LG      0x000FC000 // Mask for station short retry limit
593
#define AR_D_RETRY_LIMIT_STA_LG_S    14         // Shift for station short retry limit
594
#define AR_D_RETRY_LIMIT_RESV0       0xFFF00000 // Reserved
595

596
/* MAC DCU-global IFS settings: EIFS duration */
597
#define AR_D_GBL_IFS_EIFS         AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_EIFS)
598
#define AR_D_GBL_IFS_EIFS_M       0x0000FFFF // Mask for Slot duration (core clocks)
599
#define AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000 // Reserved
600

601
/* MAC ChannelTime settings */
602
#define AR_D0_CHNTIME     AR_MAC_DCU_OFFSET(MAC_DCU_CHANNEL_TIME)
603
#define AR_DCHNTIME(_i)   (AR_D0_CHNTIME + ((_i)<<2))
604
#define AR_D_CHNTIME_DUR         0x000FFFFF // Mask for ChannelTime duration (us)
605
#define AR_D_CHNTIME_DUR_S       0          // Shift for ChannelTime duration (us)
606
#define AR_D_CHNTIME_EN          0x00100000 // ChannelTime enable
607
#define AR_D_CHNTIME_RESV0       0xFFE00000 // Reserved
608

609
/* MAC DCU-global IFS settings: Miscellaneous */
610
#define AR_D_GBL_IFS_MISC        AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_MISC)
611
#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL        0x00000007 // Mask forLFSR slice select
612
#define AR_D_GBL_IFS_MISC_TURBO_MODE            0x00000008 // Turbo mode indication
613
#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY       0x00300000 // Mask for DCU arbiter delay
614
#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable
615
#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN    0x06000000 // Slot transmission window length mask
616
#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries
617
#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF        0x10000000 // Ignore backoff
618

619
/* MAC Miscellaneous DCU-specific settings */
620
#define AR_D0_MISC        AR_MAC_DCU_OFFSET(MAC_DCU_MISC)
621
#define AR_DMISC(_i)      (AR_D0_MISC + ((_i)<<2))
622
#define AR_D_MISC_BKOFF_THRESH        0x0000003F // Mask for Backoff threshold setting
623
#define AR_D_MISC_RETRY_CNT_RESET_EN  0x00000040 // End of tx series station RTS/data failure count reset policy
624
#define AR_D_MISC_CW_RESET_EN         0x00000080 // End of tx series CW reset enable
625
#define AR_D_MISC_FRAG_WAIT_EN        0x00000100 // Fragment Starvation Policy
626
#define AR_D_MISC_FRAG_BKOFF_EN       0x00000200 // Backoff during a frag burst
627
#define AR_D_MISC_CW_BKOFF_EN         0x00001000 // Use binary exponential CW backoff
628
#define AR_D_MISC_VIR_COL_HANDLING    0x0000C000 // Mask for Virtual collision handling policy
629
#define AR_D_MISC_VIR_COL_HANDLING_S  14         // Shift for Virtual collision handling policy
630
#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0     // Normal
631
#define AR_D_MISC_VIR_COL_HANDLING_IGNORE  1     // Ignore
632
#define AR_D_MISC_BEACON_USE          0x00010000 // Beacon use indication
633
#define AR_D_MISC_ARB_LOCKOUT_CNTRL   0x00060000 // Mask for DCU arbiter lockout control
634
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17         // Shift for DCU arbiter lockout control
635
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE     0   // No lockout
636
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1   // Intra-frame
637
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2   // Global
638
#define AR_D_MISC_ARB_LOCKOUT_IGNORE  0x00080000 // DCU arbiter lockout ignore control
639
#define AR_D_MISC_SEQ_NUM_INCR_DIS    0x00100000 // Sequence number increment disable
640
#define AR_D_MISC_POST_FR_BKOFF_DIS   0x00200000 // Post-frame backoff disable
641
#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy
642
#define AR_D_MISC_BLOWN_IFS_RETRY_EN  0x00800000 // Initiate Retry procedure on Blown IFS
643
#define AR_D_MISC_RESV0               0xFF000000 // Reserved
644

645
/* MAC Frame sequence number control/status */
646
#define AR_D_SEQNUM      AR_MAC_DCU_OFFSET(MAC_DCU_SEQ)
647

648
/* MAC DCU transmit pause control/status */
649
#define AR_D_TXPSE                 AR_MAC_DCU_OFFSET(MAC_DCU_PAUSE)
650
#define AR_D_TXPSE_CTRL            0x000003FF // Mask of DCUs to pause (DCUs 0-9)
651
#define AR_D_TXPSE_RESV0           0x0000FC00 // Reserved
652
#define AR_D_TXPSE_STATUS          0x00010000 // Transmit pause status
653
#define AR_D_TXPSE_RESV1           0xFFFE0000 // Reserved
654

655
/* MAC DCU WOW Keep-Alive Config register */
656
#define AR_D_WOW_KACFG             AR_MAC_DCU_OFFSET(MAC_DCU_WOW_KACFG)
657

658
/* MAC DCU transmission slot mask */
659
#define AR_D_TXSLOTMASK            AR_MAC_DCU_OFFSET(MAC_DCU_TXSLOT)
660
#define AR_D_TXSLOTMASK_NUM        0x0000000F // slot numbers
661

662
/* MAC DCU-specific IFS settings */
663
#define AR_D0_LCL_IFS     AR_MAC_DCU_OFFSET(MAC_DCU_LCL_IFS)
664
#define AR_DLCL_IFS(_i)   (AR_D0_LCL_IFS + ((_i)<<2))
665
#define AR_D9_LCL_IFS     AR_DLCL_IFS(9)
666
#define AR_D_LCL_IFS_CWMIN       0x000003FF // Mask for CW_MIN
667
#define AR_D_LCL_IFS_CWMIN_S     0          // Shift for CW_MIN
668
#define AR_D_LCL_IFS_CWMAX       0x000FFC00 // Mask for CW_MAX
669
#define AR_D_LCL_IFS_CWMAX_S     10         // Shift for CW_MAX
670
#define AR_D_LCL_IFS_AIFS        0x0FF00000 // Mask for AIFS
671
#define AR_D_LCL_IFS_AIFS_S      20         // Shift for AIFS
672
    /*
673
     *  Note:  even though this field is 8 bits wide the
674
     *  maximum supported AIFS value is 0xfc.  Setting the AIFS value
675
     *  to 0xfd 0xfe or 0xff will not work correctly and will cause
676
     *  the DCU to hang.
677
     */
678
#define AR_D_LCL_IFS_RESV0    0xF0000000 // Reserved
679

680

681
#define AR_CFG_LED                     0x1f04 /* LED control */
682
#define AR_CFG_SCLK_RATE_IND           0x00000003 /* sleep clock indication */
683
#define AR_CFG_SCLK_RATE_IND_S         0
684
#define AR_CFG_SCLK_32MHZ              0x00000000 /* Sleep clock rate */
685
#define AR_CFG_SCLK_4MHZ               0x00000001 /* Sleep clock rate */
686
#define AR_CFG_SCLK_1MHZ               0x00000002 /* Sleep clock rate */
687
#define AR_CFG_SCLK_32KHZ              0x00000003 /* Sleep clock rate */
688
#define AR_CFG_LED_BLINK_SLOW          0x00000008 /* LED slowest blink rate mode */
689
#define AR_CFG_LED_BLINK_THRESH_SEL    0x00000070 /* LED blink threshold select */
690
#define AR_CFG_LED_MODE_SEL            0x00000380 /* LED mode: bits 7..9 */
691
#define AR_CFG_LED_MODE_SEL_S          7          /* LED mode: bits 7..9 */
692
#define AR_CFG_LED_POWER               0x00000280 /* Power LED: bit 9=1, bit 7=<LED State> */
693
#define AR_CFG_LED_POWER_S             7          /* LED mode: bits 7..9 */
694
#define AR_CFG_LED_NETWORK             0x00000300 /* Network LED: bit 9=1, bit 8=<LED State> */
695
#define AR_CFG_LED_NETWORK_S           7          /* LED mode: bits 7..9 */
696
#define AR_CFG_LED_MODE_PROP           0x0        /* Blink prop to filtered tx/rx */
697
#define AR_CFG_LED_MODE_RPROP          0x1        /* Blink prop to unfiltered tx/rx */
698
#define AR_CFG_LED_MODE_SPLIT          0x2        /* Blink power for tx/net for rx */
699
#define AR_CFG_LED_MODE_RAND           0x3        /* Blink randomly */
700
#define AR_CFG_LED_MODE_POWER_OFF      0x4        /* Power LED OFF */
701
#define AR_CFG_LED_MODE_POWER_ON       0x5        /* Power LED ON   */
702
#define AR_CFG_LED_MODE_NETWORK_OFF    0x4        /* Network LED OFF */
703
#define AR_CFG_LED_MODE_NETWORK_ON     0x6        /* Network LED ON  */
704
#define AR_CFG_LED_ASSOC_CTL           0x00000c00 /* LED control: bits 10..11 */
705
#define AR_CFG_LED_ASSOC_CTL_S         10         /* LED control: bits 10..11 */
706
#define AR_CFG_LED_ASSOC_NONE          0x0        /* 0x00000000: STA is not associated or trying */
707
#define AR_CFG_LED_ASSOC_ACTIVE        0x1        /* 0x00000400: STA is associated */
708
#define AR_CFG_LED_ASSOC_PENDING       0x2        /* 0x00000800: STA is trying to associate */
709

710
#define AR_CFG_LED_BLINK_SLOW          0x00000008 /* LED slowest blink rate mode: bit 3 */
711
#define AR_CFG_LED_BLINK_SLOW_S        3          /* LED slowest blink rate mode: bit 3 */
712

713
#define AR_CFG_LED_BLINK_THRESH_SEL    0x00000070 /* LED blink threshold select: bits 4..6 */
714
#define AR_CFG_LED_BLINK_THRESH_SEL_S  4          /* LED blink threshold select: bits 4..6 */
715

716
#define AR_MAC_SLEEP                0x1f00
717
#define AR_MAC_SLEEP_MAC_AWAKE      0x00000000 // mac is now awake
718
#define AR_MAC_SLEEP_MAC_ASLEEP     0x00000001 // mac is now asleep
719

720

721

722
/******************************************************************************
723
 * Host Interface Register Map
724
******************************************************************************/
725
// DMA & PCI Registers in PCI space (usable during sleep)
726

727
#define AR_HOSTIF_REG(_ah, _reg) (AH9300(_ah)->ah_hostifregs._reg)
728
#define AR9300_HOSTIF_OFFSET(_x)   offsetof(struct host_intf_reg, _x)
729
#define AR9340_HOSTIF_OFFSET(_x)   offsetof(struct host_intf_reg_ar9340, _x)
730

731
/* Interface Reset Control Register */
732
#define AR_RC_AHB            0x00000001 // ahb reset
733
#define AR_RC_APB            0x00000002 // apb reset
734
#define AR_RC_HOSTIF         0x00000100 // host interface reset
735

736
/* PCI express work-arounds */
737
#define AR_WA_D3_TO_L1_DISABLE          (1 << 14)
738
#define AR_WA_UNTIE_RESET_EN            (1 << 15) /* Enable PCI Reset to POR (power-on-reset) */
739
#define AR_WA_D3_TO_L1_DISABLE_REAL     (1 << 16)
740
#define AR_WA_ASPM_TIMER_BASED_DISABLE  (1 << 17)
741
#define AR_WA_RESET_EN                  (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
742
#define AR_WA_ANALOG_SHIFT              (1 << 20)
743
#define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
744
#define AR_WA_COLD_RESET_OVERRIDE       (1 << 13) /* PCI-E Cold reset override */
745

746
/* power management state */
747
#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow
748

749
/* CXPL Debug signals which help debug Link Negotiation */
750
/* CXPL Debug signals which help debug Link Negotiation */
751

752
/* XXX check bit feilds */
753
/* Power Management Control Register */
754
#define AR_PCIE_PM_CTRL_ENA         0x00080000
755
#define AR_PMCTRL_WOW_PME_CLR       0x00200000  /* Clear WoW event */
756
#define AR_PMCTRL_HOST_PME_EN       0x00400000  /* Send OOB WAKE_L on WoW event */
757
#define AR_PMCTRL_D3COLD_VAUX       0x00800000
758
#define AR_PMCTRL_PWR_STATE_MASK    0x0F000000  /* Power State Mask */
759
#define AR_PMCTRL_PWR_STATE_D1D3    0x0F000000  /* Activate D1 and D3 */
760
#define AR_PMCTRL_PWR_STATE_D0      0x08000000  /* Activate D0 */
761
#define AR_PMCTRL_PWR_PM_CTRL_ENA   0x00008000  /* Enable power management */
762
#define AR_PMCTRL_AUX_PWR_DET       0x10000000  /* Puts Chip in L2 state */
763

764

765

766
/* APB and Local Bus Timeout Counters */
767
#define AR_HOST_TIMEOUT_APB_CNTR    0x0000FFFF
768
#define AR_HOST_TIMEOUT_APB_CNTR_S  0
769
#define AR_HOST_TIMEOUT_LCL_CNTR    0xFFFF0000
770
#define AR_HOST_TIMEOUT_LCL_CNTR_S  16
771

772
/* EEPROM Control Register */
773
#define AR_EEPROM_ABSENT         0x00000100
774
#define AR_EEPROM_CORRUPT        0x00000200
775
#define AR_EEPROM_PROT_MASK      0x03FFFC00
776
#define AR_EEPROM_PROT_MASK_S    10
777

778
// Protect Bits RP is read protect WP is write protect
779
#define EEPROM_PROTECT_RP_0_31        0x0001
780
#define EEPROM_PROTECT_WP_0_31        0x0002
781
#define EEPROM_PROTECT_RP_32_63       0x0004
782
#define EEPROM_PROTECT_WP_32_63       0x0008
783
#define EEPROM_PROTECT_RP_64_127      0x0010
784
#define EEPROM_PROTECT_WP_64_127      0x0020
785
#define EEPROM_PROTECT_RP_128_191     0x0040
786
#define EEPROM_PROTECT_WP_128_191     0x0080
787
#define EEPROM_PROTECT_RP_192_255     0x0100
788
#define EEPROM_PROTECT_WP_192_255     0x0200
789
#define EEPROM_PROTECT_RP_256_511     0x0400
790
#define EEPROM_PROTECT_WP_256_511     0x0800
791
#define EEPROM_PROTECT_RP_512_1023    0x1000
792
#define EEPROM_PROTECT_WP_512_1023    0x2000
793
#define EEPROM_PROTECT_RP_1024_2047   0x4000
794
#define EEPROM_PROTECT_WP_1024_2047   0x8000
795

796
/* RF silent */
797
#define AR_RFSILENT_FORCE             0x01
798

799
/* MAC silicon Rev ID */
800
#define AR_SREV_ID                    0x000000FF /* Mask to read SREV info */
801
#define AR_SREV_VERSION               0x000000F0 /* Mask for Chip version */
802
#define AR_SREV_VERSION_S             4          /* Mask to shift Major Rev Info */
803
#define AR_SREV_REVISION              0x00000007 /* Mask for Chip revision level */
804

805
/* Sowl extension to SREV. AR_SREV_ID must be 0xFF */
806
#define AR_SREV_ID2                           0xFFFFFFFF /* Mask to read SREV info */
807
#define AR_SREV_VERSION2                      0xFFFC0000 /* Mask for Chip version */
808
#define AR_SREV_VERSION2_S                    18         /* Mask to shift Major Rev Info */
809
#define AR_SREV_TYPE2                         0x0003F000 /* Mask for Chip type */
810
#define AR_SREV_TYPE2_S                       12         /* Mask to shift Major Rev Info */
811
#define AR_SREV_TYPE2_CHAIN                   0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */
812
#define AR_SREV_TYPE2_HOST_MODE               0x00002000 /* host mode (1 = PCI, 0 = PCIe) */
813
/* Jupiter has a different TYPE2 definition. */
814
#define AR_SREV_TYPE2_JUPITER_CHAIN           0x00001000 /* chain (1 = 2 chains, 0 = 1 chain) */
815
#define AR_SREV_TYPE2_JUPITER_BAND            0x00002000 /* band (1 =  dual band, 0 = single band) */
816
#define AR_SREV_TYPE2_JUPITER_BT              0x00004000 /* BT (1 = shared BT, 0 = no BT) */
817
#define AR_SREV_TYPE2_JUPITER_MODE            0x00008000 /* mode (1 = premium, 0 = standard) */
818
#define AR_SREV_REVISION2                     0x00000F00
819
#define AR_SREV_REVISION2_S               8
820

821
#define AR_RADIO_SREV_MAJOR                   0xf0
822
#define AR_RAD5133_SREV_MAJOR                 0xc0 /* Fowl: 2+5G/3x3 */
823
#define AR_RAD2133_SREV_MAJOR                 0xd0 /* Fowl: 2G/3x3   */
824
#define AR_RAD5122_SREV_MAJOR                 0xe0 /* Fowl: 5G/2x2   */
825
#define AR_RAD2122_SREV_MAJOR                 0xf0 /* Fowl: 2+5G/2x2 */
826

827
#if 0
828
#define AR_AHB_MODE                           0x4024 // ahb mode for dma
829
#define AR_AHB_EXACT_WR_EN                    0x00000000 // write exact bytes
830
#define AR_AHB_BUF_WR_EN                      0x00000001 // buffer write upto cacheline
831
#define AR_AHB_EXACT_RD_EN                    0x00000000 // read exact bytes
832
#define AR_AHB_CACHELINE_RD_EN                0x00000002 // read upto end of cacheline
833
#define AR_AHB_PREFETCH_RD_EN                 0x00000004 // prefetch upto page boundary
834
#define AR_AHB_PAGE_SIZE_1K                   0x00000000 // set page-size as 1k
835
#define AR_AHB_PAGE_SIZE_2K                   0x00000008 // set page-size as 2k
836
#define AR_AHB_PAGE_SIZE_4K                   0x00000010 // set page-size as 4k
837
#endif
838

839
#define AR_INTR_RTC_IRQ                       0x00000001 // rtc in shutdown state
840
#define AR_INTR_MAC_IRQ                       0x00000002 // pending mac interrupt
841
#if 0
842
/* 
843
 * the following definitions might be differents for WASP so 
844
 * disable them to avoid improper use 
845
 */
846
#define AR_INTR_EEP_PROT_ACCESS               0x00000004 // eeprom protected area access
847
#define AR_INTR_MAC_AWAKE                     0x00020000 // mac is awake
848
#define AR_INTR_MAC_ASLEEP                    0x00040000 // mac is asleep
849
#endif
850
#define AR_INTR_SPURIOUS                      0xFFFFFFFF
851

852
/* TODO: fill in other values */
853

854
/* Synchronous Interrupt Cause Register */
855

856
/* Synchronous Interrupt Enable Register */
857
#define AR_INTR_SYNC_ENABLE_GPIO      0xFFFC0000 // enable interrupts: bits 18..31
858
#define AR_INTR_SYNC_ENABLE_GPIO_S    18         // enable interrupts: bits 18..31
859

860
/*
861
 * synchronous interrupt signals
862
 */
863
enum {
864
    AR9300_INTR_SYNC_RTC_IRQ                = 0x00000001,
865
    AR9300_INTR_SYNC_MAC_IRQ                = 0x00000002,
866
    AR9300_INTR_SYNC_EEPROM_ILLEGAL_ACCESS  = 0x00000004,
867
    AR9300_INTR_SYNC_APB_TIMEOUT            = 0x00000008,
868
    AR9300_INTR_SYNC_PCI_MODE_CONFLICT      = 0x00000010,
869
    AR9300_INTR_SYNC_HOST1_FATAL            = 0x00000020,
870
    AR9300_INTR_SYNC_HOST1_PERR             = 0x00000040,
871
    AR9300_INTR_SYNC_TRCV_FIFO_PERR         = 0x00000080,
872
    AR9300_INTR_SYNC_RADM_CPL_EP            = 0x00000100,
873
    AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT    = 0x00000200,
874
    AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT     = 0x00000400,
875
    AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR      = 0x00000800,
876
    AR9300_INTR_SYNC_RADM_CPL_TIMEOUT       = 0x00001000,
877
    AR9300_INTR_SYNC_LOCAL_TIMEOUT          = 0x00002000,
878
    AR9300_INTR_SYNC_PM_ACCESS              = 0x00004000,
879
    AR9300_INTR_SYNC_MAC_AWAKE              = 0x00008000,
880
    AR9300_INTR_SYNC_MAC_ASLEEP             = 0x00010000,
881
    AR9300_INTR_SYNC_MAC_SLEEP_ACCESS       = 0x00020000,
882
    AR9300_INTR_SYNC_ALL                    = 0x0003FFFF,
883

884
    /*
885
     * Do not enable and turn on mask for both sync and async interrupt, since
886
     * chip can generate interrupt storm.
887
     */
888
    AR9300_INTR_SYNC_DEF_NO_HOST1_PERR      = (AR9300_INTR_SYNC_HOST1_FATAL         |
889
                                               AR9300_INTR_SYNC_RADM_CPL_EP         |
890
                                               AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT |
891
                                               AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT  |
892
                                               AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR   |
893
                                               AR9300_INTR_SYNC_RADM_CPL_TIMEOUT    |
894
                                               AR9300_INTR_SYNC_LOCAL_TIMEOUT       |
895
                                               AR9300_INTR_SYNC_MAC_SLEEP_ACCESS),
896
    AR9300_INTR_SYNC_DEFAULT                = (AR9300_INTR_SYNC_DEF_NO_HOST1_PERR   |
897
                                               AR9300_INTR_SYNC_HOST1_PERR),
898

899
    AR9300_INTR_SYNC_SPURIOUS               = 0xFFFFFFFF,
900
    
901
    /* WASP */
902
    AR9340_INTR_SYNC_RTC_IRQ                = 0x00000001,
903
    AR9340_INTR_SYNC_MAC_IRQ                = 0x00000002,
904
    AR9340_INTR_SYNC_HOST1_FATAL            = 0x00000004,
905
    AR9340_INTR_SYNC_HOST1_PERR             = 0x00000008,
906
    AR9340_INTR_SYNC_LOCAL_TIMEOUT          = 0x00000010,
907
    AR9340_INTR_SYNC_MAC_ASLEEP             = 0x00000020,
908
    AR9340_INTR_SYNC_MAC_SLEEP_ACCESS       = 0x00000040,
909

910
    AR9340_INTR_SYNC_DEFAULT                = (AR9340_INTR_SYNC_HOST1_FATAL         |
911
                                               AR9340_INTR_SYNC_HOST1_PERR          |
912
                                               AR9340_INTR_SYNC_LOCAL_TIMEOUT       |
913
                                               AR9340_INTR_SYNC_MAC_SLEEP_ACCESS),
914

915
    AR9340_INTR_SYNC_SPURIOUS               = 0xFFFFFFFF,
916
};
917

918
/* Asynchronous Interrupt Mask Register */
919
#define AR_INTR_ASYNC_MASK_GPIO          0xFFFC0000 // asynchronous interrupt mask: bits 18..31
920
#define AR_INTR_ASYNC_MASK_GPIO_S        18         // asynchronous interrupt mask: bits 18..31
921
#define AR_INTR_ASYNC_MASK_MCI           0x00000080
922
#define AR_INTR_ASYNC_MASK_MCI_S         7
923

924
/* Synchronous Interrupt Mask Register */
925
#define AR_INTR_SYNC_MASK_GPIO           0xFFFC0000 // synchronous interrupt mask: bits 18..31
926
#define AR_INTR_SYNC_MASK_GPIO_S         18         // synchronous interrupt mask: bits 18..31
927

928
/* Asynchronous Interrupt Cause Register */
929
#define AR_INTR_ASYNC_CAUSE_GPIO         0xFFFC0000 // GPIO interrupts: bits 18..31
930
#define AR_INTR_ASYNC_CAUSE_MCI          0x00000080
931
#define AR_INTR_ASYNC_USED               (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO | AR_INTR_ASYNC_CAUSE_MCI)
932

933
/* Asynchronous Interrupt Enable Register */
934
#define AR_INTR_ASYNC_ENABLE_GPIO        0xFFFC0000 // enable interrupts: bits 18..31
935
#define AR_INTR_ASYNC_ENABLE_GPIO_S      18         // enable interrupts: bits 18..31
936
#define AR_INTR_ASYNC_ENABLE_MCI         0x00000080
937
#define AR_INTR_ASYNC_ENABLE_MCI_S       7
938

939
/* PCIE PHY Data Register */
940

941
/* PCIE PHY Load Register */
942
#define AR_PCIE_PM_CTRL_ENA              0x00080000
943

944
#define AR93XX_NUM_GPIO                  16 // 0 to 15
945

946
/* GPIO Output Register */
947
#define AR_GPIO_OUT_VAL                  0x000FFFF
948
#define AR_GPIO_OUT_VAL_S                0
949

950
/* GPIO Input Register */
951
#define AR_GPIO_IN_VAL                   0x000FFFF
952
#define AR_GPIO_IN_VAL_S                 0
953

954
/* Host GPIO output enable bits */
955
#define AR_GPIO_OE_OUT_DRV               0x3    // 2 bit field mask, shifted by 2*bitpos
956
#define AR_GPIO_OE_OUT_DRV_NO            0x0    // tristate
957
#define AR_GPIO_OE_OUT_DRV_LOW           0x1    // drive if low
958
#define AR_GPIO_OE_OUT_DRV_HI            0x2    // drive if high
959
#define AR_GPIO_OE_OUT_DRV_ALL           0x3    // drive always
960

961
/* Host GPIO output enable bits */
962

963
/* Host GPIO Interrupt Polarity */
964
#define AR_GPIO_INTR_POL_VAL             0x0001FFFF    // bits 16:0 correspond to gpio 16:0
965
#define AR_GPIO_INTR_POL_VAL_S           0             // bits 16:0 correspond to gpio 16:0
966

967
/* Host GPIO Input Value */
968
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF     0x00000004 // default value for bt_priority_async
969
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S       2
970
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF    0x00000008 // default value for bt_frequency_async
971
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S      3
972
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF       0x00000010 // default value for bt_active_async
973
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S         4
974
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF        0x00000080 // default value for rfsilent_bb_l
975
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S      7
976
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB      0x00000400 // 0 == set bt_priority_async to default, 1 == connect bt_prority_async to baseband
977
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S    10
978
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB     0x00000800 // 0 == set bt_frequency_async to default, 1 == connect bt_frequency_async to baseband
979
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S   11
980
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB        0x00001000 // 0 == set bt_active_async to default, 1 == connect bt_active_async to baseband
981
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S      12
982
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB         0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband
983
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S       15
984
#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE        0x00010000
985
#define AR_GPIO_JTAG_DISABLE                     0x00020000 // 1 == disable JTAG
986

987
/* GPIO Input Mux1 */
988
#define AR_GPIO_INPUT_MUX1_BT_PRIORITY           0x00000f00 /* bits 8..11: input mux for BT priority input */
989
#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S         8          /* bits 8..11: input mux for BT priority input */
990
#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY          0x0000f000 /* bits 12..15: input mux for BT frequency input */
991
#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S        12         /* bits 12..15: input mux for BT frequency input */
992
#define AR_GPIO_INPUT_MUX1_BT_ACTIVE             0x000f0000 /* bits 16..19: input mux for BT active input */
993
#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S           16         /* bits 16..19: input mux for BT active input */
994

995
/* GPIO Input Mux2 */
996
#define AR_GPIO_INPUT_MUX2_CLK25                 0x0000000f // bits 0..3: input mux for clk25 input
997
#define AR_GPIO_INPUT_MUX2_CLK25_S               0          // bits 0..3: input mux for clk25 input
998
#define AR_GPIO_INPUT_MUX2_RFSILENT              0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input
999
#define AR_GPIO_INPUT_MUX2_RFSILENT_S            4          // bits 4..7: input mux for rfsilent_bb_l input
1000
#define AR_GPIO_INPUT_MUX2_RTC_RESET             0x00000f00 // bits 8..11: input mux for RTC Reset input
1001
#define AR_GPIO_INPUT_MUX2_RTC_RESET_S           8          // bits 8..11: input mux for RTC Reset input
1002

1003
/* GPIO Output Mux1 */
1004
/* GPIO Output Mux2 */
1005
/* GPIO Output Mux3 */
1006

1007
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
1008
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
1009
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
1010
#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
1011
#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
1012
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
1013
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
1014
#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA      0x16
1015
#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK       0x17
1016
#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA        0x18
1017
#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK         0x19
1018
#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX           0x14
1019
#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX           0x13
1020
#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX           9
1021
#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX           8
1022
#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE      0x1d
1023
#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA        0x1e
1024

1025
#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0     0x1d
1026
#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1     0x1e
1027
#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2     0x1b
1028
/* The above three seems to be functional values for peacock chip. For some
1029
 * reason these are continued for different boards as simple place holders.
1030
 * Now continuing to use these and adding the extra definitions for Scropion
1031
 */
1032
#define AR_GPIO_OUTPUT_MUX_AS_SWCOM3             0x26 
1033

1034
#define AR_ENABLE_SMARTANTENNA 0x00000001
1035

1036
/* Host GPIO Input State */
1037

1038
/* Host Spare */
1039

1040
/* Host PCIE Core Reset Enable */
1041

1042
/* Host CLKRUN */
1043

1044

1045
/* Host EEPROM Status */
1046
#define AR_EEPROM_STATUS_DATA_VAL                0x0000ffff
1047
#define AR_EEPROM_STATUS_DATA_VAL_S              0
1048
#define AR_EEPROM_STATUS_DATA_BUSY               0x00010000
1049
#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS        0x00020000
1050
#define AR_EEPROM_STATUS_DATA_PROT_ACCESS        0x00040000
1051
#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS      0x00080000
1052

1053
/* Host Observation Control */
1054

1055
/* Host RF Silent */
1056

1057
/* Host GPIO PDPU */
1058
#define AR_GPIO_PDPU_OPTION                      0x03
1059
#define AR_GPIO_PULL_DOWN                        0x02
1060

1061
/* Host GPIO Drive Strength */
1062

1063
/* Host Miscellaneous */
1064

1065
/* Host PCIE MSI Control Register */
1066
#define AR_PCIE_MSI_ENABLE                       0x00000001
1067
#define AR_PCIE_MSI_HW_DBI_WR_EN                 0x02000000
1068
#define AR_PCIE_MSI_HW_INT_PENDING_ADDR          0xFFA0C1FF // bits 8..11: value must be 0x5060 
1069
#define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64   0xFFA0C9FF // bits 8..11: value must be 0x5064 
1070

1071

1072
#define AR_INTR_PRIO_TX                          0x00000001
1073
#define AR_INTR_PRIO_RXLP                        0x00000002
1074
#define AR_INTR_PRIO_RXHP                        0x00000004
1075

1076
/* OTP Interface Register */
1077
#define AR_ENT_OTP                AR9300_HOSTIF_OFFSET(HOST_INTF_OTP)
1078

1079
#define AR_ENT_OTP_DUAL_BAND_DISABLE            0x00010000
1080
#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
1081
#define AR_ENT_OTP_5MHZ_DISABLE                 0x00040000
1082
#define AR_ENT_OTP_10MHZ_DISABLE                0x00080000
1083
#define AR_ENT_OTP_49GHZ_DISABLE                0x00100000
1084
#define AR_ENT_OTP_LOOPBACK_DISABLE             0x00200000
1085
#define AR_ENT_OTP_TPC_PERF_DISABLE             0x00400000
1086
#define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE         0x00800000
1087
#define AR_ENT_OTP_SPECTRAL_PRECISION           0x03000000
1088

1089
/* OTP EFUSE registers */
1090
#define AR_OTP_EFUSE_OFFSET(_x)   offsetof(struct efuse_reg_WLAN, _x)
1091
#define AR_OTP_EFUSE_INTF0        AR_OTP_EFUSE_OFFSET(OTP_INTF0)    
1092
#define AR_OTP_EFUSE_INTF5        AR_OTP_EFUSE_OFFSET(OTP_INTF5)   
1093
#define AR_OTP_EFUSE_PGENB_SETUP_HOLD_TIME  AR_OTP_EFUSE_OFFSET(OTP_PGENB_SETUP_HOLD_TIME)
1094
#define AR_OTP_EFUSE_MEM          AR_OTP_EFUSE_OFFSET(OTP_MEM)
1095

1096
/******************************************************************************
1097
 * RTC Register Map
1098
******************************************************************************/
1099

1100
#define AR_RTC_OFFSET(_x)   offsetof(struct rtc_reg, _x)
1101

1102
/* Reset Control */
1103
#define AR_RTC_RC               AR_RTC_OFFSET(RESET_CONTROL)
1104
#define AR_RTC_RC_M             0x00000003
1105
#define AR_RTC_RC_MAC_WARM      0x00000001
1106
#define AR_RTC_RC_MAC_COLD      0x00000002
1107

1108
/* Crystal Control */
1109
#define AR_RTC_XTAL_CONTROL     AR_RTC_OFFSET(XTAL_CONTROL)
1110

1111
/* Reg Control 0 */
1112
#define AR_RTC_REG_CONTROL0     AR_RTC_OFFSET(REG_CONTROL0)
1113

1114
/* Reg Control 1 */
1115
#define AR_RTC_REG_CONTROL1     AR_RTC_OFFSET(REG_CONTROL1)
1116
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM   0x00000001
1117

1118
/* TCXO Detect */
1119
#define AR_RTC_TCXO_DETECT      AR_RTC_OFFSET(TCXO_DETECT)
1120

1121
/* Crystal Test */
1122
#define AR_RTC_XTAL_TEST        AR_RTC_OFFSET(XTAL_TEST)
1123

1124
/* Sets the ADC/DAC clock quadrature */
1125
#define AR_RTC_QUADRATURE       AR_RTC_OFFSET(QUADRATURE)
1126

1127
/* PLL Control */
1128
#define AR_RTC_PLL_CONTROL      AR_RTC_OFFSET(PLL_CONTROL)
1129
#define AR_RTC_PLL_DIV          0x000003ff
1130
#define AR_RTC_PLL_DIV_S        0
1131
#define AR_RTC_PLL_REFDIV       0x00003C00
1132
#define AR_RTC_PLL_REFDIV_S     10
1133
#define AR_RTC_PLL_CLKSEL       0x0000C000
1134
#define AR_RTC_PLL_CLKSEL_S     14
1135
#define AR_RTC_PLL_BYPASS       0x00010000
1136
#define AR_RTC_PLL_BYPASS_S     16
1137

1138

1139
/* PLL Control 2: for Hornet */
1140
#define AR_RTC_PLL_CONTROL2      AR_RTC_OFFSET(PLL_CONTROL2)
1141

1142
/* PLL Settle */
1143
#define AR_RTC_PLL_SETTLE        AR_RTC_OFFSET(PLL_SETTLE)
1144

1145
/* Crystal Settle */
1146
#define AR_RTC_XTAL_SETTLE       AR_RTC_OFFSET(XTAL_SETTLE)
1147

1148
/* Controls CLK_OUT pin clock speed */
1149
#define AR_RTC_CLOCK_OUT         AR_RTC_OFFSET(CLOCK_OUT)
1150

1151
/* Forces bias block on at all times */
1152
#define AR_RTC_BIAS_OVERRIDE     AR_RTC_OFFSET(BIAS_OVERRIDE)
1153

1154
/* System Sleep status bits */
1155
#define AR_RTC_SYSTEM_SLEEP      AR_RTC_OFFSET(SYSTEM_SLEEP)
1156

1157
/* Controls sleep options for MAC */
1158
#define AR_RTC_MAC_SLEEP_CONTROL AR_RTC_OFFSET(MAC_SLEEP_CONTROL)
1159

1160
/* Keep Awake Timer */
1161
#define AR_RTC_KEEP_AWAKE        AR_RTC_OFFSET(KEEP_AWAKE)
1162

1163
/* Create a 32kHz clock derived from HF */
1164
#define AR_RTC_DERIVED_RTC_CLK   AR_RTC_OFFSET(DERIVED_RTC_CLK)
1165

1166

1167
/******************************************************************************
1168
 * RTC SYNC Register Map
1169
******************************************************************************/
1170

1171
#define AR_RTC_SYNC_OFFSET(_x)   offsetof(struct rtc_sync_reg, _x)
1172

1173
/* reset RTC */
1174
#define AR_RTC_RESET            AR_RTC_SYNC_OFFSET(RTC_SYNC_RESET)
1175
#define AR_RTC_RESET_EN         0x00000001  /* Reset RTC bit */
1176

1177
/* system sleep status */
1178
#define AR_RTC_STATUS               AR_RTC_SYNC_OFFSET(RTC_SYNC_STATUS)
1179
#define AR_RTC_STATUS_M             0x0000003f
1180
#define AR_RTC_STATUS_SHUTDOWN      0x00000001
1181
#define AR_RTC_STATUS_ON            0x00000002
1182
#define AR_RTC_STATUS_SLEEP         0x00000004
1183
#define AR_RTC_STATUS_WAKEUP        0x00000008
1184
#define AR_RTC_STATUS_SLEEP_ACCESS  0x00000010
1185
#define AR_RTC_STATUS_PLL_CHANGING  0x00000020
1186

1187
/* RTC Derived Register */
1188
#define AR_RTC_SLEEP_CLK            AR_RTC_SYNC_OFFSET(RTC_SYNC_DERIVED)
1189
#define AR_RTC_FORCE_DERIVED_CLK    0x00000002
1190
#define AR_RTC_FORCE_SWREG_PRD      0x00000004
1191
#define AR_RTC_PCIE_RST_PWDN_EN     0x00000008
1192

1193
/* RTC Force Wake Register */
1194
#define AR_RTC_FORCE_WAKE           AR_RTC_SYNC_OFFSET(RTC_SYNC_FORCE_WAKE)
1195
#define AR_RTC_FORCE_WAKE_EN        0x00000001  /* enable force wake */
1196
#define AR_RTC_FORCE_WAKE_ON_INT    0x00000002  /* auto-wake on MAC interrupt */
1197

1198
/* RTC interrupt cause/clear */
1199
#define AR_RTC_INTR_CAUSE       AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_CAUSE)
1200
/* RTC interrupt enable */
1201
#define AR_RTC_INTR_ENABLE      AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_ENABLE)
1202
/* RTC interrupt mask */
1203
#define AR_RTC_INTR_MASK        AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_MASK)
1204

1205

1206

1207
/******************************************************************************
1208
 * Analog Interface Register Map
1209
******************************************************************************/
1210

1211
#define AR_AN_OFFSET(_x)   offsetof(struct analog_intf_reg_csr, _x)
1212

1213
/* XXX */
1214
#if 1
1215
// AR9280: rf long shift registers
1216
#define AR_AN_RF2G1_CH0         0x7810
1217
#define AR_AN_RF2G1_CH0_OB      0x03800000
1218
#define AR_AN_RF2G1_CH0_OB_S    23
1219
#define AR_AN_RF2G1_CH0_DB      0x1C000000
1220
#define AR_AN_RF2G1_CH0_DB_S    26
1221

1222
#define AR_AN_RF5G1_CH0         0x7818
1223
#define AR_AN_RF5G1_CH0_OB5     0x00070000
1224
#define AR_AN_RF5G1_CH0_OB5_S   16
1225
#define AR_AN_RF5G1_CH0_DB5     0x00380000
1226
#define AR_AN_RF5G1_CH0_DB5_S   19
1227

1228
#define AR_AN_RF2G1_CH1         0x7834
1229
#define AR_AN_RF2G1_CH1_OB      0x03800000
1230
#define AR_AN_RF2G1_CH1_OB_S    23
1231
#define AR_AN_RF2G1_CH1_DB      0x1C000000
1232
#define AR_AN_RF2G1_CH1_DB_S    26
1233

1234
#define AR_AN_RF5G1_CH1         0x783C
1235
#define AR_AN_RF5G1_CH1_OB5     0x00070000
1236
#define AR_AN_RF5G1_CH1_OB5_S   16
1237
#define AR_AN_RF5G1_CH1_DB5     0x00380000
1238
#define AR_AN_RF5G1_CH1_DB5_S   19
1239

1240
#define AR_AN_TOP2                  0x7894
1241
#define AR_AN_TOP2_XPABIAS_LVL      0xC0000000
1242
#define AR_AN_TOP2_XPABIAS_LVL_S    30
1243
#define AR_AN_TOP2_LOCALBIAS        0x00200000
1244
#define AR_AN_TOP2_LOCALBIAS_S      21
1245
#define AR_AN_TOP2_PWDCLKIND        0x00400000
1246
#define AR_AN_TOP2_PWDCLKIND_S      22
1247

1248
#define AR_AN_SYNTH9            0x7868
1249
#define AR_AN_SYNTH9_REFDIVA    0xf8000000
1250
#define AR_AN_SYNTH9_REFDIVA_S  27
1251

1252
// AR9285 Analog registers 
1253
#define AR9285_AN_RF2G1          0x7820
1254
#define AR9285_AN_RF2G2          0x7824
1255

1256
#define AR9285_AN_RF2G3         0x7828
1257
#define AR9285_AN_RF2G3_OB_0    0x00E00000
1258
#define AR9285_AN_RF2G3_OB_0_S    21
1259
#define AR9285_AN_RF2G3_OB_1    0x001C0000
1260
#define AR9285_AN_RF2G3_OB_1_S    18
1261
#define AR9285_AN_RF2G3_OB_2    0x00038000
1262
#define AR9285_AN_RF2G3_OB_2_S    15
1263
#define AR9285_AN_RF2G3_OB_3    0x00007000
1264
#define AR9285_AN_RF2G3_OB_3_S    12
1265
#define AR9285_AN_RF2G3_OB_4    0x00000E00
1266
#define AR9285_AN_RF2G3_OB_4_S    9
1267

1268
#define AR9285_AN_RF2G3_DB1_0    0x000001C0
1269
#define AR9285_AN_RF2G3_DB1_0_S    6
1270
#define AR9285_AN_RF2G3_DB1_1    0x00000038
1271
#define AR9285_AN_RF2G3_DB1_1_S    3
1272
#define AR9285_AN_RF2G3_DB1_2    0x00000007
1273
#define AR9285_AN_RF2G3_DB1_2_S    0
1274
#define AR9285_AN_RF2G4         0x782C
1275
#define AR9285_AN_RF2G4_DB1_3    0xE0000000
1276
#define AR9285_AN_RF2G4_DB1_3_S    29
1277
#define AR9285_AN_RF2G4_DB1_4    0x1C000000
1278
#define AR9285_AN_RF2G4_DB1_4_S    26
1279

1280
#define AR9285_AN_RF2G4_DB2_0    0x03800000
1281
#define AR9285_AN_RF2G4_DB2_0_S    23
1282
#define AR9285_AN_RF2G4_DB2_1    0x00700000
1283
#define AR9285_AN_RF2G4_DB2_1_S    20
1284
#define AR9285_AN_RF2G4_DB2_2    0x000E0000
1285
#define AR9285_AN_RF2G4_DB2_2_S    17
1286
#define AR9285_AN_RF2G4_DB2_3    0x0001C000
1287
#define AR9285_AN_RF2G4_DB2_3_S    14
1288
#define AR9285_AN_RF2G4_DB2_4    0x00003800
1289
#define AR9285_AN_RF2G4_DB2_4_S    11
1290

1291
#define AR9285_AN_RF2G6          0x7834
1292
#define AR9285_AN_RF2G7          0x7838
1293
#define AR9285_AN_RF2G9          0x7840
1294
#define AR9285_AN_RXTXBB1        0x7854
1295
#define AR9285_AN_TOP2           0x7868
1296

1297
#define AR9285_AN_TOP3                  0x786c
1298
#define AR9285_AN_TOP3_XPABIAS_LVL      0x0000000C
1299
#define AR9285_AN_TOP3_XPABIAS_LVL_S    2
1300

1301
#define AR9285_AN_TOP4           0x7870
1302
#define AR9285_AN_TOP4_DEFAULT   0x10142c00
1303
#endif
1304

1305

1306
/******************************************************************************
1307
 * MAC PCU Register Map
1308
******************************************************************************/
1309

1310
#define AR_MAC_PCU_OFFSET(_x)   offsetof(struct mac_pcu_reg, _x)
1311

1312
/* MAC station ID0 - low 32 bits */
1313
#define AR_STA_ID0                 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_L32)
1314
/* MAC station ID1 - upper 16 bits */
1315
#define AR_STA_ID1                 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_U16)
1316
#define AR_STA_ID1_SADH_MASK       0x0000FFFF // Mask for 16 msb of MAC addr
1317
#define AR_STA_ID1_STA_AP          0x00010000 // Device is AP
1318
#define AR_STA_ID1_ADHOC           0x00020000 // Device is ad-hoc
1319
#define AR_STA_ID1_PWR_SAV         0x00040000 // Power save in generated frames
1320
#define AR_STA_ID1_KSRCHDIS        0x00080000 // Key search disable
1321
#define AR_STA_ID1_PCF             0x00100000 // Observe PCF
1322
#define AR_STA_ID1_USE_DEFANT      0x00200000 // Use default antenna
1323
#define AR_STA_ID1_DEFANT_UPDATE   0x00400000 // Update default ant w/TX antenna
1324
#define AR_STA_ID1_RTS_USE_DEF     0x00800000 // Use default antenna to send RTS
1325
#define AR_STA_ID1_ACKCTS_6MB      0x01000000 // Use 6Mb/s rate for ACK & CTS
1326
#define AR_STA_ID1_BASE_RATE_11B   0x02000000 // Use 11b base rate for ACK & CTS
1327
#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames
1328
#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael
1329
#define AR_STA_ID1_KSRCH_MODE      0x10000000 // Look-up unique key when !keyID
1330
#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num
1331
#define AR_STA_ID1_CBCIV_ENDIAN    0x40000000 // IV endian-ness in CBC nonce
1332
#define AR_STA_ID1_MCAST_KSRCH     0x80000000 // Adhoc key search enable
1333

1334
/* MAC BSSID low 32 bits */
1335
#define AR_BSS_ID0           AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_L32)
1336
/* MAC BSSID upper 16 bits / AID */
1337
#define AR_BSS_ID1           AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_U16)
1338
#define AR_BSS_ID1_U16       0x0000FFFF // Mask for upper 16 bits of BSSID
1339
#define AR_BSS_ID1_AID       0x07FF0000 // Mask for association ID
1340
#define AR_BSS_ID1_AID_S     16         // Shift for association ID
1341

1342
/*
1343
 * Added to support dual BSSID/TSF which are needed in the application
1344
 * of Mesh networking. See bug 35189. Note that the only function added
1345
 * with this BSSID2 is to receive multi/broadcast from BSSID2 as well
1346
 */
1347
/* MAC BSSID low 32 bits */
1348
#define AR_BSS2_ID0          AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32)
1349
/* MAC BSSID upper 16 bits / AID */
1350
#define AR_BSS2_ID1          AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16)
1351

1352
/* MAC Beacon average RSSI
1353
 *
1354
 * This register holds the average RSSI with 1/16 dB resolution.
1355
 * The RSSI is averaged over multiple beacons which matched our BSSID.
1356
 * Note that AVE_VALUE is 12 bits with 4 bits below the normal 8 bits.
1357
 * These lowest 4 bits provide for a resolution of 1/16 dB.
1358
 *
1359
 */
1360
#define AR_BCN_RSSI_AVE      AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_AVE)
1361
#define AR_BCN_RSSI_AVE_VAL  0x00000FFF // Beacon RSSI value
1362
#define AR_BCN_RSSI_AVE_VAL_S 0
1363

1364
/* MAC ACK & CTS time-out */
1365
#define AR_TIME_OUT          AR_MAC_PCU_OFFSET(MAC_PCU_ACK_CTS_TIMEOUT)
1366
#define AR_TIME_OUT_ACK      0x00003FFF // Mask for ACK time-out
1367
#define AR_TIME_OUT_ACK_S    0
1368
#define AR_TIME_OUT_CTS      0x3FFF0000 // Mask for CTS time-out
1369
#define AR_TIME_OUT_CTS_S    16
1370

1371
/* beacon RSSI warning / bmiss threshold */
1372
#define AR_RSSI_THR          AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_CTL)
1373
#define AR_RSSI_THR_VAL      0x000000FF // Beacon RSSI warning threshold
1374
#define AR_RSSI_THR_VAL_S    0
1375
#define AR_RSSI_THR_BM_THR   0x0000FF00 // Mask for Missed beacon threshold
1376
#define AR_RSSI_THR_BM_THR_S 8          // Shift for Missed beacon threshold
1377
#define AR_RSSI_BCN_WEIGHT   0x1F000000 // RSSI average weight
1378
#define AR_RSSI_BCN_WEIGHT_S 24
1379
#define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value
1380

1381
/* MAC transmit latency register */
1382
#define AR_USEC              AR_MAC_PCU_OFFSET(MAC_PCU_USEC_LATENCY)
1383
#define AR_USEC_USEC         0x000000FF // Mask for clock cycles in 1 usec
1384
#define AR_USEC_USEC_S       0          // Shift for clock cycles in 1 usec
1385
#define AR_USEC_TX_LAT       0x007FC000 // tx latency to start of SIGNAL (usec)
1386
#define AR_USEC_TX_LAT_S     14         // tx latency to start of SIGNAL (usec)
1387
#define AR_USEC_RX_LAT       0x1F800000 // rx latency to start of SIGNAL (usec)
1388
#define AR_USEC_RX_LAT_S     23         // rx latency to start of SIGNAL (usec)
1389

1390
#define AR_SLOT_HALF         13
1391
#define AR_SLOT_QUARTER      21
1392

1393
#define AR_USEC_RX_LATENCY                0x1f800000
1394
#define AR_USEC_RX_LATENCY_S              23
1395
#define AR_RX_LATENCY_FULL                37
1396
#define AR_RX_LATENCY_HALF                74
1397
#define AR_RX_LATENCY_QUARTER             148
1398
#define AR_RX_LATENCY_FULL_FAST_CLOCK     41
1399
#define AR_RX_LATENCY_HALF_FAST_CLOCK     82
1400
#define AR_RX_LATENCY_QUARTER_FAST_CLOCK  163
1401

1402
#define AR_USEC_TX_LATENCY                0x007fc000
1403
#define AR_USEC_TX_LATENCY_S              14
1404
#define AR_TX_LATENCY_FULL                54
1405
#define AR_TX_LATENCY_HALF                108
1406
#define AR_TX_LATENCY_QUARTER             216
1407
#define AR_TX_LATENCY_FULL_FAST_CLOCK     54
1408
#define AR_TX_LATENCY_HALF_FAST_CLOCK     119
1409
#define AR_TX_LATENCY_QUARTER_FAST_CLOCK  238
1410

1411
#define AR_USEC_HALF                      19
1412
#define AR_USEC_QUARTER                   9
1413
#define AR_USEC_HALF_FAST_CLOCK           21
1414
#define AR_USEC_QUARTER_FAST_CLOCK        10
1415

1416
#define AR_EIFS_HALF                     175
1417
#define AR_EIFS_QUARTER                  340
1418

1419
#define AR_RESET_TSF        AR_MAC_PCU_OFFSET(MAC_PCU_RESET_TSF)
1420
#define AR_RESET_TSF_ONCE   0x01000000 // reset tsf once ; self-clears bit
1421
#define AR_RESET_TSF2_ONCE  0x02000000 // reset tsf2 once ; self-clears bit
1422

1423
/* MAC CFP Interval (TU/msec) */
1424
#define AR_CFP_PERIOD                   0x8024  /* MAC CFP Interval (TU/msec) */
1425
#define AR_TIMER0                       0x8028  /* MAC Next beacon time (TU/msec) */
1426
#define AR_TIMER1                       0x802c  /* MAC DMA beacon alert time (1/8 TU) */
1427
#define AR_TIMER2                       0x8030  /* MAC Software beacon alert (1/8 TU) */
1428
#define AR_TIMER3                       0x8034  /* MAC ATIM window time */
1429

1430
/* MAC maximum CFP duration */
1431
#define AR_MAX_CFP_DUR      AR_MAC_PCU_OFFSET(MAC_PCU_MAX_CFP_DUR)
1432
#define AR_CFP_VAL          0x0000FFFF // CFP value in uS
1433

1434
/* MAC receive filter register */
1435
#define AR_RX_FILTER        AR_MAC_PCU_OFFSET(MAC_PCU_RX_FILTER)
1436
#define AR_RX_FILTER_ALL    0x00000000 // Disallow all frames
1437
#define AR_RX_UCAST         0x00000001 // Allow unicast frames
1438
#define AR_RX_MCAST         0x00000002 // Allow multicast frames
1439
#define AR_RX_BCAST         0x00000004 // Allow broadcast frames
1440
#define AR_RX_CONTROL       0x00000008 // Allow control frames
1441
#define AR_RX_BEACON        0x00000010 // Allow beacon frames
1442
#define AR_RX_PROM          0x00000020 // Promiscuous mode all packets
1443
#define AR_RX_PROBE_REQ     0x00000080 // Any probe request frameA
1444
#define AR_RX_MY_BEACON     0x00000200 // Any beacon frame with matching BSSID
1445
#define AR_RX_COMPR_BAR     0x00000400 // Compressed directed block ack request
1446
#define AR_RX_COMPR_BA      0x00000800 // Compressed directed block ack
1447
#define AR_RX_UNCOM_BA_BAR  0x00001000 // Uncompressed directed BA or BAR
1448
#define AR_RX_HWBCNPROC_EN  0x00020000 // Enable hw beacon processing (see AR_HWBCNPROC1)
1449
#define AR_RX_CONTROL_WRAPPER 0x00080000 // Control wrapper. Jupiter only.
1450
#define AR_RX_4ADDRESS      0x00100000 // 4-Address frames
1451

1452
#define AR_PHY_ERR_MASK_REG    AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT)
1453

1454

1455
/* MAC multicast filter lower 32 bits */
1456
#define AR_MCAST_FIL0       AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_L32)
1457
/* MAC multicast filter upper 32 bits */
1458
#define AR_MCAST_FIL1       AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_U32)
1459

1460
/* MAC PCU diagnostic switches */
1461
#define AR_DIAG_SW                  AR_MAC_PCU_OFFSET(MAC_PCU_DIAG_SW)
1462
#define AR_DIAG_CACHE_ACK           0x00000001 // disable ACK when no valid key
1463
#define AR_DIAG_ACK_DIS             0x00000002 // disable ACK generation
1464
#define AR_DIAG_CTS_DIS             0x00000004 // disable CTS generation
1465
#define AR_DIAG_ENCRYPT_DIS         0x00000008 // disable encryption
1466
#define AR_DIAG_DECRYPT_DIS         0x00000010 // disable decryption
1467
#define AR_DIAG_RX_DIS              0x00000020 // disable receive
1468
#define AR_DIAG_LOOP_BACK           0x00000040 // enable loopback
1469
#define AR_DIAG_CORR_FCS            0x00000080 // corrupt FCS
1470
#define AR_DIAG_CHAN_INFO           0x00000100 // dump channel info
1471
#define AR_DIAG_FRAME_NV0           0x00020000 // accept w/protocol version !0
1472
#define AR_DIAG_OBS_PT_SEL1         0x000C0000 // observation point select
1473
#define AR_DIAG_OBS_PT_SEL1_S       18 // Shift for observation point select
1474
#define AR_DIAG_FORCE_RX_CLEAR      0x00100000 // force rx_clear high
1475
#define AR_DIAG_IGNORE_VIRT_CS      0x00200000 // ignore virtual carrier sense
1476
#define AR_DIAG_FORCE_CH_IDLE_HIGH  0x00400000 // force channel idle high
1477
#define AR_DIAG_EIFS_CTRL_ENA       0x00800000 // use framed and ~wait_wep if 0
1478
#define AR_DIAG_DUAL_CHAIN_INFO     0x01000000 // dual chain channel info
1479
#define AR_DIAG_RX_ABORT            0x02000000 //  abort rx
1480
#define AR_DIAG_SATURATE_CYCLE_CNT  0x04000000 // saturate cycle cnts (no shift)
1481
#define AR_DIAG_OBS_PT_SEL2         0x08000000 // Mask for observation point sel
1482
#define AR_DIAG_OBS_PT_SEL2_S       27
1483
#define AR_DIAG_RX_CLEAR_CTL_LOW    0x10000000 // force rx_clear (ctl) low (i.e. busy)
1484
#define AR_DIAG_RX_CLEAR_EXT_LOW    0x20000000 // force rx_clear (ext) low (i.e. busy)
1485

1486
/* MAC local clock lower 32 bits */
1487
#define AR_TSF_L32          AR_MAC_PCU_OFFSET(MAC_PCU_TSF_L32)
1488
/* MAC local clock upper 32 bits */
1489
#define AR_TSF_U32          AR_MAC_PCU_OFFSET(MAC_PCU_TSF_U32)
1490

1491
/*
1492
 * Secondary TSF support added for dual BSSID/TSF
1493
 * which is needed in the application of DirectConnect or
1494
 * Mesh networking
1495
 */
1496
/* MAC local clock lower 32 bits */
1497
#define AR_TSF2_L32         AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32)
1498
/* MAC local clock upper 32 bits */
1499
#define AR_TSF2_U32         AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32)
1500

1501
/* ADDAC test register */
1502
#define AR_TST_ADDAC        AR_MAC_PCU_OFFSET(MAC_PCU_TST_ADDAC)
1503

1504
#define AR_TST_ADDAC_TST_MODE 0x1
1505
#define AR_TST_ADDAC_TST_MODE_S 0
1506
#define AR_TST_ADDAC_TST_LOOP_ENA 0x2
1507
#define AR_TST_ADDAC_TST_LOOP_ENA_S 1
1508
#define AR_TST_ADDAC_BEGIN_CAPTURE 0x80000
1509
#define AR_TST_ADDAC_BEGIN_CAPTURE_S 19
1510

1511
/* default antenna register */
1512
#define AR_DEF_ANTENNA      AR_MAC_PCU_OFFSET(MAC_PCU_DEF_ANTENNA)
1513

1514
/* MAC AES mute mask */
1515
#define AR_AES_MUTE_MASK0       AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_0)
1516
#define AR_AES_MUTE_MASK0_FC    0x0000FFFF // frame ctrl mask bits
1517
#define AR_AES_MUTE_MASK0_QOS   0xFFFF0000 // qos ctrl mask bits
1518
#define AR_AES_MUTE_MASK0_QOS_S 16
1519

1520
/* MAC AES mute mask 1 */
1521
#define AR_AES_MUTE_MASK1       AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_1)
1522
#define AR_AES_MUTE_MASK1_SEQ                       0x0000FFFF // seq + frag mask bits
1523
#define AR_AES_MUTE_MASK1_FC_MGMT                   0xFFFF0000   // frame ctrl mask for mgmt frames (Sowl)
1524
#define AR_AES_MUTE_MASK1_FC_MGMT_S                 16
1525

1526
/* control clock domain */
1527
#define AR_GATED_CLKS       AR_MAC_PCU_OFFSET(MAC_PCU_GATED_CLKS)
1528
#define AR_GATED_CLKS_TX    0x00000002
1529
#define AR_GATED_CLKS_RX    0x00000004
1530
#define AR_GATED_CLKS_REG   0x00000008
1531

1532
/* MAC PCU observation bus 2 */
1533
#define AR_OBS_BUS_CTRL     AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_2)
1534
#define AR_OBS_BUS_SEL_1    0x00040000
1535
#define AR_OBS_BUS_SEL_2    0x00080000
1536
#define AR_OBS_BUS_SEL_3    0x000C0000
1537
#define AR_OBS_BUS_SEL_4    0x08040000
1538
#define AR_OBS_BUS_SEL_5    0x08080000
1539

1540
/* MAC PCU observation bus 1 */
1541
#define AR_OBS_BUS_1               AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_1)
1542
#define AR_OBS_BUS_1_PCU           0x00000001
1543
#define AR_OBS_BUS_1_RX_END        0x00000002
1544
#define AR_OBS_BUS_1_RX_WEP        0x00000004
1545
#define AR_OBS_BUS_1_RX_BEACON     0x00000008
1546
#define AR_OBS_BUS_1_RX_FILTER     0x00000010
1547
#define AR_OBS_BUS_1_TX_HCF        0x00000020
1548
#define AR_OBS_BUS_1_QUIET_TIME    0x00000040
1549
#define AR_OBS_BUS_1_CHAN_IDLE     0x00000080
1550
#define AR_OBS_BUS_1_TX_HOLD       0x00000100
1551
#define AR_OBS_BUS_1_TX_FRAME      0x00000200
1552
#define AR_OBS_BUS_1_RX_FRAME      0x00000400
1553
#define AR_OBS_BUS_1_RX_CLEAR      0x00000800
1554
#define AR_OBS_BUS_1_WEP_STATE     0x0003F000
1555
#define AR_OBS_BUS_1_WEP_STATE_S   12
1556
#define AR_OBS_BUS_1_RX_STATE      0x01F00000
1557
#define AR_OBS_BUS_1_RX_STATE_S    20
1558
#define AR_OBS_BUS_1_TX_STATE      0x7E000000
1559
#define AR_OBS_BUS_1_TX_STATE_S    25
1560

1561
/* MAC PCU dynamic MIMO power save */
1562
#define AR_PCU_SMPS                  AR_MAC_PCU_OFFSET(MAC_PCU_DYM_MIMO_PWR_SAVE)
1563
#define AR_PCU_SMPS_MAC_CHAINMASK    0x00000001     // Use the Rx Chainmask of MAC's setting
1564
#define AR_PCU_SMPS_HW_CTRL_EN       0x00000002     // Enable hardware control of dynamic MIMO PS
1565
#define AR_PCU_SMPS_SW_CTRL_HPWR     0x00000004     // Software controlled High power chainmask setting
1566
#define AR_PCU_SMPS_LPWR_CHNMSK      0x00000070     // Low power setting of Rx Chainmask
1567
#define AR_PCU_SMPS_LPWR_CHNMSK_S    4
1568
#define AR_PCU_SMPS_HPWR_CHNMSK      0x00000700     // High power setting of Rx Chainmask
1569
#define AR_PCU_SMPS_HPWR_CHNMSK_S    8
1570
#define AR_PCU_SMPS_LPWR_CHNMSK_VAL  0x1
1571

1572
/* MAC PCU frame start time trigger for the AP's Downlink Traffic in TDMA mode */
1573
#define AR_TDMA_TXSTARTTRIG_LSB     AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB)
1574
#define AR_TDMA_TXSTARTTRIG_MSB     AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB)
1575

1576
/* MAC Time stamp of the last beacon received */
1577
#define AR_LAST_TSTP        AR_MAC_PCU_OFFSET(MAC_PCU_LAST_BEACON_TSF)
1578
/* MAC current NAV value */
1579
#define AR_NAV              AR_MAC_PCU_OFFSET(MAC_PCU_NAV)
1580
/* MAC RTS exchange success counter */
1581
#define AR_RTS_OK           AR_MAC_PCU_OFFSET(MAC_PCU_RTS_SUCCESS_CNT)
1582
/* MAC RTS exchange failure counter */
1583
#define AR_RTS_FAIL         AR_MAC_PCU_OFFSET(MAC_PCU_RTS_FAIL_CNT)
1584
/* MAC ACK failure counter */
1585
#define AR_ACK_FAIL         AR_MAC_PCU_OFFSET(MAC_PCU_ACK_FAIL_CNT)
1586
/* MAC FCS check failure counter */
1587
#define AR_FCS_FAIL         AR_MAC_PCU_OFFSET(MAC_PCU_FCS_FAIL_CNT)
1588
/* MAC Valid beacon value */
1589
#define AR_BEACON_CNT       AR_MAC_PCU_OFFSET(MAC_PCU_BEACON_CNT)
1590

1591
/* MAC PCU tdma slot alert control */
1592
#define AR_TDMA_SLOT_ALERT_CNTL     AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_SLOT_ALERT_CNTL)
1593

1594
/* MAC PCU Basic MCS set for MCS 0 to 31 */
1595
#define AR_BASIC_SET        AR_MAC_PCU_OFFSET(MAC_PCU_BASIC_SET)
1596
#define ALL_RATE            0xff
1597

1598
/* MAC_PCU_ _SEQ */
1599
#define AR_MGMT_SEQ         AR_MAC_PCU_OFFSET(MAC_PCU_MGMT_SEQ)
1600
#define AR_MGMT_SEQ_MIN     0xFFF       /* sequence minimum value*/
1601
#define AR_MGMT_SEQ_MIN_S   0
1602
#define AR_MIN_HW_SEQ       0
1603
#define AR_MGMT_SEQ_MAX     0xFFF0000   /* sequence maximum value*/
1604
#define AR_MGMT_SEQ_MAX_S   16
1605
#define AR_MAX_HW_SEQ       0xFF
1606
/*MAC PCU Key Cache Antenna 1 */
1607
#define AR_TX_ANT_1     AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_1)
1608
/*MAC PCU Key Cache Antenna 2 */
1609
#define AR_TX_ANT_2     AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_2)
1610
/*MAC PCU Key Cache Antenna 3 */
1611
#define AR_TX_ANT_3     AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_3)
1612
/*MAC PCU Key Cache Antenna 4 */
1613
#define AR_TX_ANT_4     AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_4)
1614

1615

1616
/* Extended range mode */
1617
#define AR_XRMODE                   AR_MAC_PCU_OFFSET(MAC_PCU_XRMODE)
1618
/* Extended range mode delay */
1619
#define AR_XRDEL                    AR_MAC_PCU_OFFSET(MAC_PCU_XRDEL)
1620
/* Extended range mode timeout */
1621
#define AR_XRTO                     AR_MAC_PCU_OFFSET(MAC_PCU_XRTO)
1622
/* Extended range mode chirp */
1623
#define AR_XRCRP                    AR_MAC_PCU_OFFSET(MAC_PCU_XRCRP)
1624
/* Extended range stomp */
1625
#define AR_XRSTMP                   AR_MAC_PCU_OFFSET(MAC_PCU_XRSTMP)
1626

1627

1628
/* Enhanced sleep control 1 */
1629
#define AR_SLEEP1               AR_MAC_PCU_OFFSET(MAC_PCU_SLP1)
1630
#define AR_SLEEP1_ASSUME_DTIM   0x00080000 // Assume DTIM on missed beacon
1631
#define AR_SLEEP1_CAB_TIMEOUT   0xFFE00000 // Cab timeout(TU) mask
1632
#define AR_SLEEP1_CAB_TIMEOUT_S 21         // Cab timeout(TU) shift
1633

1634
/* Enhanced sleep control 2 */
1635
#define AR_SLEEP2               AR_MAC_PCU_OFFSET(MAC_PCU_SLP2)
1636
#define AR_SLEEP2_BEACON_TIMEOUT    0xFFE00000 // Beacon timeout(TU) mask
1637
#define AR_SLEEP2_BEACON_TIMEOUT_S  21         // Beacon timeout(TU) shift
1638

1639
/*MAC_PCU_SELF_GEN_DEFAULT*/
1640
#define AR_SELFGEN              AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_DEFAULT)
1641
#define AR_MMSS                 0x00000007
1642
#define AR_MMSS_S               0
1643
#define AR_SELFGEN_MMSS_NO RESTRICTION  0
1644
#define AR_SELFGEN_MMSS_ONEOVER4_us     1
1645
#define AR_SELFGEN_MMSS_ONEOVER2_us     2
1646
#define AR_SELFGEN_MMSS_ONE_us          3
1647
#define AR_SELFGEN_MMSS_TWO_us          4
1648
#define AR_SELFGEN_MMSS_FOUR_us         5
1649
#define AR_SELFGEN_MMSS_EIGHT_us        6
1650
#define AR_SELFGEN_MMSS_SIXTEEN_us      7
1651

1652
#define AR_CEC                  0x00000018
1653
#define AR_CEC_S                3
1654
/* Although in original standard 0 is for 1 stream and 1 is for 2 stream */
1655
/*  due to H/W resaon, Here should set 1 for 1 stream and 2 for 2 stream */
1656
#define AR_SELFGEN_CEC_ONE_SPACETIMESTREAM      1   
1657
#define AR_SELFGEN_CEC_TWO_SPACETIMESTREAM      2   
1658

1659
/* BSSID mask lower 32 bits */
1660
#define AR_BSSMSKL              AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_L32)
1661
/* BSSID mask upper 16 bits */
1662
#define AR_BSSMSKU              AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_U16)
1663

1664
/* Transmit power control for gen frames */
1665
#define AR_TPC                 AR_MAC_PCU_OFFSET(MAC_PCU_TPC)
1666
#define AR_TPC_ACK             0x0000003f // ack frames mask
1667
#define AR_TPC_ACK_S           0x00       // ack frames shift
1668
#define AR_TPC_CTS             0x00003f00 // cts frames mask
1669
#define AR_TPC_CTS_S           0x08       // cts frames shift
1670
#define AR_TPC_CHIRP           0x003f0000 // chirp frames mask
1671
#define AR_TPC_CHIRP_S         16         // chirp frames shift
1672
#define AR_TPC_RPT             0x3f000000 // rpt frames mask
1673
#define AR_TPC_RPT_S           24         // rpt frames shift
1674

1675
/* Profile count transmit frames */
1676
#define AR_TFCNT           AR_MAC_PCU_OFFSET(MAC_PCU_TX_FRAME_CNT)
1677
/* Profile count receive frames */
1678
#define AR_RFCNT           AR_MAC_PCU_OFFSET(MAC_PCU_RX_FRAME_CNT)
1679
/* Profile count receive clear */
1680
#define AR_RCCNT           AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_CNT)
1681
/* Profile count cycle counter */
1682
#define AR_CCCNT           AR_MAC_PCU_OFFSET(MAC_PCU_CYCLE_CNT)
1683

1684
/* Quiet time programming for TGh */
1685
#define AR_QUIET1                      AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)
1686
#define AR_QUIET1_NEXT_QUIET_S         0            // TSF of next quiet period (TU)
1687
#define AR_QUIET1_NEXT_QUIET_M         0x0000ffff
1688
#define AR_QUIET1_QUIET_ENABLE         0x00010000   // Enable Quiet time operation
1689
#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000   // ack/cts in quiet period
1690
#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17
1691
#define AR_QUIET2                      AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_2)
1692
#define AR_QUIET2_QUIET_PERIOD_S       0            // Periodicity of quiet period (TU)
1693
#define AR_QUIET2_QUIET_PERIOD_M       0x0000ffff
1694
#define AR_QUIET2_QUIET_DUR_S          16           // quiet period (TU)
1695
#define AR_QUIET2_QUIET_DUR            0xffff0000
1696

1697
/* locate no_ack in qos */
1698
#define AR_QOS_NO_ACK              AR_MAC_PCU_OFFSET(MAC_PCU_QOS_NO_ACK)
1699
#define AR_QOS_NO_ACK_TWO_BIT      0x0000000f // 2 bit sentinel for no-ack
1700
#define AR_QOS_NO_ACK_TWO_BIT_S    0
1701
#define AR_QOS_NO_ACK_BIT_OFF      0x00000070 // offset for no-ack
1702
#define AR_QOS_NO_ACK_BIT_OFF_S    4
1703
#define AR_QOS_NO_ACK_BYTE_OFF     0x00000180 // from end of header
1704
#define AR_QOS_NO_ACK_BYTE_OFF_S   7
1705

1706
/* Phy errors to be filtered */
1707
#define AR_PHY_ERR             AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK)
1708
    /* XXX validate! XXX */
1709
#define AR_PHY_ERR_DCHIRP      0x00000008   // Bit  3 enables double chirp
1710
#define AR_PHY_ERR_RADAR       0x00000020   // Bit  5 is Radar signal
1711
#define AR_PHY_ERR_OFDM_TIMING 0x00020000   // Bit 17 is AH_FALSE detect for OFDM
1712
#define AR_PHY_ERR_CCK_TIMING  0x02000000   // Bit 25 is AH_FALSE detect for CCK
1713

1714
/* MAC PCU extended range latency */
1715
#define AR_XRLAT               AR_MAC_PCU_OFFSET(MAC_PCU_XRLAT)
1716

1717
/* MAC PCU Receive Buffer settings */
1718
#define AR_RXFIFO_CFG          AR_MAC_PCU_OFFSET(MAC_PCU_RXBUF)
1719
#define AR_RXFIFO_CFG_REG_RD_ENA_S 11
1720
#define AR_RXFIFO_CFG_REG_RD_ENA   (0x1 << AR_RXFIFO_CFG_REG_RD_ENA_S)
1721

1722
/* MAC PCU QoS control */
1723
#define AR_MIC_QOS_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_CONTROL)
1724
/* MAC PCU Michael QoS select */
1725
#define AR_MIC_QOS_SELECT  AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_SELECT)
1726

1727
/* PCU Miscellaneous Mode */
1728
#define AR_PCU_MISC                AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)
1729
#define AR_PCU_FORCE_BSSID_MATCH   0x00000001    // force bssid to match
1730
#define AR_PCU_MIC_NEW_LOC_ENA     0x00000004    // tx/rx mic key are together
1731
#define AR_PCU_TX_ADD_TSF          0x00000008    // add tx_tsf + int_tsf
1732
#define AR_PCU_CCK_SIFS_MODE       0x00000010    // assume 11b sifs programmed
1733
#define AR_PCU_RX_ANT_UPDT         0x00000800    // KC_RX_ANT_UPDATE
1734
#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000    // enforce txop / tbtt
1735
#define AR_PCU_MISS_BCN_IN_SLEEP   0x00004000    // count bmiss's when sleeping
1736
#define AR_PCU_BUG_12306_FIX_ENA   0x00020000    // use rx_clear to count sifs
1737
#define AR_PCU_FORCE_QUIET_COLL    0x00040000    // kill xmit for channel change
1738
#define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
1739
#define AR_PCU_BT_ANT_PREVENT_RX_S 20
1740
#define AR_PCU_TBTT_PROTECT        0x00200000    // no xmit upto tbtt + 20 uS
1741
#define AR_PCU_CLEAR_VMF           0x01000000    // clear vmf mode (fast cc)
1742
#define AR_PCU_CLEAR_BA_VALID      0x04000000    // clear ba state
1743
#define AR_PCU_SEL_EVM             0x08000000    // select EVM data or PLCP header
1744
#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 /* always perform key search */
1745
/* count of filtered ofdm */
1746
#define AR_FILT_OFDM           AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_OFDM_CNT)
1747
#define AR_FILT_OFDM_COUNT     0x00FFFFFF        // count of filtered ofdm
1748

1749
/* count of filtered cck */
1750
#define AR_FILT_CCK            AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_CCK_CNT)
1751
#define AR_FILT_CCK_COUNT      0x00FFFFFF        // count of filtered cck
1752

1753
/* MAC PCU PHY error counter 1 */
1754
#define AR_PHY_ERR_1           AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1)
1755
#define AR_PHY_ERR_1_COUNT     0x00FFFFFF        // phy errs that pass mask_1
1756
/* MAC PCU PHY error mask 1 */
1757
#define AR_PHY_ERR_MASK_1      AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1_MASK)
1758

1759
/* MAC PCU PHY error counter 2 */
1760
#define AR_PHY_ERR_2           AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2)
1761
#define AR_PHY_ERR_2_COUNT     0x00FFFFFF        // phy errs that pass mask_2
1762
/* MAC PCU PHY error mask 2 */
1763
#define AR_PHY_ERR_MASK_2      AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2_MASK)
1764

1765
#define AR_PHY_COUNTMAX        (3 << 22)         // Max counted before intr
1766
#define AR_MIBCNT_INTRMASK     (3 << 22)         // Mask top 2 bits of counters
1767

1768
/* interrupt if rx_tsf-int_tsf */
1769
#define AR_TSFOOR_THRESHOLD     AR_MAC_PCU_OFFSET(MAC_PCU_TSF_THRESHOLD)
1770
#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF       // field width
1771

1772
/* MAC PCU PHY error counter 3 */
1773
#define AR_PHY_ERR_3           AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3)
1774
#define AR_PHY_ERR_3_COUNT     0x00FFFFFF        // phy errs that pass mask_3
1775
/* MAC PCU PHY error mask 3 */
1776
#define AR_PHY_ERR_MASK_3      AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3_MASK)
1777

1778
/* Bluetooth coexistance mode */
1779
#define AR_BT_COEX_MODE            AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE)
1780
#define AR_BT_TIME_EXTEND          0x000000ff
1781
#define AR_BT_TIME_EXTEND_S        0
1782
#define AR_BT_TXSTATE_EXTEND       0x00000100
1783
#define AR_BT_TXSTATE_EXTEND_S     8
1784
#define AR_BT_TX_FRAME_EXTEND      0x00000200
1785
#define AR_BT_TX_FRAME_EXTEND_S    9
1786
#define AR_BT_MODE                 0x00000c00
1787
#define AR_BT_MODE_S               10
1788
#define AR_BT_QUIET                0x00001000
1789
#define AR_BT_QUIET_S              12
1790
#define AR_BT_QCU_THRESH           0x0001e000
1791
#define AR_BT_QCU_THRESH_S         13
1792
#define AR_BT_RX_CLEAR_POLARITY    0x00020000
1793
#define AR_BT_RX_CLEAR_POLARITY_S  17
1794
#define AR_BT_PRIORITY_TIME        0x00fc0000
1795
#define AR_BT_PRIORITY_TIME_S      18
1796
#define AR_BT_FIRST_SLOT_TIME      0xff000000
1797
#define AR_BT_FIRST_SLOT_TIME_S    24
1798

1799
/* BlueTooth coexistance WLAN weights */
1800
#define AR_BT_COEX_WL_WEIGHTS0     AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS0)
1801
#define AR_BT_BT_WGHT              0x0000ffff
1802
#define AR_BT_BT_WGHT_S            0
1803
#define AR_BT_WL_WGHT              0xffff0000
1804
#define AR_BT_WL_WGHT_S            16
1805

1806
/* HCF timeout: Slotted behavior */
1807
#define AR_HCFTO                   AR_MAC_PCU_OFFSET(MAC_PCU_HCF_TIMEOUT)
1808

1809
/* BlueTooth mode 2: Slotted behavior */
1810
#define AR_BT_COEX_MODE2           AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE2)
1811
#define AR_BT_BCN_MISS_THRESH      0x000000ff
1812
#define AR_BT_BCN_MISS_THRESH_S    0
1813
#define AR_BT_BCN_MISS_CNT         0x0000ff00
1814
#define AR_BT_BCN_MISS_CNT_S       8
1815
#define AR_BT_HOLD_RX_CLEAR        0x00010000
1816
#define AR_BT_HOLD_RX_CLEAR_S      16
1817
#define AR_BT_SLEEP_ALLOW_BT       0x00020000
1818
#define AR_BT_SLEEP_ALLOW_BT_S     17
1819
#define AR_BT_PROTECT_AFTER_WAKE   0x00080000
1820
#define AR_BT_PROTECT_AFTER_WAKE_S 19
1821
#define AR_BT_DISABLE_BT_ANT       0x00100000
1822
#define AR_BT_DISABLE_BT_ANT_S     20
1823
#define AR_BT_QUIET_2_WIRE         0x00200000
1824
#define AR_BT_QUIET_2_WIRE_S       21
1825
#define AR_BT_WL_ACTIVE_MODE       0x00c00000
1826
#define AR_BT_WL_ACTIVE_MODE_S     22
1827
#define AR_BT_WL_TXRX_SEPARATE     0x01000000
1828
#define AR_BT_WL_TXRX_SEPARATE_S   24
1829
#define AR_BT_RS_DISCARD_EXTEND    0x02000000
1830
#define AR_BT_RS_DISCARD_EXTEND_S  25
1831
#define AR_BT_TSF_BT_ACTIVE_CTRL   0x0c000000
1832
#define AR_BT_TSF_BT_ACTIVE_CTRL_S 26
1833
#define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000
1834
#define AR_BT_TSF_BT_PRIORITY_CTRL_S 28
1835
#define AR_BT_INTERRUPT_ENABLE     0x40000000
1836
#define AR_BT_INTERRUPT_ENABLE_S   30
1837
#define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000
1838
#define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31
1839

1840
/* Generic Timers 2 */
1841
#define AR_GEN_TIMERS2_0                    AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2)
1842
#define AR_GEN_TIMERS2_NEXT(_i)            (AR_GEN_TIMERS2_0 + ((_i)<<2))
1843
#define AR_GEN_TIMERS2_PERIOD(_i)          (AR_GEN_TIMERS2_NEXT(8) + ((_i)<<2))
1844

1845
#define AR_GEN_TIMERS2_0_NEXT               AR_GEN_TIMERS2_NEXT(0)
1846
#define AR_GEN_TIMERS2_1_NEXT               AR_GEN_TIMERS2_NEXT(1)
1847
#define AR_GEN_TIMERS2_2_NEXT               AR_GEN_TIMERS2_NEXT(2)
1848
#define AR_GEN_TIMERS2_3_NEXT               AR_GEN_TIMERS2_NEXT(3)
1849
#define AR_GEN_TIMERS2_4_NEXT               AR_GEN_TIMERS2_NEXT(4)
1850
#define AR_GEN_TIMERS2_5_NEXT               AR_GEN_TIMERS2_NEXT(5)
1851
#define AR_GEN_TIMERS2_6_NEXT               AR_GEN_TIMERS2_NEXT(6)
1852
#define AR_GEN_TIMERS2_7_NEXT               AR_GEN_TIMERS2_NEXT(7)
1853
#define AR_GEN_TIMERS2_0_PERIOD             AR_GEN_TIMERS2_PERIOD(0)
1854
#define AR_GEN_TIMERS2_1_PERIOD             AR_GEN_TIMERS2_PERIOD(1)
1855
#define AR_GEN_TIMERS2_2_PERIOD             AR_GEN_TIMERS2_PERIOD(2)
1856
#define AR_GEN_TIMERS2_3_PERIOD             AR_GEN_TIMERS2_PERIOD(3)
1857
#define AR_GEN_TIMERS2_4_PERIOD             AR_GEN_TIMERS2_PERIOD(4)
1858
#define AR_GEN_TIMERS2_5_PERIOD             AR_GEN_TIMERS2_PERIOD(5)
1859
#define AR_GEN_TIMERS2_6_PERIOD             AR_GEN_TIMERS2_PERIOD(6)
1860
#define AR_GEN_TIMERS2_7_PERIOD             AR_GEN_TIMERS2_PERIOD(7)
1861

1862
#define AR_GEN_TIMER_BANK_1_LEN             8
1863
#define AR_FIRST_NDP_TIMER                  7
1864
#define AR_NUM_GEN_TIMERS                   16
1865
#define AR_GEN_TIMER_RESERVED               8
1866

1867
/* Generic Timers 2 Mode */
1868
#define AR_GEN_TIMERS2_MODE        AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2_MODE)
1869

1870
/* BlueTooth coexistance WLAN weights 1 */
1871
#define AR_BT_COEX_WL_WEIGHTS1     AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS1)
1872

1873
/* BlueTooth Coexistence TSF Snapshot for BT_ACTIVE */
1874
#define AR_BT_TSF_ACTIVE           AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE)
1875

1876
/* BlueTooth Coexistence TSF Snapshot for BT_PRIORITY */
1877
#define AR_BT_TSF_PRIORITY         AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY)
1878

1879
/* SIFS, TX latency and ACK shift */
1880
#define AR_TXSIFS              AR_MAC_PCU_OFFSET(MAC_PCU_TXSIFS)
1881
#define AR_TXSIFS_TIME         0x000000FF        // uS in SIFS
1882
#define AR_TXSIFS_TX_LATENCY   0x00000F00        // uS for transmission thru bb
1883
#define AR_TXSIFS_TX_LATENCY_S 8
1884
#define AR_TXSIFS_ACK_SHIFT    0x00007000        // chan width for ack
1885
#define AR_TXSIFS_ACK_SHIFT_S  12
1886

1887
/* BlueTooth mode 3 */
1888
#define AR_BT_COEX_MODE3           AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE3)
1889

1890

1891
/* TXOP for legacy non-qos */
1892
#define AR_TXOP_X          AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_X)
1893
#define AR_TXOP_X_VAL      0x000000FF
1894

1895
/* TXOP for TID 0 to 3 */
1896
#define AR_TXOP_0_3    AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_0_3)
1897
/* TXOP for TID 4 to 7 */
1898
#define AR_TXOP_4_7    AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_4_7)
1899
/* TXOP for TID 8 to 11 */
1900
#define AR_TXOP_8_11   AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_8_11)
1901
/* TXOP for TID 12 to 15 */
1902
#define AR_TXOP_12_15  AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_12_15)
1903

1904
/* Generic Timers */
1905
#define AR_GEN_TIMERS_0           AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS)
1906
#define AR_GEN_TIMERS(_i)         (AR_GEN_TIMERS_0 + ((_i)<<2))
1907

1908
/* generic timers based on tsf - all uS */
1909
#define AR_NEXT_TBTT_TIMER                  AR_GEN_TIMERS(0)
1910
#define AR_NEXT_DMA_BEACON_ALERT            AR_GEN_TIMERS(1)
1911
#define AR_NEXT_SWBA                        AR_GEN_TIMERS(2)
1912
#define AR_NEXT_HCF                         AR_GEN_TIMERS(3)
1913
#define AR_NEXT_TIM                         AR_GEN_TIMERS(4)
1914
#define AR_NEXT_DTIM                        AR_GEN_TIMERS(5)
1915
#define AR_NEXT_QUIET_TIMER                 AR_GEN_TIMERS(6)
1916
#define AR_NEXT_NDP_TIMER                   AR_GEN_TIMERS(7)
1917
#define AR_BEACON_PERIOD                    AR_GEN_TIMERS(8)
1918
#define AR_DMA_BEACON_PERIOD                AR_GEN_TIMERS(9)
1919
#define AR_SWBA_PERIOD                      AR_GEN_TIMERS(10)
1920
#define AR_HCF_PERIOD                       AR_GEN_TIMERS(11)
1921
#define AR_TIM_PERIOD                       AR_GEN_TIMERS(12)
1922
#define AR_DTIM_PERIOD                      AR_GEN_TIMERS(13)
1923
#define AR_QUIET_PERIOD                     AR_GEN_TIMERS(14)
1924
#define AR_NDP_PERIOD                       AR_GEN_TIMERS(15)
1925

1926
/* Generic Timers Mode */
1927
#define AR_TIMER_MODE                       AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_MODE)
1928
#define AR_TBTT_TIMER_EN                    0x00000001
1929
#define AR_DBA_TIMER_EN                     0x00000002
1930
#define AR_SWBA_TIMER_EN                    0x00000004
1931
#define AR_HCF_TIMER_EN                     0x00000008
1932
#define AR_TIM_TIMER_EN                     0x00000010
1933
#define AR_DTIM_TIMER_EN                    0x00000020
1934
#define AR_QUIET_TIMER_EN                   0x00000040
1935
#define AR_NDP_TIMER_EN                     0x00000080
1936
#define AR_TIMER_OVERFLOW_INDEX             0x00000700
1937
#define AR_TIMER_OVERFLOW_INDEX_S           8
1938
#define AR_TIMER_THRESH                     0xFFFFF000
1939
#define AR_TIMER_THRESH_S                   12
1940

1941
#define AR_SLP32_MODE                  AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_MODE)
1942
#define AR_SLP32_HALF_CLK_LATENCY      0x000FFFFF    // rising <-> falling edge
1943
#define AR_SLP32_ENA                   0x00100000
1944
#define AR_SLP32_TSF_WRITE_STATUS      0x00200000    // tsf update in progress
1945

1946
#define AR_SLP32_WAKE                  AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_WAKE)
1947
#define AR_SLP32_WAKE_XTL_TIME         0x0000FFFF    // time to wake crystal
1948

1949
#define AR_SLP32_INC                   AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_INC)
1950
#define AR_SLP32_TST_INC               0x000FFFFF
1951

1952
/* Sleep MIB cycle count 32kHz cycles for which mac is asleep */
1953
#define AR_SLP_CNT         AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB1)
1954
#define AR_SLP_CYCLE_CNT   0x8254    // absolute number of 32kHz cycles
1955

1956
/* Sleep MIB cycle count 2 */
1957
#define AR_SLP_MIB2        AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB2)
1958

1959
/* Sleep MIB control status */
1960
#define AR_SLP_MIB_CTRL    AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB3)
1961
#define AR_SLP_MIB_CLEAR   0x00000001    // clear pending
1962
#define AR_SLP_MIB_PENDING 0x00000002    // clear counters
1963

1964
//#ifdef AR9300_EMULATION
1965
// MAC trace buffer registers (emulation only)
1966
#define AR_MAC_PCU_LOGIC_ANALYZER               AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER)
1967
#define AR_MAC_PCU_LOGIC_ANALYZER_CTL           0x0000000F
1968
#define AR_MAC_PCU_LOGIC_ANALYZER_HOLD          0x00000001
1969
#define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR         0x00000002
1970
#define AR_MAC_PCU_LOGIC_ANALYZER_STATE         0x00000004
1971
#define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE        0x00000008
1972
#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL       0x000000F0
1973
#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S     4
1974
#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR      0x0003FF00
1975
#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S    8
1976

1977
#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE     0xFFFC0000
1978
#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S   18
1979
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614   0x00040000
1980
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768   0x20000000
1981
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803   0x40000000
1982
#define AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996  0x9d500010
1983
#define AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE       0x9d400010
1984

1985
#define AR_MAC_PCU_LOGIC_ANALYZER_32L           AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_32L)
1986
#define AR_MAC_PCU_LOGIC_ANALYZER_16U           AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_16U)
1987

1988
#define AR_MAC_PCU_TRACE_REG_START      0xE000
1989
#define AR_MAC_PCU_TRACE_REG_END        0xFFFC
1990
#define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(uint32_t))
1991
//#endif  // AR9300_EMULATION
1992

1993
/* MAC PCU global mode register */
1994
#define AR_2040_MODE                    AR_MAC_PCU_OFFSET(MAC_PCU_20_40_MODE)
1995
#define AR_2040_JOINED_RX_CLEAR         0x00000001   // use ctl + ext rx_clear for cca
1996

1997
/* MAC PCU H transfer timeout register */
1998
#define AR_H_XFER_TIMEOUT               AR_MAC_PCU_OFFSET(MAC_PCU_H_XFER_TIMEOUT)
1999
#define AR_EXBF_IMMDIATE_RESP           0x00000040
2000
#define AR_EXBF_NOACK_NO_RPT            0x00000100
2001
#define AR_H_XFER_TIMEOUT_COUNT         0xf
2002
#define AR_H_XFER_TIMEOUT_COUNT_S       0
2003

2004
/*
2005
 * Additional cycle counter. See also AR_CCCNT
2006
 * extension channel rx clear count
2007
 * counts number of cycles rx_clear (ext) is low (i.e. busy)
2008
 * when the MAC is not actively transmitting/receiving
2009
 */
2010
#define AR_EXTRCCNT             AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_DIFF_CNT)
2011

2012
/* antenna mask for self generated files */
2013
#define AR_SELFGEN_MASK         AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_ANTENNA_MASK)
2014

2015
/* control registers for block BA control fields */
2016
#define AR_BA_BAR_CONTROL       AR_MAC_PCU_OFFSET(MAC_PCU_BA_BAR_CONTROL)
2017

2018
/* legacy PLCP spoof */
2019
#define AR_LEG_PLCP_SPOOF       AR_MAC_PCU_OFFSET(MAC_PCU_LEGACY_PLCP_SPOOF)
2020

2021
/* PHY error mask and EIFS mask continued */
2022
#define AR_PHY_ERR_MASK_CONT    AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT)
2023

2024
/* MAC PCU transmit timer */
2025
#define AR_TX_TIMER             AR_MAC_PCU_OFFSET(MAC_PCU_TX_TIMER)
2026

2027
/* MAC PCU transmit buffer control */
2028
#define AR_PCU_TXBUF_CTRL               AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_CTRL)
2029
#define AR_PCU_TXBUF_CTRL_SIZE_MASK     0x7FF
2030
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
2031

2032
/*
2033
 * MAC PCU miscellaneous mode 2
2034
 * WAR flags for various bugs, see mac_pcu_reg documentation.
2035
 */
2036
#define AR_PCU_MISC_MODE2               AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE2)
2037
#define AR_PCU_MISC_MODE2_BUG_21532_ENABLE             0x00000001
2038
#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE           0x00000002   /* Decrypt MGT frames using MFP method */
2039
#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT   0x00000004   /* Don't decrypt MGT frames at all */
2040

2041
#define AR_BUG_58603_FIX_ENABLE                        0x00000008   /* Enable fix for bug 58603. This allows
2042
                                                                     * the use of AR_AGG_WEP_ENABLE.
2043
                                                                     */
2044

2045
#define AR_PCU_MISC_MODE2_PROM_VC_MODE                 0xa148103b   /* Enable promiscous in azimuth mode */
2046

2047
#define AR_PCU_MISC_MODE2_RESERVED                     0x00000038
2048

2049
#define AR_ADHOC_MCAST_KEYID_ENABLE                    0x00000040   /* This bit enables the Multicast search
2050
                                                                     * based on both MAC Address and Key ID.
2051
                                                                     * If bit is 0, then Multicast search is
2052
                                                                     * based on MAC address only.
2053
                                                                     * For Merlin and above only.
2054
                                                                     */
2055

2056
#define AR_PCU_MISC_MODE2_CFP_IGNORE                   0x00000080
2057
#define AR_PCU_MISC_MODE2_MGMT_QOS                     0x0000FF00 
2058
#define AR_PCU_MISC_MODE2_MGMT_QOS_S                   8
2059
#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000
2060
#define AR_AGG_WEP_ENABLE                              0x00020000   /* This field enables AGG_WEP feature,
2061
                                                                     * when it is enable, AGG_WEP would takes
2062
                                                                     * charge of the encryption interface of
2063
                                                                     * pcu_txsm.
2064
                                                                     */
2065
#define AR_PCU_MISC_MODE2_HWWAR1                       0x00100000
2066
#define AR_PCU_MISC_MODE2_PROXY_STA                    0x01000000  /* see EV 75996 */ 
2067
#define AR_PCU_MISC_MODE2_HWWAR2                       0x02000000
2068
#define AR_DECOUPLE_DECRYPTION                         0x08000000
2069

2070
#define AR_PCU_MISC_MODE2_RESERVED2                    0xFFFE0000
2071

2072
/* MAC PCU Alternate AES QoS mute mask */
2073
#define AR_ALT_AES_MUTE_MASK            AR_MAC_PCU_OFFSET(MAC_PCU_ALT_AES_MUTE_MASK)
2074

2075
/* Async Fifo registers - debug only */
2076
#define AR_ASYNC_FIFO_1                 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG1)
2077
#define AR_ASYNC_FIFO_2                 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG2)
2078
#define AR_ASYNC_FIFO_3                 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG3)
2079

2080
/* Maps the 16 user priority TID values to Access categories */
2081
#define AR_TID_TO_AC_MAP                AR_MAC_PCU_OFFSET(MAC_PCU_TID_TO_AC)
2082

2083
/* High Priority Queue Control */
2084
#define AR_HP_Q_CONTROL                 AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE)
2085

2086
/* Rx High Priority Queue Control */
2087
#define AR_HPQ_CONTROL                  AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE)
2088
#define AR_HPQ_ENABLE                   0x00000001
2089
#define AR_HPQ_MASK_BE                  0x00000002
2090
#define AR_HPQ_MASK_BK                  0x00000004
2091
#define AR_HPQ_MASK_VI                  0x00000008
2092
#define AR_HPQ_MASK_VO                  0x00000010
2093
#define AR_HPQ_UAPSD                    0x00000020
2094
#define AR_HPQ_FRAME_FILTER_0           0x00000040
2095
#define AR_HPQ_FRAME_BSSID_MATCH_0      0x00000080
2096
#define AR_HPQ_UAPSD_TRIGGER_EN         0x00100000
2097

2098
#define AR_BT_COEX_BT_WEIGHTS0          AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS0)
2099
#define AR_BT_COEX_BT_WEIGHTS1          AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS1)
2100
#define AR_BT_COEX_BT_WEIGHTS2          AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS2)
2101
#define AR_BT_COEX_BT_WEIGHTS3          AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS3)
2102

2103
#define AR_AGC_SATURATION_CNT0          AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT0)
2104
#define AR_AGC_SATURATION_CNT1          AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT1)
2105
#define AR_AGC_SATURATION_CNT2          AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT2)
2106

2107
/* Hardware beacon processing */
2108
#define AR_HWBCNPROC1                   AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC1)
2109
#define AR_HWBCNPROC1_CRC_ENABLE        0x00000001  /* Enable hw beacon processing */
2110
#define AR_HWBCNPROC1_RESET_CRC         0x00000002  /* Reset the last beacon CRC calculated */
2111
#define AR_HWBCNPROC1_EXCLUDE_BCN_INTVL 0x00000004  /* Exclude Beacon interval in CRC calculation */
2112
#define AR_HWBCNPROC1_EXCLUDE_CAP_INFO  0x00000008  /* Exclude Beacon capability information in CRC calculation */
2113
#define AR_HWBCNPROC1_EXCLUDE_TIM_ELM   0x00000010  /* Exclude Beacon TIM element in CRC calculation */
2114
#define AR_HWBCNPROC1_EXCLUDE_ELM0      0x00000020  /* Exclude element ID ELM0 in CRC calculation */
2115
#define AR_HWBCNPROC1_EXCLUDE_ELM1      0x00000040  /* Exclude element ID ELM1 in CRC calculation */
2116
#define AR_HWBCNPROC1_EXCLUDE_ELM2      0x00000080  /* Exclude element ID ELM2 in CRC calculation */
2117
#define AR_HWBCNPROC1_ELM0_ID           0x0000FF00  /* Element ID 0 */
2118
#define AR_HWBCNPROC1_ELM0_ID_S         8
2119
#define AR_HWBCNPROC1_ELM1_ID           0x00FF0000  /* Element ID 1 */
2120
#define AR_HWBCNPROC1_ELM1_ID_S         16
2121
#define AR_HWBCNPROC1_ELM2_ID           0xFF000000  /* Element ID 2 */
2122
#define AR_HWBCNPROC1_ELM2_ID_S         24
2123

2124
#define AR_HWBCNPROC2                   AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC2)
2125
#define AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE    0x00000001  /* Enable filtering beacons based on filter interval */
2126
#define AR_HWBCNPROC2_RESET_INTERVAL            0x00000002  /* Reset internal interval counter interval */
2127
#define AR_HWBCNPROC2_EXCLUDE_ELM3              0x00000004  /* Exclude element ID ELM3 in CRC calculation */
2128
#define AR_HWBCNPROC2_RSVD                      0x000000F8  /* reserved */
2129
#define AR_HWBCNPROC2_FILTER_INTERVAL           0x0000FF00  /* Filter interval for beacons */
2130
#define AR_HWBCNPROC2_FILTER_INTERVAL_S         8
2131
#define AR_HWBCNPROC2_ELM3_ID                   0x00FF0000  /* Element ID 3 */
2132
#define AR_HWBCNPROC2_ELM3_ID_S                 16
2133
#define AR_HWBCNPROC2_RSVD2                     0xFF000000  /* reserved */
2134

2135
#define AR_MAC_PCU_MISC_MODE3           AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE3)
2136
#define AR_BUG_61936_FIX_ENABLE         0x00000040  /* EV61936 - rx descriptor corruption */
2137
#define AR_TIME_BASED_DISCARD_EN        0x80000000
2138
#define AR_TIME_BASED_DISCARD_EN_S      31
2139

2140
#define AR_MAC_PCU_GEN_TIMER_TSF_SEL    AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_TSF_SEL)
2141

2142
#define AR_MAC_PCU_TBD_FILTER           AR_MAC_PCU_OFFSET(MAC_PCU_TBD_FILTER)
2143
#define AR_MAC_PCU_USE_WBTIMER_TX_TS    0x00000001
2144
#define AR_MAC_PCU_USE_WBTIMER_TX_TS_S  0
2145
#define AR_MAC_PCU_USE_WBTIMER_RX_TS    0x00000002
2146
#define AR_MAC_PCU_USE_WBTIMER_RX_TS_S  1
2147

2148
#define AR_TXBUF_BA                     AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_BA)
2149

2150

2151
/* MAC Key Cache */
2152
#define AR_KEYTABLE_0           AR_MAC_PCU_OFFSET(MAC_PCU_KEY_CACHE)
2153
#define AR_KEYTABLE(_n)         (AR_KEYTABLE_0 + ((_n)*32))
2154
#define AR_KEY_CACHE_SIZE       128
2155
#define AR_RSVD_KEYTABLE_ENTRIES 4
2156
#define AR_KEY_TYPE             0x00000007 // MAC Key Type Mask
2157
#define AR_KEYTABLE_TYPE_40     0x00000000  /* WEP 40 bit key */
2158
#define AR_KEYTABLE_TYPE_104    0x00000001  /* WEP 104 bit key */
2159
#define AR_KEYTABLE_TYPE_128    0x00000003  /* WEP 128 bit key */
2160
#define AR_KEYTABLE_TYPE_TKIP   0x00000004  /* TKIP and Michael */
2161
#define AR_KEYTABLE_TYPE_AES    0x00000005  /* AES/OCB 128 bit key */
2162
#define AR_KEYTABLE_TYPE_CCM    0x00000006  /* AES/CCM 128 bit key */
2163
#define AR_KEYTABLE_TYPE_CLR    0x00000007  /* no encryption */
2164
#define AR_KEYTABLE_ANT         0x00000008  /* previous transmit antenna */
2165
#define AR_KEYTABLE_UAPSD       0x000001E0  /* UAPSD AC mask */
2166
#define AR_KEYTABLE_UAPSD_S     5
2167
#define AR_KEYTABLE_PWRMGT      0x00000200  /* hw managed PowerMgt bit */
2168

2169
#define AR_KEYTABLE_MMSS        0x00001c00  /* remote's MMSS*/
2170
#define AR_KEYTABLE_MMSS_S      10
2171
#define AR_KEYTABLE_CEC         0x00006000  /* remote's CEC*/
2172
#define AR_KEYTABLE_CEC_S       13
2173
#define AR_KEYTABLE_STAGGED     0x00010000  /* remote's stagged sounding*/
2174
#define AR_KEYTABLE_STAGGED_S   16
2175

2176
#define AR_KEYTABLE_VALID       0x00008000  /* key and MAC address valid */
2177
#define AR_KEYTABLE_KEY0(_n)    (AR_KEYTABLE(_n) + 0)   /* key bit 0-31 */
2178
#define AR_KEYTABLE_KEY1(_n)    (AR_KEYTABLE(_n) + 4)   /* key bit 32-47 */
2179
#define AR_KEYTABLE_KEY2(_n)    (AR_KEYTABLE(_n) + 8)   /* key bit 48-79 */
2180
#define AR_KEYTABLE_KEY3(_n)    (AR_KEYTABLE(_n) + 12)  /* key bit 80-95 */
2181
#define AR_KEYTABLE_KEY4(_n)    (AR_KEYTABLE(_n) + 16)  /* key bit 96-127 */
2182
#define AR_KEYTABLE_TYPE(_n)    (AR_KEYTABLE(_n) + 20)  /* key type */
2183
#define AR_KEYTABLE_MAC0(_n)    (AR_KEYTABLE(_n) + 24)  /* MAC address 1-32 */
2184
#define AR_KEYTABLE_MAC1(_n)    (AR_KEYTABLE(_n) + 28)  /* MAC address 33-47 */
2185
#define AR_KEYTABLE_DIR_ACK_BIT    0x00000010  /* Directed ACK bit */
2186

2187

2188

2189
/*
2190
 * MAC WoW Registers.
2191
 */
2192
#define    AR_WOW_PATTERN_REG          AR_MAC_PCU_OFFSET(MAC_PCU_WOW1)
2193
#define    AR_WOW_PAT_BACKOFF          0x00000004
2194
#define    AR_WOW_BACK_OFF_SHIFT(x)    ((x & 0xf) << 27)    /* in usecs */
2195
#define    AR_WOW_MAC_INTR_EN          0x00040000
2196
#define    AR_WOW_MAGIC_EN             0x00010000
2197
#define    AR_WOW_PATTERN_EN(x)        ((x & 0xff) << 0)
2198
#define    AR_WOW_PATTERN_FOUND_SHIFT  8
2199
#define    AR_WOW_PATTERN_FOUND(x)     (x & (0xff << AR_WOW_PATTERN_FOUND_SHIFT))
2200
#define    AR_WOW_PATTERN_FOUND_MASK   ((0xff) << AR_WOW_PATTERN_FOUND_SHIFT)
2201
#define    AR_WOW_MAGIC_PAT_FOUND      0x00020000
2202
#define    AR_WOW_MAC_INTR             0x00080000
2203
#define    AR_WOW_KEEP_ALIVE_FAIL      0x00100000
2204
#define    AR_WOW_BEACON_FAIL          0x00200000
2205

2206

2207
#define    AR_WOW_COUNT_REG            AR_MAC_PCU_OFFSET(MAC_PCU_WOW2)
2208
#define    AR_WOW_AIFS_CNT(x)          ((x & 0xff) << 0)
2209
#define    AR_WOW_SLOT_CNT(x)          ((x & 0xff) << 8)
2210
#define    AR_WOW_KEEP_ALIVE_CNT(x)    ((x & 0xff) << 16)
2211
/*
2212
 * Default values for Wow Configuration for backoff, aifs, slot, keep-alive, etc.
2213
 * to be programmed into various registers.
2214
 */
2215
#define    AR_WOW_CNT_AIFS_CNT         0x00000022    // AR_WOW_COUNT_REG
2216
#define    AR_WOW_CNT_SLOT_CNT         0x00000009    // AR_WOW_COUNT_REG
2217
/*
2218
 * Keepalive count applicable for Merlin 2.0 and above.
2219
 */
2220
#define    AR_WOW_CNT_KA_CNT           0x00000008    // AR_WOW_COUNT_REG
2221

2222

2223
#define    AR_WOW_BCN_EN_REG           AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON_FAIL)
2224
#define    AR_WOW_BEACON_FAIL_EN       0x00000001
2225

2226
#define    AR_WOW_BCN_TIMO_REG         AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON)
2227
#define    AR_WOW_BEACON_TIMO          0x40000000  /* Valid if BCN_EN is set */
2228
#define    AR_WOW_BEACON_TIMO_MAX      0xFFFFFFFF  /* Max. value for Beacon Timeout */
2229

2230
#define    AR_WOW_KEEP_ALIVE_TIMO_REG  AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_KEEP_ALIVE)
2231
#define    AR_WOW_KEEP_ALIVE_TIMO      0x00007A12
2232
#define    AR_WOW_KEEP_ALIVE_NEVER     0xFFFFFFFF
2233

2234
#define    AR_WOW_KEEP_ALIVE_REG       AR_MAC_PCU_OFFSET(MAC_PCU_WOW_KA)
2235
#define    AR_WOW_KEEP_ALIVE_AUTO_DIS  0x00000001
2236
#define    AR_WOW_KEEP_ALIVE_FAIL_DIS  0x00000002
2237

2238
#define    AR_WOW_US_SCALAR_REG        AR_MAC_PCU_OFFSET(PCU_1US)
2239

2240
#define    AR_WOW_KEEP_ALIVE_DELAY_REG AR_MAC_PCU_OFFSET(PCU_KA)
2241
#define    AR_WOW_KEEP_ALIVE_DELAY     0x000003E8 // 1 msec
2242

2243
#define    AR_WOW_PATTERN_MATCH_REG    AR_MAC_PCU_OFFSET(WOW_EXACT)
2244
#define    AR_WOW_PAT_END_OF_PKT(x)    ((x & 0xf) << 0)
2245
#define    AR_WOW_PAT_OFF_MATCH(x)     ((x & 0xf) << 8)
2246

2247
#define    AR_WOW_PATTERN_MATCH_REG_2  AR_MAC_PCU_OFFSET(WOW2_EXACT)
2248
#define    AR_WOW_PATTERN_OFF1_REG     AR_MAC_PCU_OFFSET(PCU_WOW4) /* Pattern bytes 0 -> 3 */
2249
#define    AR_WOW_PATTERN_OFF2_REG     AR_MAC_PCU_OFFSET(PCU_WOW5) /* Pattern bytes 4 -> 7 */
2250
#define    AR_WOW_PATTERN_OFF3_REG     AR_MAC_PCU_OFFSET(PCU_WOW6) /* Pattern bytes 8 -> 11 */
2251
#define    AR_WOW_PATTERN_OFF4_REG     AR_MAC_PCU_OFFSET(PCU_WOW7) /* Pattern bytes 12 -> 15 */
2252

2253
/* start address of the frame in RxBUF */
2254
#define    AR_WOW_RXBUF_START_ADDR     AR_MAC_PCU_OFFSET(MAC_PCU_WOW6)
2255

2256
/* Pattern detect and enable bits */
2257
#define    AR_WOW_PATTERN_DETECT_ENABLE   AR_MAC_PCU_OFFSET(MAC_PCU_WOW4)
2258

2259
/* Rx Abort Enable */
2260
#define    AR_WOW_RX_ABORT_ENABLE      AR_MAC_PCU_OFFSET(MAC_PCU_WOW5)
2261

2262
/* PHY error counter 1, 2, and 3 mask continued */
2263
#define    AR_PHY_ERR_CNT_MASK_CONT    AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_MASK_CONT)
2264

2265
/* AZIMUTH mode reg can be used for proxySTA */
2266
#define AR_AZIMUTH_MODE                 AR_MAC_PCU_OFFSET(MAC_PCU_AZIMUTH_MODE)
2267
#define AR_AZIMUTH_KEY_SEARCH_AD1       0x00000002
2268
#define AR_AZIMUTH_CTS_MATCH_TX_AD2     0x00000040
2269
#define AR_AZIMUTH_BA_USES_AD1          0x00000080
2270
#define AR_AZIMUTH_FILTER_PASS_HOLD     0x00000200
2271

2272
/* Length of Pattern Match for Pattern */
2273
#define    AR_WOW_LENGTH1_REG          AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH1)
2274
#define    AR_WOW_LENGTH2_REG          AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH2)
2275
#define    AR_WOW_LENGTH3_REG          AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH3)
2276
#define    AR_WOW_LENGTH4_REG          AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH4)
2277

2278
#define    AR_LOC_CTL_REG              AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_CONTROL)
2279
#define    AR_LOC_TIMER_REG            AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_TIMER)
2280
#define    AR_LOC_CTL_REG_FS           0x1
2281

2282
/* Register to enable pattern match for less than 256 bytes packets */
2283
#define AR_WOW_PATTERN_MATCH_LT_256B_REG    AR_MAC_PCU_OFFSET(WOW_PATTERN_MATCH_LESS_THAN_256_BYTES)
2284

2285

2286
#define    AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | AR_WOW_MAGIC_PAT_FOUND | \
2287
                               AR_WOW_KEEP_ALIVE_FAIL | AR_WOW_BEACON_FAIL))
2288
#define AR_WOW_CLEAR_EVENTS(x)     (x & ~(AR_WOW_PATTERN_EN(0xff) | \
2289
       AR_WOW_MAGIC_EN | AR_WOW_MAC_INTR_EN | AR_WOW_BEACON_FAIL | \
2290
       AR_WOW_KEEP_ALIVE_FAIL))
2291

2292

2293
/*
2294
 * Keep it long for Beacon workaround - ensures no AH_FALSE alarm
2295
 */
2296
#define AR_WOW_BMISSTHRESHOLD       0x20
2297

2298

2299
/* WoW - Transmit buffer for keep alive frames */
2300
#define AR_WOW_TRANSMIT_BUFFER      AR_MAC_PCU_OFFSET(MAC_PCU_BUF)
2301
#define AR_WOW_TXBUF(_i)    (AR_WOW_TRANSMIT_BUFFER + ((_i)<<2))
2302

2303
#define AR_WOW_KA_DESC_WORD2        AR_WOW_TXBUF(0)
2304
#define AR_WOW_KA_DESC_WORD3        AR_WOW_TXBUF(1)
2305
#define AR_WOW_KA_DESC_WORD4        AR_WOW_TXBUF(2)
2306
#define AR_WOW_KA_DESC_WORD5        AR_WOW_TXBUF(3)
2307
#define AR_WOW_KA_DESC_WORD6        AR_WOW_TXBUF(4)
2308
#define AR_WOW_KA_DESC_WORD7        AR_WOW_TXBUF(5)
2309
#define AR_WOW_KA_DESC_WORD8        AR_WOW_TXBUF(6)
2310
#define AR_WOW_KA_DESC_WORD9        AR_WOW_TXBUF(7)
2311
#define AR_WOW_KA_DESC_WORD10       AR_WOW_TXBUF(8)
2312
#define AR_WOW_KA_DESC_WORD11       AR_WOW_TXBUF(9)
2313
#define AR_WOW_KA_DESC_WORD12       AR_WOW_TXBUF(10)
2314
#define AR_WOW_KA_DESC_WORD13       AR_WOW_TXBUF(11)
2315

2316
/* KA_DATA_WORD = 6 words. Depending on the number of
2317
 * descriptor words, it can start at AR_WOW_TXBUF(12)
2318
 * or AR_WOW_TXBUF(13) */
2319

2320
#define AR_WOW_OFFLOAD_GTK_DATA_START       AR_WOW_TXBUF(19)
2321

2322
#define AR_WOW_KA_DATA_WORD_END_JUPITER     AR_WOW_TXBUF(60)
2323

2324
#define AR_WOW_SW_NULL_PARAMETER            AR_WOW_TXBUF(61)
2325
#define AR_WOW_SW_NULL_LONG_PERIOD_MASK     0x0000FFFF
2326
#define AR_WOW_SW_NULL_LONG_PERIOD_MASK_S   0
2327
#define AR_WOW_SW_NULL_SHORT_PERIOD_MASK    0xFFFF0000
2328
#define AR_WOW_SW_NULL_SHORT_PERIOD_MASK_S  16
2329

2330
#define AR_WOW_OFFLOAD_COMMAND_JUPITER      AR_WOW_TXBUF(62)
2331
#define AR_WOW_OFFLOAD_ENA_GTK              0x80000000
2332
#define AR_WOW_OFFLOAD_ENA_ACER_MAGIC       0x40000000
2333
#define AR_WOW_OFFLOAD_ENA_STD_MAGIC        0x20000000
2334
#define AR_WOW_OFFLOAD_ENA_SWKA             0x10000000
2335
#define AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD      0x08000000
2336
#define AR_WOW_OFFLOAD_ENA_NS_OFFLOAD       0x04000000
2337
#define AR_WOW_OFFLOAD_ENA_4WAY_WAKE        0x02000000
2338
#define AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE   0x01000000
2339
#define AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE     0x00800000
2340
#define AR_WOW_OFFLOAD_ENA_BT_SLEEP         0x00080000
2341
#define AR_WOW_OFFLOAD_ENA_SW_NULL          0x00040000
2342
#define AR_WOW_OFFLOAD_ENA_HWKA_FAIL        0x00020000
2343
#define AR_WOW_OFFLOAD_ENA_DEVID_SWAR       0x00010000
2344

2345
#define AR_WOW_OFFLOAD_STATUS_JUPITER       AR_WOW_TXBUF(63)
2346

2347
/* WoW Transmit Buffer for patterns */
2348
#define AR_WOW_TB_PATTERN0          AR_WOW_TXBUF(64)
2349
#define AR_WOW_TB_PATTERN1          AR_WOW_TXBUF(128)
2350
#define AR_WOW_TB_PATTERN2          AR_WOW_TXBUF(192)
2351
#define AR_WOW_TB_PATTERN3          AR_WOW_TXBUF(256)
2352
#define AR_WOW_TB_PATTERN4          AR_WOW_TXBUF(320)
2353
#define AR_WOW_TB_PATTERN5          AR_WOW_TXBUF(384)
2354
#define AR_WOW_TB_PATTERN6          AR_WOW_TXBUF(448)
2355
#define AR_WOW_TB_PATTERN7          AR_WOW_TXBUF(512)
2356
#define AR_WOW_TB_MASK0             AR_WOW_TXBUF(768)
2357
#define AR_WOW_TB_MASK1             AR_WOW_TXBUF(776)
2358
#define AR_WOW_TB_MASK2             AR_WOW_TXBUF(784)
2359
#define AR_WOW_TB_MASK3             AR_WOW_TXBUF(792)
2360
#define AR_WOW_TB_MASK4             AR_WOW_TXBUF(800)
2361
#define AR_WOW_TB_MASK5             AR_WOW_TXBUF(808)
2362
#define AR_WOW_TB_MASK6             AR_WOW_TXBUF(816)
2363
#define AR_WOW_TB_MASK7             AR_WOW_TXBUF(824)
2364

2365

2366
#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START   AR_WOW_TXBUF(825)
2367
#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START_JUPITER   AR_WOW_TXBUF(832)
2368
#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_WORDS   4
2369

2370
#define AR_WOW_OFFLOAD_GTK_DATA_START_JUPITER       AR_WOW_TXBUF(836)
2371
#define AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER       20
2372

2373
#define AR_WOW_OFFLOAD_ACER_MAGIC_START         AR_WOW_TXBUF(856)
2374
#define AR_WOW_OFFLOAD_ACER_MAGIC_WORDS         2
2375

2376
#define AR_WOW_OFFLOAD_ACER_KA0_START           AR_WOW_TXBUF(858)
2377
#define AR_WOW_OFFLOAD_ACER_KA0_PERIOD_MS       AR_WOW_TXBUF(858)
2378
#define AR_WOW_OFFLOAD_ACER_KA0_SIZE            AR_WOW_TXBUF(859)
2379
#define AR_WOW_OFFLOAD_ACER_KA0_DATA            AR_WOW_TXBUF(860)
2380
#define AR_WOW_OFFLOAD_ACER_KA0_DATA_WORDS      20
2381
#define AR_WOW_OFFLOAD_ACER_KA0_WORDS           22
2382

2383
#define AR_WOW_OFFLOAD_ACER_KA1_START           AR_WOW_TXBUF(880)
2384
#define AR_WOW_OFFLOAD_ACER_KA1_PERIOD_MS       AR_WOW_TXBUF(880)
2385
#define AR_WOW_OFFLOAD_ACER_KA1_SIZE            AR_WOW_TXBUF(881)
2386
#define AR_WOW_OFFLOAD_ACER_KA1_DATA            AR_WOW_TXBUF(882)
2387
#define AR_WOW_OFFLOAD_ACER_KA1_DATA_WORDS      20
2388
#define AR_WOW_OFFLOAD_ACER_KA1_WORDS           22
2389

2390
#define AR_WOW_OFFLOAD_ARP0_START               AR_WOW_TXBUF(902)
2391
#define AR_WOW_OFFLOAD_ARP0_VALID               AR_WOW_TXBUF(902)
2392
#define AR_WOW_OFFLOAD_ARP0_RMT_IP              AR_WOW_TXBUF(903)
2393
#define AR_WOW_OFFLOAD_ARP0_HOST_IP             AR_WOW_TXBUF(904)
2394
#define AR_WOW_OFFLOAD_ARP0_MAC_L               AR_WOW_TXBUF(905)
2395
#define AR_WOW_OFFLOAD_ARP0_MAC_H               AR_WOW_TXBUF(906)
2396
#define AR_WOW_OFFLOAD_ARP0_WORDS               5
2397

2398
#define AR_WOW_OFFLOAD_ARP1_START               AR_WOW_TXBUF(907)
2399
#define AR_WOW_OFFLOAD_ARP1_VALID               AR_WOW_TXBUF(907)
2400
#define AR_WOW_OFFLOAD_ARP1_RMT_IP              AR_WOW_TXBUF(908)
2401
#define AR_WOW_OFFLOAD_ARP1_HOST_IP             AR_WOW_TXBUF(909)
2402
#define AR_WOW_OFFLOAD_ARP1_MAC_L               AR_WOW_TXBUF(910)
2403
#define AR_WOW_OFFLOAD_ARP1_MAC_H               AR_WOW_TXBUF(911)
2404
#define AR_WOW_OFFLOAD_ARP1_WORDS               5
2405

2406
#define AR_WOW_OFFLOAD_NS0_START                AR_WOW_TXBUF(912)
2407
#define AR_WOW_OFFLOAD_NS0_VALID                AR_WOW_TXBUF(912)
2408
#define AR_WOW_OFFLOAD_NS0_RMT_IPV6             AR_WOW_TXBUF(913)
2409
#define AR_WOW_OFFLOAD_NS0_SOLICIT_IPV6         AR_WOW_TXBUF(917)
2410
#define AR_WOW_OFFLOAD_NS0_MAC_L                AR_WOW_TXBUF(921)
2411
#define AR_WOW_OFFLOAD_NS0_MAC_H                AR_WOW_TXBUF(922)
2412
#define AR_WOW_OFFLOAD_NS0_TGT0_IPV6            AR_WOW_TXBUF(923)
2413
#define AR_WOW_OFFLOAD_NS0_TGT1_IPV6            AR_WOW_TXBUF(927)
2414
#define AR_WOW_OFFLOAD_NS0_WORDS                19
2415

2416
#define AR_WOW_OFFLOAD_NS1_START                AR_WOW_TXBUF(931)
2417
#define AR_WOW_OFFLOAD_NS1_VALID                AR_WOW_TXBUF(931)
2418
#define AR_WOW_OFFLOAD_NS1_RMT_IPV6             AR_WOW_TXBUF(932)
2419
#define AR_WOW_OFFLOAD_NS1_SOLICIT_IPV6         AR_WOW_TXBUF(936)
2420
#define AR_WOW_OFFLOAD_NS1_MAC_L                AR_WOW_TXBUF(940)
2421
#define AR_WOW_OFFLOAD_NS1_MAC_H                AR_WOW_TXBUF(941)
2422
#define AR_WOW_OFFLOAD_NS1_TGT0_IPV6            AR_WOW_TXBUF(942)
2423
#define AR_WOW_OFFLOAD_NS1_TGT1_IPV6            AR_WOW_TXBUF(946)
2424
#define AR_WOW_OFFLOAD_NS1_WORDS                19
2425

2426
#define AR_WOW_OFFLOAD_WLAN_REGSET_START        AR_WOW_TXBUF(950)
2427
#define AR_WOW_OFFLOAD_WLAN_REGSET_NUM          AR_WOW_TXBUF(950)
2428
#define AR_WOW_OFFLOAD_WLAN_REGSET_REGVAL       AR_WOW_TXBUF(951)
2429
#define AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR     32
2430
#define AR_WOW_OFFLOAD_WLAN_REGSET_WORDS        65  //(1 + AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR * 2)
2431

2432
/* Currently Pattern 0-7 are supported - so bit 0-7 are set */
2433
#define AR_WOW_PATTERN_SUPPORTED    0xFF
2434
#define AR_WOW_LENGTH_MAX           0xFF
2435
#define AR_WOW_LENGTH1_SHIFT(_i)    ((0x3 - ((_i) & 0x3)) << 0x3)
2436
#define AR_WOW_LENGTH1_MASK(_i)     (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH1_SHIFT(_i))
2437
#define AR_WOW_LENGTH2_SHIFT(_i)    ((0x7 - ((_i) & 0x7)) << 0x3)
2438
#define AR_WOW_LENGTH2_MASK(_i)     (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH2_SHIFT(_i))
2439

2440
/*
2441
 * MAC Direct Connect registers
2442
 *
2443
 * Added to support dual BSSID/TSF which are needed in the application
2444
 * of Mesh networking or Direct Connect.
2445
 */
2446

2447
/*
2448
 * Note that the only function added with this BSSID2 is to receive
2449
 * multi/broadcast from BSSID2 as well
2450
 */
2451
/* MAC BSSID low 32 bits */
2452
#define AR_BSS2_ID0           AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32)
2453
/* MAC BSSID upper 16 bits / AID */
2454
#define AR_BSS2_ID1           AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16)
2455

2456
/*
2457
 * Secondary TSF support added for dual BSSID/TSF
2458
 */
2459
/* MAC local clock lower 32 bits */
2460
#define AR_TSF2_L32          AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32)
2461
/* MAC local clock upper 32 bits */
2462
#define AR_TSF2_U32          AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32)
2463

2464
/* MAC Direct Connect Control */
2465
#define AR_DIRECT_CONNECT    AR_MAC_PCU_OFFSET(MAC_PCU_DIRECT_CONNECT)
2466
#define AR_DC_AP_STA_EN      0x00000001
2467
#define AR_DC_AP_STA_EN_S    0
2468

2469
/*
2470
 * tx_bf Register
2471
 */
2472
#define AR_SVD_OFFSET(_x)   offsetof(struct svd_reg, _x)
2473

2474
#define AR_TXBF_DBG         AR_SVD_OFFSET(TXBF_DBG)
2475

2476
#define AR_TXBF             AR_SVD_OFFSET(TXBF)
2477
#define AR_TXBF_CB_TX       0x00000003
2478
#define AR_TXBF_CB_TX_S     0
2479
#define AR_TXBF_PSI_1_PHI_3         0
2480
#define AR_TXBF_PSI_2_PHI_4         1        
2481
#define AR_TXBF_PSI_3_PHI_5         2
2482
#define AR_TXBF_PSI_4_PHI_6         3
2483

2484
#define AR_TXBF_NB_TX       0x0000000C
2485
#define AR_TXBF_NB_TX_S     2
2486
#define AR_TXBF_NUMBEROFBIT_4       0
2487
#define AR_TXBF_NUMBEROFBIT_2       1
2488
#define AR_TXBF_NUMBEROFBIT_6       2
2489
#define AR_TXBF_NUMBEROFBIT_8       3
2490

2491
#define AR_TXBF_NG_RPT_TX   0x00000030
2492
#define AR_TXBF_NG_RPT_TX_S 4
2493
#define AR_TXBF_No_GROUP            0
2494
#define AR_TXBF_TWO_GROUP           1
2495
#define AR_TXBF_FOUR_GROUP          2
2496

2497
#define AR_TXBF_NG_CVCACHE  0x000000C0
2498
#define AR_TXBF_NG_CVCACHE_S  6
2499
#define AR_TXBF_FOUR_CLIENTS        0
2500
#define AR_TXBF_EIGHT_CLIENTS       1
2501
#define AR_TXBF_SIXTEEN_CLIENTS     2
2502

2503
#define AR_TXBF_TXCV_BFWEIGHT_METHOD 0x00000600
2504
#define AR_TXBF_TXCV_BFWEIGHT_METHOD_S 9
2505
#define AR_TXBF_NO_WEIGHTING        0
2506
#define AR_TXBF_MAX_POWER           1
2507
#define AR_TXBF_KEEP_RATIO          2
2508

2509
#define AR_TXBF_RLR_EN        0x00000800
2510
#define AR_TXBF_RC_20_U_DONE  0x00001000
2511
#define AR_TXBF_RC_20_L_DONE  0x00002000
2512
#define AR_TXBF_RC_40_DONE    0x00004000
2513
#define AR_TXBF_FORCE_UPDATE_V2BB   0x00008000
2514

2515
#define AR_TXBF_TIMER             AR_SVD_OFFSET(TXBF_TIMER)
2516
#define AR_TXBF_TIMER_TIMEOUT     0x000000FF
2517
#define AR_TXBF_TIMER_TIMEOUT_S   0
2518
#define AR_TXBF_TIMER_ATIMEOU     0x0000FF00
2519
#define AR_TXBF_TIMER_ATIMEOUT_S  8
2520

2521
/* for SVD cache update */
2522
#define AR_TXBF_SW          AR_SVD_OFFSET(TXBF_SW)
2523
#define AR_LRU_ACK          0x00000001
2524
#define AR_LRU_ADDR         0x000003FE
2525
#define AR_LRU_ADDR_S       1
2526
#define AR_LRU_EN           0x00000800
2527
#define AR_LRU_EN_S         11
2528
#define AR_DEST_IDX         0x0007f000
2529
#define AR_DEST_IDX_S       12
2530
#define AR_LRU_WR_ACK       0x00080000
2531
#define AR_LRU_WR_ACK_S     19
2532
#define AR_LRU_RD_ACK       0x00100000
2533
#define AR_LRU_RD_ACK_S     20
2534

2535
#define AR_RC0_0            AR_SVD_OFFSET(RC0)
2536
#define AR_RC0(_idx)        (AR_RC0_0+(_idx))
2537
#define AR_RC1_0            AR_SVD_OFFSET(RC1)
2538
#define AR_RC1(_idx)        (AR_RC1_0+(_idx))
2539

2540
#define AR_CVCACHE_0        AR_SVD_OFFSET(CVCACHE)
2541
#define AR_CVCACHE(_idx)    (AR_CVCACHE_0+(_idx))
2542
/* for CV CACHE Header */
2543
#define AR_CVCACHE_Ng_IDX   0x0000C000
2544
#define AR_CVCACHE_Ng_IDX_S 14
2545
#define AR_CVCACHE_BW40     0x00010000
2546
#define AR_CVCACHE_BW40_S   16
2547
#define AR_CVCACHE_IMPLICIT 0x00020000
2548
#define AR_CVCACHE_IMPLICIT_S   17
2549
#define AR_CVCACHE_DEST_IDX 0x01FC0000
2550
#define AR_CVCACHE_DEST_IDX_S   18
2551
#define AR_CVCACHE_Nc_IDX   0x06000000
2552
#define AR_CVCACHE_Nc_IDX_S 25
2553
#define AR_CVCACHE_Nr_IDX   0x18000000
2554
#define AR_CVCACHE_Nr_IDX_S 27
2555
#define AR_CVCACHE_EXPIRED  0x20000000
2556
#define AR_CVCACHE_EXPIRED_S    29
2557
#define AR_CVCACHE_WRITE    0x80000000
2558
/* for CV cache data*/
2559
#define AR_CVCACHE_RD_EN    0x40000000
2560
#define AR_CVCACHE_DATA     0x3fffffff
2561
/*
2562
 * ANT DIV setting
2563
 */
2564
#define ANT_DIV_CONTROL_ALL (0x7e000000)
2565
#define ANT_DIV_CONTROL_ALL_S (25)
2566
#define ANT_DIV_ENABLE (0x1000000)
2567
#define ANT_DIV_ENABLE_S (24)
2568
#define FAST_DIV_ENABLE (0x2000)
2569
#define FAST_DIV_ENABLE_S (13)
2570

2571
/* Global register */
2572
#define AR_GLB_REG_OFFSET(_x)     offsetof(struct wlan_bt_glb_reg_pcie, _x)
2573

2574
#define AR_MBOX_CTRL_STATUS                 AR_GLB_REG_OFFSET(GLB_MBOX_CONTROL_STATUS)
2575
#define AR_MBOX_INT_EMB_CPU                 0x0001
2576
#define AR_MBOX_INT_WLAN                    0x0002
2577
#define AR_MBOX_RESET                       0x0004
2578
#define AR_MBOX_RAM_REQ_MASK                0x0018
2579
#define AR_MBOX_RAM_REQ_NO_RAM              0x0000
2580
#define AR_MBOX_RAM_REQ_USB                 0x0008 
2581
#define AR_MBOX_RAM_REQ_WLAN_BUF            0x0010
2582
#define AR_MBOX_RAM_REQ_PATCH_REAPPY        0x0018
2583
#define AR_MBOX_RAM_CONF                    0x0020
2584
#define AR_MBOX_WLAN_BUF                    0x0040
2585
#define AR_MBOX_WOW_REQ                     0x0080
2586
#define AR_MBOX_WOW_CONF                    0x0100
2587
#define AR_MBOX_WOW_ERROR_MASK              0x1e00
2588
#define AR_MBOX_WOW_ERROR_NONE              0x0000
2589
#define AR_MBOX_WOW_ERROR_INVALID_MSG       0x0200
2590
#define AR_MBOX_WOW_ERROR_MALFORMED_MSG     0x0400
2591
#define AR_MBOX_WOW_ERROR_INVALID_RAM_IMAGE 0x0600
2592

2593
#define AR_WLAN_WOW_STATUS                 AR_GLB_REG_OFFSET(GLB_WLAN_WOW_STATUS)
2594

2595
#define AR_WLAN_WOW_ENABLE                 AR_GLB_REG_OFFSET(GLB_WLAN_WOW_ENABLE)
2596

2597
#define AR_EMB_CPU_WOW_STATUS               AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_STATUS)
2598
#define AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL 0x1
2599
#define AR_EMB_CPU_WOW_STATUS_BEACON_MISS     0x2
2600
#define AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH   0x4
2601
#define AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN   0x8
2602
  
2603
#define AR_EMB_CPU_WOW_ENABLE               AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_ENABLE)
2604
#define AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL 0x1
2605
#define AR_EMB_CPU_WOW_ENABLE_BEACON_MISS     0x2
2606
#define AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH   0x4
2607
#define AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN   0x8
2608

2609
#define AR_SW_WOW_CONTROL                   AR_GLB_REG_OFFSET(GLB_SW_WOW_CONTROL)
2610
#define AR_SW_WOW_ENABLE                    0x1
2611
#define AR_SWITCH_TO_REFCLK                 0x2
2612
#define AR_RESET_CONTROL                    0x4
2613
#define AR_RESET_VALUE_MASK                 0x8
2614
#define AR_HW_WOW_DISABLE                   0x10
2615
#define AR_CLR_MAC_INTERRUPT                0x20
2616
#define AR_CLR_KA_INTERRUPT                 0x40
2617

2618
/*
2619
 * WLAN coex registers
2620
 */
2621
#define AR_WLAN_COEX_OFFSET(_x)   offsetof(struct wlan_coex_reg, _x)
2622

2623
#define AR_MCI_COMMAND0                 AR_WLAN_COEX_OFFSET(MCI_COMMAND0)
2624
#define AR_MCI_COMMAND0_HEADER          0xFF
2625
#define AR_MCI_COMMAND0_HEADER_S        0
2626
#define AR_MCI_COMMAND0_LEN             0x1f00
2627
#define AR_MCI_COMMAND0_LEN_S           8
2628
#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
2629
#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13
2630

2631
#define AR_MCI_COMMAND1                 AR_WLAN_COEX_OFFSET(MCI_COMMAND1)
2632

2633
#define AR_MCI_COMMAND2                 AR_WLAN_COEX_OFFSET(MCI_COMMAND2)
2634
#define AR_MCI_COMMAND2_RESET_TX        0x01
2635
#define AR_MCI_COMMAND2_RESET_TX_S      0
2636
#define AR_MCI_COMMAND2_RESET_RX        0x02
2637
#define AR_MCI_COMMAND2_RESET_RX_S      1
2638
#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES     0x3FC
2639
#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S   2
2640
#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP        0x400
2641
#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S      10
2642

2643
#define AR_MCI_RX_CTRL                  AR_WLAN_COEX_OFFSET(MCI_RX_CTRL)
2644

2645
#define AR_MCI_TX_CTRL                  AR_WLAN_COEX_OFFSET(MCI_TX_CTRL)
2646
/* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */
2647
#define AR_MCI_TX_CTRL_CLK_DIV          0x03
2648
#define AR_MCI_TX_CTRL_CLK_DIV_S        0
2649
#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04
2650
#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2
2651
#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8
2652
#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3
2653
#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM  0xF000000
2654
#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24
2655

2656
#define AR_MCI_MSG_ATTRIBUTES_TABLE     AR_WLAN_COEX_OFFSET(MCI_MSG_ATTRIBUTES_TABLE)
2657
#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF
2658
#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0
2659
#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000
2660
#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16
2661

2662
#define AR_MCI_SCHD_TABLE_0             AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_0)
2663
#define AR_MCI_SCHD_TABLE_1             AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_1)
2664
#define AR_MCI_GPM_0                    AR_WLAN_COEX_OFFSET(MCI_GPM_0)
2665
#define AR_MCI_GPM_1                    AR_WLAN_COEX_OFFSET(MCI_GPM_1)
2666
#define AR_MCI_GPM_WRITE_PTR            0xFFFF0000
2667
#define AR_MCI_GPM_WRITE_PTR_S          16
2668
#define AR_MCI_GPM_BUF_LEN              0x0000FFFF
2669
#define AR_MCI_GPM_BUF_LEN_S            0
2670

2671
#define AR_MCI_INTERRUPT_RAW            AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RAW)
2672
#define AR_MCI_INTERRUPT_EN             AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_EN)
2673
#define AR_MCI_INTERRUPT_SW_MSG_DONE            0x00000001
2674
#define AR_MCI_INTERRUPT_SW_MSG_DONE_S          0
2675
#define AR_MCI_INTERRUPT_CPU_INT_MSG            0x00000002
2676
#define AR_MCI_INTERRUPT_CPU_INT_MSG_S          1
2677
#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL          0x00000004
2678
#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S        2
2679
#define AR_MCI_INTERRUPT_RX_INVALID_HDR         0x00000008
2680
#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S       3
2681
#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL         0x00000010
2682
#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S       4
2683
#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL         0x00000020
2684
#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S       5
2685
#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL         0x00000080
2686
#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S       7
2687
#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL         0x00000100
2688
#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S       8
2689
#define AR_MCI_INTERRUPT_RX_MSG                 0x00000200
2690
#define AR_MCI_INTERRUPT_RX_MSG_S               9
2691
#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE    0x00000400
2692
#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S  10
2693
#define AR_MCI_INTERRUPT_BT_PRI                 0x07fff800
2694
#define AR_MCI_INTERRUPT_BT_PRI_S               11
2695
#define AR_MCI_INTERRUPT_BT_PRI_THRESH          0x08000000
2696
#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S        27
2697
#define AR_MCI_INTERRUPT_BT_FREQ                0x10000000
2698
#define AR_MCI_INTERRUPT_BT_FREQ_S              28
2699
#define AR_MCI_INTERRUPT_BT_STOMP               0x20000000
2700
#define AR_MCI_INTERRUPT_BT_STOMP_S             29
2701
#define AR_MCI_INTERRUPT_BB_AIC_IRQ             0x40000000
2702
#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S           30
2703
#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT      0x80000000
2704
#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S    31
2705

2706
#define AR_MCI_INTERRUPT_MSG_FAIL_MASK ( AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
2707
                                         AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
2708
                                         AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
2709
                                         AR_MCI_INTERRUPT_TX_SW_MSG_FAIL )
2710

2711
#define AR_MCI_INTERRUPT_DEFAULT              ( AR_MCI_INTERRUPT_SW_MSG_DONE |          \
2712
                                                AR_MCI_INTERRUPT_RX_INVALID_HDR |       \
2713
                                                AR_MCI_INTERRUPT_RX_HW_MSG_FAIL |       \
2714
                                                AR_MCI_INTERRUPT_RX_SW_MSG_FAIL |       \
2715
                                                AR_MCI_INTERRUPT_TX_HW_MSG_FAIL |       \
2716
                                                AR_MCI_INTERRUPT_TX_SW_MSG_FAIL |       \
2717
                                                AR_MCI_INTERRUPT_RX_MSG |               \
2718
                                                AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE |  \
2719
                                                AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT )
2720

2721
#define AR_MCI_REMOTE_CPU_INT           AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT)
2722
#define AR_MCI_REMOTE_CPU_INT_EN        AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT_EN)
2723

2724
#define AR_MCI_INTERRUPT_RX_MSG_RAW     AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_RAW)
2725
#define AR_MCI_INTERRUPT_RX_MSG_EN      AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_EN)
2726
#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET    0x00000001
2727
#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S  0
2728
#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL     0x00000002
2729
#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S   1
2730
#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK       0x00000004
2731
#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S     2
2732
#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO       0x00000008
2733
#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S     3
2734
#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST        0x00000010
2735
#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S      4
2736
#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO       0x00000020
2737
#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S     5
2738
#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT         0x00000040
2739
#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S       6
2740
#define AR_MCI_INTERRUPT_RX_MSG_GPM             0x00000100
2741
#define AR_MCI_INTERRUPT_RX_MSG_GPM_S           8
2742
#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO        0x00000200
2743
#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S      9
2744
#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING    0x00000400
2745
#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S  10
2746
#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING      0x00000800
2747
#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S    11
2748
#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE        0x00001000
2749
#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S      12
2750
#ifdef AH_DEBUG
2751
#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT       ( AR_MCI_INTERRUPT_RX_MSG_GPM           | \
2752
                                                AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET  | \
2753
                                                AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING    | \
2754
                                                AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING  | \
2755
                                                AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO     | \
2756
                                                AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL   | \
2757
                                                AR_MCI_INTERRUPT_RX_MSG_LNA_INFO      | \
2758
                                                AR_MCI_INTERRUPT_RX_MSG_CONT_NACK     | \
2759
                                                AR_MCI_INTERRUPT_RX_MSG_CONT_INFO     | \
2760
                                                AR_MCI_INTERRUPT_RX_MSG_CONT_RST      | \
2761
                                                AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE )
2762
#else
2763
#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT       ( AR_MCI_INTERRUPT_RX_MSG_GPM           | \
2764
                                                AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET  | \
2765
                                                AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING    | \
2766
                                                AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING  | \
2767
                                                AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE )
2768
#endif
2769
#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK       ( AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO     | \
2770
                                                AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL   | \
2771
                                                AR_MCI_INTERRUPT_RX_MSG_LNA_INFO      | \
2772
                                                AR_MCI_INTERRUPT_RX_MSG_CONT_NACK     | \
2773
                                                AR_MCI_INTERRUPT_RX_MSG_CONT_INFO     | \
2774
                                                AR_MCI_INTERRUPT_RX_MSG_CONT_RST )
2775

2776
#define AR_MCI_CPU_INT                  AR_WLAN_COEX_OFFSET(MCI_CPU_INT)
2777

2778
#define AR_MCI_RX_STATUS                AR_WLAN_COEX_OFFSET(MCI_RX_STATUS)
2779
#define AR_MCI_RX_LAST_SCHD_MSG_INDEX   0x00000F00
2780
#define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8
2781
#define AR_MCI_RX_REMOTE_SLEEP          0x00001000
2782
#define AR_MCI_RX_REMOTE_SLEEP_S        12
2783
#define AR_MCI_RX_MCI_CLK_REQ           0x00002000
2784
#define AR_MCI_RX_MCI_CLK_REQ_S         13
2785

2786
#define AR_MCI_CONT_STATUS              AR_WLAN_COEX_OFFSET(MCI_CONT_STATUS)
2787
#define AR_MCI_CONT_RSSI_POWER          0x000000FF
2788
#define AR_MCI_CONT_RSSI_POWER_S        0
2789
#define AR_MCI_CONT_RRIORITY            0x0000FF00
2790
#define AR_MCI_CONT_RRIORITY_S          8
2791
#define AR_MCI_CONT_TXRX                0x00010000
2792
#define AR_MCI_CONT_TXRX_S              16
2793

2794
#define AR_MCI_BT_PRI0                  AR_WLAN_COEX_OFFSET(MCI_BT_PRI0) 
2795
#define AR_MCI_BT_PRI1                  AR_WLAN_COEX_OFFSET(MCI_BT_PRI1) 
2796
#define AR_MCI_BT_PRI2                  AR_WLAN_COEX_OFFSET(MCI_BT_PRI2) 
2797
#define AR_MCI_BT_PRI3                  AR_WLAN_COEX_OFFSET(MCI_BT_PRI3) 
2798
#define AR_MCI_BT_PRI                   AR_WLAN_COEX_OFFSET(MCI_BT_PRI) 
2799
#define AR_MCI_WL_FREQ0                 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ0) 
2800
#define AR_MCI_WL_FREQ1                 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ1) 
2801
#define AR_MCI_WL_FREQ2                 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ2) 
2802
#define AR_MCI_GAIN                     AR_WLAN_COEX_OFFSET(MCI_GAIN) 
2803
#define AR_MCI_WBTIMER1                 AR_WLAN_COEX_OFFSET(MCI_WBTIMER1) 
2804
#define AR_MCI_WBTIMER2                 AR_WLAN_COEX_OFFSET(MCI_WBTIMER2) 
2805
#define AR_MCI_WBTIMER3                 AR_WLAN_COEX_OFFSET(MCI_WBTIMER3) 
2806
#define AR_MCI_WBTIMER4                 AR_WLAN_COEX_OFFSET(MCI_WBTIMER4) 
2807
#define AR_MCI_MAXGAIN                  AR_WLAN_COEX_OFFSET(MCI_MAXGAIN) 
2808
#define AR_MCI_HW_SCHD_TBL_CTL          AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_CTL) 
2809
#define AR_MCI_HW_SCHD_TBL_D0           AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D0) 
2810
#define AR_MCI_HW_SCHD_TBL_D1           AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D1) 
2811
#define AR_MCI_HW_SCHD_TBL_D2           AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D2) 
2812
#define AR_MCI_HW_SCHD_TBL_D3           AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D3) 
2813
#define AR_MCI_TX_PAYLOAD0              AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD0) 
2814
#define AR_MCI_TX_PAYLOAD1              AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD1) 
2815
#define AR_MCI_TX_PAYLOAD2              AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD2) 
2816
#define AR_MCI_TX_PAYLOAD3              AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD3) 
2817
#define AR_BTCOEX_WBTIMER               AR_WLAN_COEX_OFFSET(BTCOEX_WBTIMER) 
2818

2819
#define AR_BTCOEX_CTRL                  AR_WLAN_COEX_OFFSET(BTCOEX_CTRL)
2820
#define AR_BTCOEX_CTRL_JUPITER_MODE     0x00000001
2821
#define AR_BTCOEX_CTRL_JUPITER_MODE_S   0
2822
#define AR_BTCOEX_CTRL_WBTIMER_EN       0x00000002
2823
#define AR_BTCOEX_CTRL_WBTIMER_EN_S     1
2824
#define AR_BTCOEX_CTRL_MCI_MODE_EN      0x00000004
2825
#define AR_BTCOEX_CTRL_MCI_MODE_EN_S    2
2826
#define AR_BTCOEX_CTRL_LNA_SHARED       0x00000008
2827
#define AR_BTCOEX_CTRL_LNA_SHARED_S     3
2828
#define AR_BTCOEX_CTRL_PA_SHARED        0x00000010
2829
#define AR_BTCOEX_CTRL_PA_SHARED_S      4
2830
#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020
2831
#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5
2832
#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN    0x00000040
2833
#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S  6
2834
#define AR_BTCOEX_CTRL_NUM_ANTENNAS     0x00000180
2835
#define AR_BTCOEX_CTRL_NUM_ANTENNAS_S   7
2836
#define AR_BTCOEX_CTRL_RX_CHAIN_MASK    0x00000E00
2837
#define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S  9
2838
#define AR_BTCOEX_CTRL_AGGR_THRESH      0x00007000
2839
#define AR_BTCOEX_CTRL_AGGR_THRESH_S    12
2840
#define AR_BTCOEX_CTRL_1_CHAIN_BCN      0x00080000
2841
#define AR_BTCOEX_CTRL_1_CHAIN_BCN_S    19
2842
#define AR_BTCOEX_CTRL_1_CHAIN_ACK      0x00100000
2843
#define AR_BTCOEX_CTRL_1_CHAIN_ACK_S    20
2844
#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN   0x1FE00000
2845
#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28
2846
#define AR_BTCOEX_CTRL_REDUCE_TXPWR     0x20000000
2847
#define AR_BTCOEX_CTRL_REDUCE_TXPWR_S   29
2848
#define AR_BTCOEX_CTRL_SPDT_ENABLE_10   0x40000000
2849
#define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30
2850
#define AR_BTCOEX_CTRL_SPDT_POLARITY    0x80000000
2851
#define AR_BTCOEX_CTRL_SPDT_POLARITY_S  31
2852

2853
#define AR_BTCOEX_WL_WEIGHTS0           AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS0) 
2854
#define AR_BTCOEX_WL_WEIGHTS1           AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS1) 
2855
#define AR_BTCOEX_WL_WEIGHTS2           AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS2) 
2856
#define AR_BTCOEX_WL_WEIGHTS3           AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS3) 
2857
#define AR_BTCOEX_MAX_TXPWR(_x)         (AR_WLAN_COEX_OFFSET(BTCOEX_MAX_TXPWR) + ((_x) << 2))
2858
#define AR_BTCOEX_WL_LNA                AR_WLAN_COEX_OFFSET(BTCOEX_WL_LNA) 
2859
#define AR_BTCOEX_WL_LNA_TIMEOUT                        0x003FFFFF
2860
#define AR_BTCOEX_WL_LNA_TIMEOUT_S                      0
2861

2862
#define AR_BTCOEX_RFGAIN_CTRL           AR_WLAN_COEX_OFFSET(BTCOEX_RFGAIN_CTRL) 
2863

2864
#define AR_BTCOEX_CTRL2                 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL2) 
2865
#define AR_BTCOEX_CTRL2_TXPWR_THRESH    0x0007F800
2866
#define AR_BTCOEX_CTRL2_TXPWR_THRESH_S  11
2867
#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK   0x00380000
2868
#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19
2869
#define AR_BTCOEX_CTRL2_RX_DEWEIGHT     0x00400000
2870
#define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S   22
2871
#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL    0x00800000
2872
#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S  23
2873
#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL  0x01000000
2874
#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24
2875
#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE     0x02000000
2876
#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S   25
2877

2878
#define AR_BTCOEX_RC                    AR_WLAN_COEX_OFFSET(BTCOEX_RC) 
2879
#define AR_BTCOEX_MAX_RFGAIN(_x)        AR_WLAN_COEX_OFFSET(BTCOEX_MAX_RFGAIN[_x]) 
2880
#define AR_BTCOEX_DBG                   AR_WLAN_COEX_OFFSET(BTCOEX_DBG) 
2881
#define AR_MCI_LAST_HW_MSG_HDR          AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_HDR) 
2882
#define AR_MCI_LAST_HW_MSG_BDY          AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_BDY) 
2883

2884
#define AR_MCI_SCHD_TABLE_2             AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_2)
2885
#define AR_MCI_SCHD_TABLE_2_MEM_BASED   0x00000001
2886
#define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0
2887
#define AR_MCI_SCHD_TABLE_2_HW_BASED    0x00000002
2888
#define AR_MCI_SCHD_TABLE_2_HW_BASED_S  1
2889

2890
#define AR_BTCOEX_CTRL3                 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL3)
2891
#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT   0x00000FFF
2892
#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0
2893

2894
/* QCA9565 */
2895

2896
#define AR_BTCOEX_WL_LNADIV                                0x1a64
2897
#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD               0x00003FFF
2898
#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S             0
2899
#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY           0x00004000
2900
#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S         14
2901
#define AR_BTCOEX_WL_LNADIV_FORCE_ON                       0x00008000
2902
#define AR_BTCOEX_WL_LNADIV_FORCE_ON_S                     15
2903
#define AR_BTCOEX_WL_LNADIV_MODE_OPTION                    0x00030000
2904
#define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S                  16
2905
#define AR_BTCOEX_WL_LNADIV_MODE                           0x007c0000
2906
#define AR_BTCOEX_WL_LNADIV_MODE_S                         18
2907
#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ    0x00800000
2908
#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S  23
2909
#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE       0x01000000
2910
#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S     24
2911
#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT   0x02000000
2912
#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 25
2913
#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD          0xFC000000
2914
#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S        26
2915

2916
#define AR_MCI_MISC                                     0x1a74
2917
#define AR_MCI_MISC_HW_FIX_EN                           0x00000001
2918
#define AR_MCI_MISC_HW_FIX_EN_S                         0
2919

2920
/******************************************************************************
2921
 * WLAN BT Global Register Map
2922
******************************************************************************/
2923
#define AR_WLAN_BT_GLB_OFFSET(_x)   offsetof(struct wlan_bt_glb_reg_pcie, _x)
2924

2925
/*
2926
 * WLAN BT Global Registers
2927
 */
2928

2929
#define AR_GLB_GPIO_CONTROL                 AR_WLAN_BT_GLB_OFFSET(GLB_GPIO_CONTROL)
2930
#define AR_GLB_WLAN_WOW_STATUS              AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_STATUS)
2931
#define AR_GLB_WLAN_WOW_ENABLE              AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_ENABLE)
2932
#define AR_GLB_EMB_CPU_WOW_STATUS           AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_STATUS)
2933
#define AR_GLB_EMB_CPU_WOW_ENABLE           AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_ENABLE)
2934
#define AR_GLB_MBOX_CONTROL_STATUS          AR_WLAN_BT_GLB_OFFSET(GLB_MBOX_CONTROL_STATUS)
2935
#define AR_GLB_SW_WOW_CLK_CONTROL           AR_WLAN_BT_GLB_OFFSET(GLB_SW_WOW_CLK_CONTROL)
2936
#define AR_GLB_APB_TIMEOUT                  AR_WLAN_BT_GLB_OFFSET(GLB_APB_TIMEOUT)
2937
#define AR_GLB_OTP_LDO_CONTROL              AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_CONTROL)
2938
#define AR_GLB_OTP_LDO_POWER_GOOD           AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_POWER_GOOD)
2939
#define AR_GLB_OTP_LDO_STATUS               AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_STATUS)
2940
#define AR_GLB_SWREG_DISCONT_MODE           AR_WLAN_BT_GLB_OFFSET(GLB_SWREG_DISCONT_MODE)
2941
#define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL0   AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL0)
2942
#define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL1   AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL1)
2943
#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL0    AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL0)
2944
#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL1    AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL1)
2945
#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL2    AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL2)
2946
#define AR_GLB_SCRATCH(_ah)             \
2947
    (AR_SREV_APHRODITE(_ah)?          \
2948
        AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Aphrodite_10.GLB_SCRATCH) : \
2949
        (AR_SREV_JUPITER_20(_ah) ?          \
2950
            AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_SCRATCH) : \
2951
            AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_10.GLB_SCRATCH)))
2952

2953
#define AR_GLB_CONTROL  AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_CONTROL)
2954
#define AR_BTCOEX_CTRL_SPDT_ENABLE          0x00000001
2955
#define AR_BTCOEX_CTRL_SPDT_ENABLE_S        0
2956
#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL     0x00000002
2957
#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S   1
2958
#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT   0x00000004
2959
#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2
2960
#define AR_GLB_WLAN_UART_INTF_EN            0x00020000
2961
#define AR_GLB_WLAN_UART_INTF_EN_S          17
2962
#define AR_GLB_DS_JTAG_DISABLE              0x00040000
2963
#define AR_GLB_DS_JTAG_DISABLE_S            18
2964

2965
#define AR_GLB_STATUS   AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_STATUS)
2966

2967
/*
2968
 * MAC Version and Revision
2969
 */
2970

2971
#define AR_SREV_VERSION_OSPREY 0x1C0
2972
#define AR_SREV_VERSION_AR9580 0x1C0
2973
#define AR_SREV_VERSION_JUPITER 0x280
2974
#define AR_SREV_VERSION_HORNET 0x200
2975
#define AR_SREV_VERSION_WASP   0x300 /* XXX: Check Wasp version number */
2976
#define AR_SREV_VERSION_SCORPION 0x400
2977
#define AR_SREV_VERSION_POSEIDON 0x240
2978
#define AR_SREV_VERSION_HONEYBEE 0x500
2979
#define AR_SREV_VERSION_APHRODITE 0x2C0
2980

2981
#define AR_SREV_REVISION_OSPREY_10            0      /* Osprey 1.0 */
2982
#define AR_SREV_REVISION_OSPREY_20            2      /* Osprey 2.0/2.1 */
2983
#define AR_SREV_REVISION_OSPREY_22            3      /* Osprey 2.2 */
2984
#define AR_SREV_REVISION_AR9580_10            4      /* AR9580/Peacock 1.0 */
2985

2986
#define AR_SREV_REVISION_HORNET_10            0      /* Hornet 1.0 */
2987
#define AR_SREV_REVISION_HORNET_11            1      /* Hornet 1.1 */
2988
#define AR_SREV_REVISION_HORNET_12            2      /* Hornet 1.2 */
2989
#define AR_SREV_REVISION_HORNET_11_MASK       0xf    /* Hornet 1.1 revision mask */
2990

2991
#define AR_SREV_REVISION_POSEIDON_10          0      /* Poseidon 1.0 */
2992
#define AR_SREV_REVISION_POSEIDON_11          1      /* Poseidon 1.1 */
2993

2994
#define AR_SREV_REVISION_WASP_10              0      /* Wasp 1.0 */
2995
#define AR_SREV_REVISION_WASP_11              1      /* Wasp 1.1 */
2996
#define AR_SREV_REVISION_WASP_12              2      /* Wasp 1.2 */
2997
#define AR_SREV_REVISION_WASP_13              3      /* Wasp 1.3 */
2998
#define AR_SREV_REVISION_WASP_MASK            0xf    /* Wasp revision mask */
2999
#define AR_SREV_REVISION_WASP_MINOR_MINOR_MASK  0x10000 /* Wasp minor minor revision mask */
3000
#define AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT 16      /* Wasp minor minor revision shift */
3001

3002
#define AR_SREV_REVISION_JUPITER_10           0      /* Jupiter 1.0 */
3003
#define AR_SREV_REVISION_JUPITER_20           2      /* Jupiter 2.0 */
3004
#define AR_SREV_REVISION_JUPITER_21           3      /* Jupiter 2.1 */
3005

3006
#define AR_SREV_REVISION_HONEYBEE_10          0      /* Honeybee 1.0 */
3007
#define AR_SREV_REVISION_HONEYBEE_11          1      /* Honeybee 1.1 */
3008
#define AR_SREV_REVISION_HONEYBEE_MASK        0xf    /* Honeybee revision mask */
3009

3010
#define AR_SREV_REVISION_APHRODITE_10         0      /* Aphrodite 1.0 */
3011

3012
#if defined(AH_SUPPORT_OSPREY)
3013
#define AR_SREV_OSPREY(_ah) \
3014
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY))
3015

3016
#define AR_SREV_OSPREY_22(_ah) \
3017
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && \
3018
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OSPREY_22))
3019
#else
3020
#define AR_SREV_OSPREY(_ah)                                        0
3021
#define AR_SREV_OSPREY_10(_ah)                                     0
3022
#define AR_SREV_OSPREY_20(_ah)                                     0
3023
#define AR_SREV_OSPREY_22(_ah)                                     0
3024
#define AR_SREV_OSPREY_20_OR_LATER(_ah)                            0
3025
#define AR_SREV_OSPREY_22_OR_LATER(_ah)                            0
3026
#endif /* #if defined(AH_SUPPORT_OSPREY) */
3027

3028
#define AR_SREV_AR9580(_ah) \
3029
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \
3030
     (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_AR9580_10))
3031

3032
#define AR_SREV_AR9580_10(_ah) \
3033
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \
3034
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_AR9580_10))
3035

3036
/* NOTE: When adding chips newer than Peacock, add chip check here.  */
3037
#define AR_SREV_AR9580_10_OR_LATER(_ah) \
3038
    (AR_SREV_AR9580(_ah) || AR_SREV_SCORPION(_ah) || AR_SREV_HONEYBEE(_ah))
3039

3040
#define AR_SREV_JUPITER(_ah) \
3041
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER))
3042

3043
#define AR_SREV_JUPITER_10(_ah) \
3044
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \
3045
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_10))
3046

3047
#define AR_SREV_JUPITER_20(_ah) \
3048
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \
3049
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_20))
3050

3051
#define AR_SREV_JUPITER_21(_ah) \
3052
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \
3053
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_21))
3054

3055
#define AR_SREV_JUPITER_20_OR_LATER(_ah) \
3056
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \
3057
     (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_20))
3058

3059
#define AR_SREV_JUPITER_21_OR_LATER(_ah) \
3060
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \
3061
     (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_21))
3062

3063
#define AR_SREV_APHRODITE(_ah) \
3064
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE))
3065

3066
#define AR_SREV_APHRODITE_10(_ah) \
3067
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE) && \
3068
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_APHRODITE_10))
3069

3070
#if defined(AH_SUPPORT_HORNET)
3071
#define AR_SREV_HORNET_10(_ah) \
3072
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \
3073
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_10))
3074

3075
#define AR_SREV_HORNET_11(_ah) \
3076
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \
3077
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_11))
3078

3079
#define AR_SREV_HORNET_12(_ah) \
3080
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \
3081
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_12))
3082

3083
#define AR_SREV_HORNET(_ah) \
3084
    ( AR_SREV_HORNET_10(_ah) || AR_SREV_HORNET_11(_ah) || AR_SREV_HORNET_12(_ah) )
3085
#else
3086
#define AR_SREV_HORNET_10(_ah)                                    0
3087
#define AR_SREV_HORNET_11(_ah)                                    0
3088
#define AR_SREV_HORNET_12(_ah)                                    0
3089
#define AR_SREV_HORNET(_ah)                                       0
3090
#endif /* #if defined(AH_SUPPORT_HORNET) */
3091

3092
#if defined(AH_SUPPORT_WASP)
3093
#define AR_SREV_WASP(_ah) \
3094
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP))
3095
#else
3096
#define AR_SREV_WASP(_ah)                                         0
3097
#endif /* #if defined(AH_SUPPORT_WASP) */
3098

3099
#if defined(AH_SUPPORT_HONEYBEE)
3100
#define AR_SREV_HONEYBEE(_ah) \
3101
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE))
3102
#define AR_SREV_HONEYBEE_10(_ah) \
3103
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \
3104
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_10))
3105
#define AR_SREV_HONEYBEE_11(_ah) \
3106
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \
3107
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_11))
3108
#else
3109
#define AR_SREV_HONEYBEE(_ah)                                         0
3110
#define AR_SREV_HONEYBEE_10(_ah) 0
3111
#define AR_SREV_HONEYBEE_11(_ah) 0
3112
#endif /* #if defined(AH_SUPPORT_HONEYBEE) */
3113

3114
#define AR_SREV_WASP_10(_ah) \
3115
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \
3116
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_10))
3117

3118
#define AR_SREV_WASP_11(_ah) \
3119
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \
3120
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_11))
3121

3122
#define AR_SREV_WASP_12(_ah) \
3123
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \
3124
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_12))
3125

3126
#if defined(AH_SUPPORT_SCORPION)
3127
#define AR_SREV_SCORPION(_ah) \
3128
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SCORPION))
3129
#else
3130
#define AR_SREV_SCORPION(_ah) 0
3131
#endif /* #if defined(AH_SUPPORT_SCORPION) */
3132

3133
#if defined(AH_SUPPORT_POSEIDON)
3134
#define AR_SREV_POSEIDON(_ah) \
3135
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON))
3136

3137
#define AR_SREV_POSEIDON_10(_ah) \
3138
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \
3139
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_10))
3140

3141
#define AR_SREV_POSEIDON_11(_ah) \
3142
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \
3143
     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_11))
3144
#else
3145
#define AR_SREV_POSEIDON(_ah)                                    0
3146
#define AR_SREV_POSEIDON_10(_ah)                                 0
3147
#define AR_SREV_POSEIDON_11(_ah)                                 0
3148
#endif /* #if defined(AH_SUPPORT_POSEIDON) */
3149

3150
#define AR_SREV_POSEIDON_11_OR_LATER(_ah) \
3151
    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \
3152
     (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_POSEIDON_11))
3153

3154
#define AR_SREV_POSEIDON_OR_LATER(_ah) \
3155
    (AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_POSEIDON)
3156
#define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah) || AR_SREV_HONEYBEE(_ah))
3157
/*
3158
* Mask used to construct AAD for CCMP-AES
3159
* Cisco spec defined bits 0-3 as mask 
3160
* IEEE802.11w defined as bit 4.
3161
*/
3162
#define AR_MFP_QOS_MASK_IEEE      0x10 
3163
#define AR_MFP_QOS_MASK_CISCO     0xf
3164

3165
/*
3166
* frame control field mask:
3167
* 0 0 0 0 0 0 0 0
3168
* | | | | | | | | _ Order            bit
3169
* | | | | | | | _ _ Protected Frame  bit
3170
* | | | | | | _ _ _ More data        bit
3171
* | | | | | _ _ _ _ Power management bit
3172
* | | | | _ _ _ _ _ Retry            bit
3173
* | | | _ _ _ _ _ _ More fragments   bit
3174
* | | _ _ _ _ _ _ _ FromDS           bit
3175
* | _ _ _ _ _ _ _ _ ToDS             bit
3176
*/
3177
#define AR_AES_MUTE_MASK1_FC_MGMT_MFP 0xC7FF
3178
#endif
3179

3180
Product

Resources

Company
