Path: blob/main/sys/contrib/dev/broadcom/brcm80211/brcmsmac/phy/phy_hal.h
178701 views
// SPDX-License-Identifier: ISC1/*2* Copyright (c) 2010 Broadcom Corporation3*/45/*6* phy_hal.h: functionality exported from the phy to higher layers7*/89#ifndef _BRCM_PHY_HAL_H_10#define _BRCM_PHY_HAL_H_1112#include <brcmu_utils.h>13#include <brcmu_wifi.h>14#include <phy_shim.h>1516#define IDCODE_VER_MASK 0x0000000f17#define IDCODE_VER_SHIFT 018#define IDCODE_MFG_MASK 0x00000fff19#define IDCODE_MFG_SHIFT 020#define IDCODE_ID_MASK 0x0ffff00021#define IDCODE_ID_SHIFT 1222#define IDCODE_REV_MASK 0xf000000023#define IDCODE_REV_SHIFT 282425#define NORADIO_ID 0xe4f526#define NORADIO_IDCODE 0x4e4f52462728#define BCM2055_ID 0x205529#define BCM2055_IDCODE 0x0205500030#define BCM2055A0_IDCODE 0x1205517f3132#define BCM2056_ID 0x205633#define BCM2056_IDCODE 0x0205600034#define BCM2056A0_IDCODE 0x1205617f3536#define BCM2057_ID 0x205737#define BCM2057_IDCODE 0x0205700038#define BCM2057A0_IDCODE 0x1205717f3940#define BCM2064_ID 0x206441#define BCM2064_IDCODE 0x0206400042#define BCM2064A0_IDCODE 0x0206417f4344#define PHY_TPC_HW_OFF false45#define PHY_TPC_HW_ON true4647#define PHY_PERICAL_DRIVERUP 148#define PHY_PERICAL_WATCHDOG 249#define PHY_PERICAL_PHYINIT 350#define PHY_PERICAL_JOIN_BSS 451#define PHY_PERICAL_START_IBSS 552#define PHY_PERICAL_UP_BSS 653#define PHY_PERICAL_CHAN 754#define PHY_FULLCAL 85556#define PHY_PERICAL_DISABLE 057#define PHY_PERICAL_SPHASE 158#define PHY_PERICAL_MPHASE 259#define PHY_PERICAL_MANUAL 36061#define PHY_HOLD_FOR_ASSOC 162#define PHY_HOLD_FOR_SCAN 263#define PHY_HOLD_FOR_RM 464#define PHY_HOLD_FOR_PLT 865#define PHY_HOLD_FOR_MUTE 1666#define PHY_HOLD_FOR_NOT_ASSOC 0x206768#define PHY_MUTE_FOR_PREISM 169#define PHY_MUTE_ALL 0xffffffff7071#define PHY_NOISE_FIXED_VAL (-95)72#define PHY_NOISE_FIXED_VAL_NPHY (-92)73#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)7475#define PHY_MODE_CAL 0x000276#define PHY_MODE_NOISEM 0x00047778#define BRCMS_TXPWR_DB_FACTOR 47980/* a large TX Power as an init value to factor out of min() calculations,81* keep low enough to fit in an s8, units are .25 dBm82*/83#define BRCMS_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */8485#define BRCMS_NUM_RATES_CCK 486#define BRCMS_NUM_RATES_OFDM 887#define BRCMS_NUM_RATES_MCS_1_STREAM 888#define BRCMS_NUM_RATES_MCS_2_STREAM 889#define BRCMS_NUM_RATES_MCS_3_STREAM 890#define BRCMS_NUM_RATES_MCS_4_STREAM 89192#define BRCMS_RSSI_INVALID 0 /* invalid RSSI value */9394struct d11regs;95struct phy_shim_info;9697struct txpwr_limits {98u8 cck[BRCMS_NUM_RATES_CCK];99u8 ofdm[BRCMS_NUM_RATES_OFDM];100101u8 ofdm_cdd[BRCMS_NUM_RATES_OFDM];102103u8 ofdm_40_siso[BRCMS_NUM_RATES_OFDM];104u8 ofdm_40_cdd[BRCMS_NUM_RATES_OFDM];105106u8 mcs_20_siso[BRCMS_NUM_RATES_MCS_1_STREAM];107u8 mcs_20_cdd[BRCMS_NUM_RATES_MCS_1_STREAM];108u8 mcs_20_stbc[BRCMS_NUM_RATES_MCS_1_STREAM];109u8 mcs_20_mimo[BRCMS_NUM_RATES_MCS_2_STREAM];110111u8 mcs_40_siso[BRCMS_NUM_RATES_MCS_1_STREAM];112u8 mcs_40_cdd[BRCMS_NUM_RATES_MCS_1_STREAM];113u8 mcs_40_stbc[BRCMS_NUM_RATES_MCS_1_STREAM];114u8 mcs_40_mimo[BRCMS_NUM_RATES_MCS_2_STREAM];115u8 mcs32;116};117118struct tx_power {119u32 flags;120u16 chanspec; /* txpwr report for this channel */121u16 local_chanspec; /* channel on which we are associated */122u8 local_max; /* local max according to the AP */123u8 local_constraint; /* local constraint according to the AP */124s8 antgain[2]; /* Ant gain for each band - from SROM */125u8 rf_cores; /* count of RF Cores being reported */126u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */127u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain128* without adjustment */129u8 est_Pout_cck; /* Latest CCK tx power out estimate */130u8 tx_power_max[4]; /* Maximum target power among all rates */131/* Index of the rate with the max target power */132u8 tx_power_max_rate_ind[4];133/* User limit */134u8 user_limit[WL_TX_POWER_RATES];135/* Regulatory power limit */136u8 reg_limit[WL_TX_POWER_RATES];137/* Max power board can support (SROM) */138u8 board_limit[WL_TX_POWER_RATES];139/* Latest target power */140u8 target[WL_TX_POWER_RATES];141};142143struct brcms_chanvec {144u8 vec[MAXCHANNEL / NBBY];145};146147struct shared_phy_params {148struct si_pub *sih;149struct phy_shim_info *physhim;150uint unit;151uint corerev;152u16 vid;153u16 did;154uint chip;155uint chiprev;156uint chippkg;157uint sromrev;158uint boardtype;159uint boardrev;160u32 boardflags;161u32 boardflags2;162};163164165struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp);166struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh,167struct bcma_device *d11core, int bandtype,168struct wiphy *wiphy);169void wlc_phy_detach(struct brcms_phy_pub *ppi);170171bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype,172u16 *phyrev, u16 *radioid, u16 *radiover);173bool wlc_phy_get_encore(struct brcms_phy_pub *pih);174u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih);175176void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *ppi, bool newstate);177void wlc_phy_hw_state_upd(struct brcms_phy_pub *ppi, bool newstate);178void wlc_phy_init(struct brcms_phy_pub *ppi, u16 chanspec);179void wlc_phy_watchdog(struct brcms_phy_pub *ppi);180int wlc_phy_down(struct brcms_phy_pub *ppi);181u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih);182void wlc_phy_cal_init(struct brcms_phy_pub *ppi);183void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init);184185void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi, u16 chanspec);186u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi);187void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi, u16 newch);188void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw);189190int wlc_phy_rssi_compute(struct brcms_phy_pub *pih, struct d11rxhdr *rxh);191void wlc_phy_por_inform(struct brcms_phy_pub *ppi);192void wlc_phy_noise_sample_intr(struct brcms_phy_pub *ppi);193bool wlc_phy_bist_check_phy(struct brcms_phy_pub *ppi);194195void wlc_phy_switch_radio(struct brcms_phy_pub *ppi, bool on);196void wlc_phy_anacore(struct brcms_phy_pub *ppi, bool on);197198void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,199bool wide_filter);200void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,201struct brcms_chanvec *channels);202203void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint chan, u8 *_min_,204u8 *_max_, int rate);205void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi, struct txpwr_limits *,206u16 chanspec);207int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm, bool *override);208int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm, bool override);209void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,210struct txpwr_limits *);211bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi);212213void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain);214void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain);215u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih);216void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool val);217218void wlc_phy_cal_perical(struct brcms_phy_pub *ppi, u8 reason);219void wlc_phy_cal_papd_recal(struct brcms_phy_pub *ppi);220221void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val);222void wlc_phy_hold_upd(struct brcms_phy_pub *ppi, u32 id, bool val);223void wlc_phy_mute_upd(struct brcms_phy_pub *ppi, bool val, u32 flags);224225void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type);226227void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi,228struct tx_power *power, uint channel);229230void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal);231void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war);232void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih, bool bf_preempt);233void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap);234235const u8 *wlc_phy_get_ofdm_rate_lookup(void);236237s8 wlc_phy_get_tx_power_offset_by_mcs(struct brcms_phy_pub *ppi,238u8 mcs_offset);239s8 wlc_phy_get_tx_power_offset(struct brcms_phy_pub *ppi, u8 tbl_offset);240#endif /* _BRCM_PHY_HAL_H_ */241242243